mirror of
https://github.com/lowRISC/ibex.git
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[rtl] Add CSR module and instantiate
- This change should have no functional impact on the design - Adding the separate module will allow easy parameterization of security hardening for individual CSRs in the future - As a side benefit, clock gating is added for CSRs that didn't previously have it - Note that this change makes the cpuctrl register always present, rather than individual bits being added depending on parameterized features. This is not ideal, but the parameterization becomes rather messy otherwise. Signed-off-by: Tom Roberts <tomroberts@lowrisc.org>
This commit is contained in:
Tom Roberts
Tom Roberts
parent
8953d82ca4
commit
1a9545baaf
5 changed files with 437 additions and 195 deletions
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@ -37,6 +37,7 @@ ${PRJ_DIR}/rtl/ibex_alu.sv
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${PRJ_DIR}/rtl/ibex_branch_predict.sv
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${PRJ_DIR}/rtl/ibex_compressed_decoder.sv
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${PRJ_DIR}/rtl/ibex_controller.sv
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${PRJ_DIR}/rtl/ibex_csr.sv
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${PRJ_DIR}/rtl/ibex_cs_registers.sv
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${PRJ_DIR}/rtl/ibex_counter.sv
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${PRJ_DIR}/rtl/ibex_decoder.sv
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@ -19,6 +19,7 @@ filesets:
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- rtl/ibex_compressed_decoder.sv
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- rtl/ibex_controller.sv
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- rtl/ibex_cs_registers.sv
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- rtl/ibex_csr.sv
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- rtl/ibex_counter.sv
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- rtl/ibex_decoder.sv
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- rtl/ibex_ex_block.sv
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@ -161,7 +161,7 @@ lint_off -rule UNUSED -file "*/rtl/ibex_decoder.sv" -match "*instr_alu*"
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// Signal unoptimizable: Feedback to clock or circular logic:
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// ibex_core.cs_registers_i.mie_q
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// Issue lowrisc/ibex#212
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lint_off -rule UNOPTFLAT -file "*/rtl/ibex_cs_registers.sv" -match "*ibex_core.cs_registers_i.mie_q*"
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lint_off -rule UNOPTFLAT -file "*/rtl/ibex_csr.sv" -match "*ibex_core.cs_registers_i.u_mie_csr.rdata_q*"
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// Temporary waivers until OpenTitan primitives are lint-clean
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// https://github.com/lowRISC/opentitan/issues/2313
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@ -166,7 +166,6 @@ module ibex_cs_registers #(
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// CPU control register fields
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typedef struct packed {
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logic [31:6] unused_ctrl;
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logic [2:0] dummy_instr_mask;
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logic dummy_instr_en;
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logic data_ind_timing;
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@ -179,21 +178,32 @@ module ibex_cs_registers #(
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// CSRs
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priv_lvl_e priv_lvl_q, priv_lvl_d;
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status_t mstatus_q, mstatus_d;
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logic mstatus_en;
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irqs_t mie_q, mie_d;
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logic [31:0] mscratch_q, mscratch_d;
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logic mie_en;
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logic [31:0] mscratch_q;
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logic mscratch_en;
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logic [31:0] mepc_q, mepc_d;
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logic mepc_en;
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logic [5:0] mcause_q, mcause_d;
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logic mcause_en;
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logic [31:0] mtval_q, mtval_d;
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logic mtval_en;
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logic [31:0] mtvec_q, mtvec_d;
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logic mtvec_en;
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irqs_t mip;
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dcsr_t dcsr_q, dcsr_d;
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logic dcsr_en;
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logic [31:0] depc_q, depc_d;
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logic [31:0] dscratch0_q, dscratch0_d;
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logic [31:0] dscratch1_q, dscratch1_d;
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logic depc_en;
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logic [31:0] dscratch0_q;
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logic [31:0] dscratch1_q;
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logic dscratch0_en, dscratch1_en;
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// CSRs for recoverable NMIs
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// NOTE: these CSRS are nonstandard, see https://github.com/riscv/riscv-isa-manual/issues/261
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status_stk_t mstack_q, mstack_d;
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logic mstack_en;
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logic [31:0] mstack_epc_q, mstack_epc_d;
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logic [5:0] mstack_cause_q, mstack_cause_d;
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@ -223,7 +233,8 @@ module ibex_cs_registers #(
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logic [31:0] tmatch_value_rdata;
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// CPU control bits
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cpu_ctrl_t cpuctrl_rdata, cpuctrl_wdata;
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cpu_ctrl_t cpuctrl_q, cpuctrl_d, cpuctrl_wdata;
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logic cpuctrl_we;
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// CSR update logic
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logic [31:0] csr_wdata_int;
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@ -425,7 +436,7 @@ module ibex_cs_registers #(
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// Custom CSR for controlling CPU features
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CSR_CPUCTRL: begin
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csr_rdata_int = {cpuctrl_rdata};
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csr_rdata_int = {{32-$bits(cpu_ctrl_t){1'b0}},cpuctrl_q};
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end
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// Custom CSR for LFSR re-seeding (cannot be read)
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@ -444,31 +455,46 @@ module ibex_cs_registers #(
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exception_pc = pc_id_i;
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priv_lvl_d = priv_lvl_q;
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mstatus_en = 1'b0;
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mstatus_d = mstatus_q;
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mie_d = mie_q;
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mscratch_d = mscratch_q;
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mepc_d = mepc_q;
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mcause_d = mcause_q;
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mtval_d = mtval_q;
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mtvec_d = csr_mtvec_init_i ? {boot_addr_i[31:8], 6'b0, 2'b01} : mtvec_q;
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mie_en = 1'b0;
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mscratch_en = 1'b0;
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mepc_en = 1'b0;
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mepc_d = {csr_wdata_int[31:1], 1'b0};
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mcause_en = 1'b0;
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mcause_d = {csr_wdata_int[31], csr_wdata_int[4:0]};
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mtval_en = 1'b0;
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mtval_d = csr_wdata_int;
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mtvec_en = csr_mtvec_init_i;
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// mtvec.MODE set to vectored
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// mtvec.BASE must be 256-byte aligned
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mtvec_d = csr_mtvec_init_i ? {boot_addr_i[31:8], 6'b0, 2'b01} :
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{csr_wdata_int[31:8], 6'b0, 2'b01};
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dcsr_en = 1'b0;
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dcsr_d = dcsr_q;
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depc_d = depc_q;
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dscratch0_d = dscratch0_q;
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dscratch1_d = dscratch1_q;
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depc_d = {csr_wdata_int[31:1], 1'b0};
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depc_en = 1'b0;
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dscratch0_en = 1'b0;
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dscratch1_en = 1'b0;
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mstack_d = mstack_q;
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mstack_epc_d = mstack_epc_q;
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mstack_cause_d = mstack_cause_q;
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mstack_en = 1'b0;
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mstack_d.mpie = mstatus_q.mpie;
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mstack_d.mpp = mstatus_q.mpp;
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mstack_epc_d = mepc_q;
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mstack_cause_d = mcause_q;
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mcountinhibit_we = 1'b0;
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mhpmcounter_we = '0;
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mhpmcounterh_we = '0;
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cpuctrl_we = 1'b0;
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if (csr_we_int) begin
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unique case (csr_addr_i)
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// mstatus: IE bit
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CSR_MSTATUS: begin
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mstatus_d = '{
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mstatus_en = 1'b1;
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mstatus_d = '{
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mie: csr_wdata_int[CSR_MSTATUS_MIE_BIT],
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mpie: csr_wdata_int[CSR_MSTATUS_MPIE_BIT],
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mpp: priv_lvl_e'(csr_wdata_int[CSR_MSTATUS_MPP_BIT_HIGH:CSR_MSTATUS_MPP_BIT_LOW]),
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@ -482,28 +508,21 @@ module ibex_cs_registers #(
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end
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// interrupt enable
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CSR_MIE: begin
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mie_d.irq_software = csr_wdata_int[CSR_MSIX_BIT];
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mie_d.irq_timer = csr_wdata_int[CSR_MTIX_BIT];
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mie_d.irq_external = csr_wdata_int[CSR_MEIX_BIT];
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mie_d.irq_fast = csr_wdata_int[CSR_MFIX_BIT_HIGH:CSR_MFIX_BIT_LOW];
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end
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CSR_MIE: mie_en = 1'b1;
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CSR_MSCRATCH: mscratch_d = csr_wdata_int;
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CSR_MSCRATCH: mscratch_en = 1'b1;
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// mepc: exception program counter
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CSR_MEPC: mepc_d = {csr_wdata_int[31:1], 1'b0};
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CSR_MEPC: mepc_en = 1'b1;
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// mcause
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CSR_MCAUSE: mcause_d = {csr_wdata_int[31], csr_wdata_int[4:0]};
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CSR_MCAUSE: mcause_en = 1'b1;
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// mtval: trap value
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CSR_MTVAL: mtval_d = csr_wdata_int;
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CSR_MTVAL: mtval_en = 1'b1;
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// mtvec
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// mtvec.MODE set to vectored
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// mtvec.BASE must be 256-byte aligned
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CSR_MTVEC: mtvec_d = {csr_wdata_int[31:8], 6'b0, 2'b01};
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CSR_MTVEC: mtvec_en = 1'b1;
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CSR_DCSR: begin
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dcsr_d = csr_wdata_int;
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@ -523,13 +542,14 @@ module ibex_cs_registers #(
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dcsr_d.zero0 = 1'b0;
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dcsr_d.zero1 = 1'b0;
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dcsr_d.zero2 = 12'h0;
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dcsr_en = 1'b1;
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end
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// dpc: debug program counter
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CSR_DPC: depc_d = {csr_wdata_int[31:1], 1'b0};
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CSR_DPC: depc_en = 1'b1;
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CSR_DSCRATCH0: dscratch0_d = csr_wdata_int;
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CSR_DSCRATCH1: dscratch1_d = csr_wdata_int;
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CSR_DSCRATCH0: dscratch0_en = 1'b1;
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CSR_DSCRATCH1: dscratch1_en = 1'b1;
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// machine counter/timers
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CSR_MCOUNTINHIBIT: mcountinhibit_we = 1'b1;
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@ -560,6 +580,8 @@ module ibex_cs_registers #(
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mhpmcounterh_we[mhpmcounter_idx] = 1'b1;
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end
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CSR_CPUCTRL: cpuctrl_we = 1'b1;
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default:;
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endcase
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end
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@ -589,22 +611,25 @@ module ibex_cs_registers #(
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// do not update cause, epc, tval, epc and status
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dcsr_d.prv = priv_lvl_q;
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dcsr_d.cause = debug_cause_i;
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dcsr_en = 1'b1;
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depc_d = exception_pc;
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depc_en = 1'b1;
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end else if (!debug_mode_i) begin
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// In debug mode, "exceptions do not update any registers. That
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// includes cause, epc, tval, dpc and mstatus." [Debug Spec v0.13.2, p.39]
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mtval_en = 1'b1;
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mtval_d = csr_mtval_i;
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mstatus_en = 1'b1;
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mstatus_d.mie = 1'b0; // disable interrupts
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// save current status
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mstatus_d.mpie = mstatus_q.mie;
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mstatus_d.mpp = priv_lvl_q;
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mepc_en = 1'b1;
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mepc_d = exception_pc;
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mcause_en = 1'b1;
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mcause_d = {csr_mcause_i};
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// save previous status for recoverable NMI
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mstack_d.mpie = mstatus_q.mpie;
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mstack_d.mpp = mstatus_q.mpp;
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mstack_epc_d = mepc_q;
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mstack_cause_d = mcause_q;
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mstack_en = 1'b1;
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end
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end // csr_save_cause_i
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@ -614,13 +639,16 @@ module ibex_cs_registers #(
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csr_restore_mret_i: begin // MRET
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priv_lvl_d = mstatus_q.mpp;
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mstatus_en = 1'b1;
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mstatus_d.mie = mstatus_q.mpie; // re-enable interrupts
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if (nmi_mode_i) begin
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// when returning from an NMI restore state from mstack CSR
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mstatus_d.mpie = mstack_q.mpie;
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mstatus_d.mpp = mstack_q.mpp;
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mepc_en = 1'b1;
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mepc_d = mstack_epc_q;
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mcause_en = 1'b1;
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mcause_d = mstack_cause_q;
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end else begin
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// otherwise just set mstatus.MPIE/MPP
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@ -634,6 +662,22 @@ module ibex_cs_registers #(
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endcase
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end
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// Update current priv level
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always_ff @(posedge clk_i or negedge rst_ni) begin
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if (!rst_ni) begin
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priv_lvl_q <= PRIV_LVL_M;
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end else begin
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priv_lvl_q <= priv_lvl_d;
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end
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end
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// Send current priv level to the decoder
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assign priv_mode_id_o = priv_lvl_q;
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// New instruction fetches need to account for updates to priv_lvl_q this cycle
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assign priv_mode_if_o = priv_lvl_d;
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// Load/store instructions must factor in MPRV for PMP checking
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assign priv_mode_lsu_o = mstatus_q.mprv ? mstatus_q.mpp : priv_lvl_q;
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// CSR operation logic
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always_comb begin
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unique case (csr_op_i)
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@ -671,68 +715,224 @@ module ibex_cs_registers #(
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assign irqs_o = mip & mie_q;
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assign irq_pending_o = |irqs_o;
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// actual registers
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always_ff @(posedge clk_i or negedge rst_ni) begin
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if (!rst_ni) begin
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priv_lvl_q <= PRIV_LVL_M;
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mstatus_q <= '{
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mie: 1'b0,
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mpie: 1'b1,
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mpp: PRIV_LVL_U,
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mprv: 1'b0,
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tw: 1'b0
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};
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mie_q <= '0;
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mscratch_q <= '0;
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mepc_q <= '0;
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mcause_q <= '0;
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mtval_q <= '0;
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mtvec_q <= 32'h0000_0001;
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dcsr_q <= '{
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xdebugver: XDEBUGVER_STD,
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cause: DBG_CAUSE_NONE, // 3'h0
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prv: PRIV_LVL_M,
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default: '0
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};
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depc_q <= '0;
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dscratch0_q <= '0;
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dscratch1_q <= '0;
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////////////////////////
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// CSR instantiations //
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////////////////////////
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mstack_q <= '{
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mpie: 1'b1,
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mpp: PRIV_LVL_U
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};
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mstack_epc_q <= '0;
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mstack_cause_q <= '0;
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// MSTATUS
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localparam status_t MSTATUS_RST_VAL = '{mie: 1'b0,
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mpie: 1'b1,
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mpp: PRIV_LVL_U,
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mprv: 1'b0,
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tw: 1'b0};
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ibex_csr #(
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.Width ($bits(status_t)),
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.ShadowCopy (1'b0),
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.ResetValue ({MSTATUS_RST_VAL})
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) u_mstatus_csr (
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.clk_i (clk_i),
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.rst_ni (rst_ni),
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.wr_data_i ({mstatus_d}),
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.wr_en_i (mstatus_en),
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.rd_data_o (mstatus_q),
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.rd_error_o ()
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);
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end else begin
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// update CSRs
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priv_lvl_q <= priv_lvl_d;
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mstatus_q <= mstatus_d;
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mie_q <= mie_d;
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mscratch_q <= mscratch_d;
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mepc_q <= mepc_d;
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mcause_q <= mcause_d;
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mtval_q <= mtval_d;
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mtvec_q <= mtvec_d;
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dcsr_q <= dcsr_d;
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depc_q <= depc_d;
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dscratch0_q <= dscratch0_d;
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dscratch1_q <= dscratch1_d;
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// MEPC
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ibex_csr #(
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.Width (32),
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.ShadowCopy (1'b0),
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.ResetValue ('0)
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) u_mepc_csr (
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.clk_i (clk_i),
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.rst_ni (rst_ni),
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.wr_data_i (mepc_d),
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.wr_en_i (mepc_en),
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.rd_data_o (mepc_q),
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.rd_error_o ()
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);
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mstack_q <= mstack_d;
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mstack_epc_q <= mstack_epc_d;
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mstack_cause_q <= mstack_cause_d;
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// MIE
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assign mie_d.irq_software = csr_wdata_int[CSR_MSIX_BIT];
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assign mie_d.irq_timer = csr_wdata_int[CSR_MTIX_BIT];
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assign mie_d.irq_external = csr_wdata_int[CSR_MEIX_BIT];
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assign mie_d.irq_fast = csr_wdata_int[CSR_MFIX_BIT_HIGH:CSR_MFIX_BIT_LOW];
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ibex_csr #(
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.Width ($bits(irqs_t)),
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.ShadowCopy (1'b0),
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.ResetValue ('0)
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) u_mie_csr (
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.clk_i (clk_i),
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.rst_ni (rst_ni),
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.wr_data_i ({mie_d}),
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.wr_en_i (mie_en),
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.rd_data_o (mie_q),
|
||||
.rd_error_o ()
|
||||
);
|
||||
|
||||
end
|
||||
end
|
||||
// MSCRATCH
|
||||
ibex_csr #(
|
||||
.Width (32),
|
||||
.ShadowCopy (1'b0),
|
||||
.ResetValue ('0)
|
||||
) u_mscratch_csr (
|
||||
.clk_i (clk_i),
|
||||
.rst_ni (rst_ni),
|
||||
.wr_data_i (csr_wdata_int),
|
||||
.wr_en_i (mscratch_en),
|
||||
.rd_data_o (mscratch_q),
|
||||
.rd_error_o ()
|
||||
);
|
||||
|
||||
// Send current priv level to the decoder
|
||||
assign priv_mode_id_o = priv_lvl_q;
|
||||
// New instruction fetches need to account for updates to priv_lvl_q this cycle
|
||||
assign priv_mode_if_o = priv_lvl_d;
|
||||
// Load/store instructions must factor in MPRV for PMP checking
|
||||
assign priv_mode_lsu_o = mstatus_q.mprv ? mstatus_q.mpp : priv_lvl_q;
|
||||
// MCAUSE
|
||||
ibex_csr #(
|
||||
.Width (6),
|
||||
.ShadowCopy (1'b0),
|
||||
.ResetValue ('0)
|
||||
) u_mcause_csr (
|
||||
.clk_i (clk_i),
|
||||
.rst_ni (rst_ni),
|
||||
.wr_data_i (mcause_d),
|
||||
.wr_en_i (mcause_en),
|
||||
.rd_data_o (mcause_q),
|
||||
.rd_error_o ()
|
||||
);
|
||||
|
||||
// MTVAL
|
||||
ibex_csr #(
|
||||
.Width (32),
|
||||
.ShadowCopy (1'b0),
|
||||
.ResetValue ('0)
|
||||
) u_mtval_csr (
|
||||
.clk_i (clk_i),
|
||||
.rst_ni (rst_ni),
|
||||
.wr_data_i (mtval_d),
|
||||
.wr_en_i (mtval_en),
|
||||
.rd_data_o (mtval_q),
|
||||
.rd_error_o ()
|
||||
);
|
||||
|
||||
// MTVEC
|
||||
ibex_csr #(
|
||||
.Width (32),
|
||||
.ShadowCopy (1'b0),
|
||||
.ResetValue (32'd1)
|
||||
) u_mtvec_csr (
|
||||
.clk_i (clk_i),
|
||||
.rst_ni (rst_ni),
|
||||
.wr_data_i (mtvec_d),
|
||||
.wr_en_i (mtvec_en),
|
||||
.rd_data_o (mtvec_q),
|
||||
.rd_error_o ()
|
||||
);
|
||||
|
||||
// DCSR
|
||||
localparam dcsr_t DCSR_RESET_VAL = '{
|
||||
xdebugver: XDEBUGVER_STD,
|
||||
cause: DBG_CAUSE_NONE, // 3'h0
|
||||
prv: PRIV_LVL_M,
|
||||
default: '0
|
||||
};
|
||||
ibex_csr #(
|
||||
.Width ($bits(dcsr_t)),
|
||||
.ShadowCopy (1'b0),
|
||||
.ResetValue ({DCSR_RESET_VAL})
|
||||
) u_dcsr_csr (
|
||||
.clk_i (clk_i),
|
||||
.rst_ni (rst_ni),
|
||||
.wr_data_i ({dcsr_d}),
|
||||
.wr_en_i (dcsr_en),
|
||||
.rd_data_o (dcsr_q),
|
||||
.rd_error_o ()
|
||||
);
|
||||
|
||||
// DEPC
|
||||
ibex_csr #(
|
||||
.Width (32),
|
||||
.ShadowCopy (1'b0),
|
||||
.ResetValue ('0)
|
||||
) u_depc_csr (
|
||||
.clk_i (clk_i),
|
||||
.rst_ni (rst_ni),
|
||||
.wr_data_i (depc_d),
|
||||
.wr_en_i (depc_en),
|
||||
.rd_data_o (depc_q),
|
||||
.rd_error_o ()
|
||||
);
|
||||
|
||||
// DSCRATCH0
|
||||
ibex_csr #(
|
||||
.Width (32),
|
||||
.ShadowCopy (1'b0),
|
||||
.ResetValue ('0)
|
||||
) u_dscratch0_csr (
|
||||
.clk_i (clk_i),
|
||||
.rst_ni (rst_ni),
|
||||
.wr_data_i (csr_wdata_int),
|
||||
.wr_en_i (dscratch0_en),
|
||||
.rd_data_o (dscratch0_q),
|
||||
.rd_error_o ()
|
||||
);
|
||||
|
||||
// DSCRATCH1
|
||||
ibex_csr #(
|
||||
.Width (32),
|
||||
.ShadowCopy (1'b0),
|
||||
.ResetValue ('0)
|
||||
) u_dscratch1_csr (
|
||||
.clk_i (clk_i),
|
||||
.rst_ni (rst_ni),
|
||||
.wr_data_i (csr_wdata_int),
|
||||
.wr_en_i (dscratch1_en),
|
||||
.rd_data_o (dscratch1_q),
|
||||
.rd_error_o ()
|
||||
);
|
||||
|
||||
// MSTACK
|
||||
localparam status_stk_t MSTACK_RESET_VAL = '{
|
||||
mpie: 1'b1,
|
||||
mpp: PRIV_LVL_U
|
||||
};
|
||||
ibex_csr #(
|
||||
.Width ($bits(status_stk_t)),
|
||||
.ShadowCopy (1'b0),
|
||||
.ResetValue ({MSTACK_RESET_VAL})
|
||||
) u_mstack_csr (
|
||||
.clk_i (clk_i),
|
||||
.rst_ni (rst_ni),
|
||||
.wr_data_i ({mstack_d}),
|
||||
.wr_en_i (mstack_en),
|
||||
.rd_data_o (mstack_q),
|
||||
.rd_error_o ()
|
||||
);
|
||||
|
||||
// MSTACK_EPC
|
||||
ibex_csr #(
|
||||
.Width (32),
|
||||
.ShadowCopy (1'b0),
|
||||
.ResetValue ('0)
|
||||
) u_mstack_epc_csr (
|
||||
.clk_i (clk_i),
|
||||
.rst_ni (rst_ni),
|
||||
.wr_data_i (mstack_epc_d),
|
||||
.wr_en_i (mstack_en),
|
||||
.rd_data_o (mstack_epc_q),
|
||||
.rd_error_o ()
|
||||
);
|
||||
|
||||
// MSTACK_CAUSE
|
||||
ibex_csr #(
|
||||
.Width (6),
|
||||
.ShadowCopy (1'b0),
|
||||
.ResetValue ('0)
|
||||
) u_mstack_cause_csr (
|
||||
.clk_i (clk_i),
|
||||
.rst_ni (rst_ni),
|
||||
.wr_data_i (mstack_cause_d),
|
||||
.wr_en_i (mstack_en),
|
||||
.rd_data_o (mstack_cause_q),
|
||||
.rd_error_o ()
|
||||
);
|
||||
|
||||
// -----------------
|
||||
// PMP registers
|
||||
|
|
@ -814,13 +1014,18 @@ module ibex_cs_registers #(
|
|||
assign pmp_cfg_wdata[i].write = &csr_wdata_int[(i%4)*PMP_CFG_W+:2];
|
||||
assign pmp_cfg_wdata[i].read = csr_wdata_int[(i%4)*PMP_CFG_W];
|
||||
|
||||
always_ff @(posedge clk_i or negedge rst_ni) begin
|
||||
if (!rst_ni) begin
|
||||
pmp_cfg[i] <= pmp_cfg_t'('b0);
|
||||
end else if (pmp_cfg_we[i]) begin
|
||||
pmp_cfg[i] <= pmp_cfg_wdata[i];
|
||||
end
|
||||
end
|
||||
ibex_csr #(
|
||||
.Width ($bits(pmp_cfg_t)),
|
||||
.ShadowCopy (1'b0),
|
||||
.ResetValue ('0)
|
||||
) u_pmp_cfg_csr (
|
||||
.clk_i (clk_i),
|
||||
.rst_ni (rst_ni),
|
||||
.wr_data_i ({pmp_cfg_wdata[i]}),
|
||||
.wr_en_i (pmp_cfg_we[i]),
|
||||
.rd_data_o (pmp_cfg[i]),
|
||||
.rd_error_o ()
|
||||
);
|
||||
|
||||
// --------------------------
|
||||
// Instantiate addr registers
|
||||
|
|
@ -834,13 +1039,19 @@ module ibex_cs_registers #(
|
|||
(csr_addr == (CSR_OFF_PMP_ADDR + i[11:0]));
|
||||
end
|
||||
|
||||
always_ff @(posedge clk_i or negedge rst_ni) begin
|
||||
if (!rst_ni) begin
|
||||
pmp_addr[i] <= 'b0;
|
||||
end else if (pmp_addr_we[i]) begin
|
||||
pmp_addr[i] <= csr_wdata_int;
|
||||
end
|
||||
end
|
||||
ibex_csr #(
|
||||
.Width (32),
|
||||
.ShadowCopy (1'b0),
|
||||
.ResetValue ('0)
|
||||
) u_pmp_addr_csr (
|
||||
.clk_i (clk_i),
|
||||
.rst_ni (rst_ni),
|
||||
.wr_data_i (csr_wdata_int),
|
||||
.wr_en_i (pmp_addr_we[i]),
|
||||
.rd_data_o (pmp_addr[i]),
|
||||
.rd_error_o ()
|
||||
);
|
||||
|
||||
assign csr_pmp_cfg_o[i] = pmp_cfg[i];
|
||||
assign csr_pmp_addr_o[i] = {pmp_addr[i],2'b00};
|
||||
end
|
||||
|
|
@ -997,27 +1208,35 @@ module ibex_cs_registers #(
|
|||
assign tmatch_value_we = csr_we_int & debug_mode_i & (csr_addr_i == CSR_TDATA2);
|
||||
|
||||
// tmatch_control is enabled when the execute bit is set
|
||||
assign tmatch_control_d = tmatch_control_we ? csr_wdata_int[2] :
|
||||
tmatch_control_q;
|
||||
// tmatch_value has its own clock gate
|
||||
assign tmatch_control_d = csr_wdata_int[2];
|
||||
assign tmatch_value_d = csr_wdata_int[31:0];
|
||||
|
||||
// Registers
|
||||
always_ff @(posedge clk_i or negedge rst_ni) begin
|
||||
if (!rst_ni) begin
|
||||
tmatch_control_q <= 'b0;
|
||||
end else begin
|
||||
tmatch_control_q <= tmatch_control_d;
|
||||
end
|
||||
end
|
||||
ibex_csr #(
|
||||
.Width (1),
|
||||
.ShadowCopy (1'b0),
|
||||
.ResetValue ('0)
|
||||
) u_tmatch_control_csr (
|
||||
.clk_i (clk_i),
|
||||
.rst_ni (rst_ni),
|
||||
.wr_data_i (tmatch_control_d),
|
||||
.wr_en_i (tmatch_control_we),
|
||||
.rd_data_o (tmatch_control_q),
|
||||
.rd_error_o ()
|
||||
);
|
||||
|
||||
always_ff @(posedge clk_i or negedge rst_ni) begin
|
||||
if (!rst_ni) begin
|
||||
tmatch_value_q <= 'b0;
|
||||
end else if (tmatch_value_we) begin
|
||||
tmatch_value_q <= tmatch_value_d;
|
||||
end
|
||||
end
|
||||
ibex_csr #(
|
||||
.Width (32),
|
||||
.ShadowCopy (1'b0),
|
||||
.ResetValue ('0)
|
||||
) u_tmatch_value_csr (
|
||||
.clk_i (clk_i),
|
||||
.rst_ni (rst_ni),
|
||||
.wr_data_i (tmatch_value_d),
|
||||
.wr_en_i (tmatch_value_we),
|
||||
.rd_data_o (tmatch_value_q),
|
||||
.rd_error_o ()
|
||||
);
|
||||
|
||||
// Assign read data
|
||||
// TSELECT - only one supported
|
||||
|
|
@ -1054,27 +1273,16 @@ module ibex_cs_registers #(
|
|||
assign trigger_match_o = 'b0;
|
||||
end
|
||||
|
||||
// CPU control fields
|
||||
assign cpuctrl_rdata.unused_ctrl = '0;
|
||||
//////////////////////////
|
||||
// CPU control register //
|
||||
//////////////////////////
|
||||
|
||||
// Cast register write data
|
||||
assign cpuctrl_wdata = cpu_ctrl_t'(csr_wdata_int);
|
||||
assign cpuctrl_wdata = cpu_ctrl_t'(csr_wdata_int[$bits(cpu_ctrl_t)-1:0]);
|
||||
|
||||
// Generate fixed time execution bit
|
||||
if (DataIndTiming) begin : gen_dit
|
||||
logic data_ind_timing_d, data_ind_timing_q;
|
||||
|
||||
assign data_ind_timing_d = (csr_we_int && (csr_addr == CSR_CPUCTRL)) ?
|
||||
cpuctrl_wdata.data_ind_timing : data_ind_timing_q;
|
||||
|
||||
always_ff @(posedge clk_i or negedge rst_ni) begin
|
||||
if (!rst_ni) begin
|
||||
data_ind_timing_q <= 1'b0; // disabled on reset
|
||||
end else begin
|
||||
data_ind_timing_q <= data_ind_timing_d;
|
||||
end
|
||||
end
|
||||
|
||||
assign cpuctrl_rdata.data_ind_timing = data_ind_timing_q;
|
||||
assign cpuctrl_d.data_ind_timing = cpuctrl_wdata.data_ind_timing;
|
||||
|
||||
end else begin : gen_no_dit
|
||||
// tieoff for the unused bit
|
||||
|
|
@ -1082,34 +1290,16 @@ module ibex_cs_registers #(
|
|||
assign unused_dit = cpuctrl_wdata.data_ind_timing;
|
||||
|
||||
// field will always read as zero if not configured
|
||||
assign cpuctrl_rdata.data_ind_timing = 1'b0;
|
||||
assign cpuctrl_d.data_ind_timing = 1'b0;
|
||||
end
|
||||
|
||||
assign data_ind_timing_o = cpuctrl_rdata.data_ind_timing;
|
||||
assign data_ind_timing_o = cpuctrl_q.data_ind_timing;
|
||||
|
||||
// Generate dummy instruction signals
|
||||
if (DummyInstructions) begin : gen_dummy
|
||||
logic dummy_instr_en_d, dummy_instr_en_q;
|
||||
logic [2:0] dummy_instr_mask_d, dummy_instr_mask_q;
|
||||
assign cpuctrl_d.dummy_instr_en = cpuctrl_wdata.dummy_instr_en;
|
||||
assign cpuctrl_d.dummy_instr_mask = cpuctrl_wdata.dummy_instr_mask;
|
||||
|
||||
assign dummy_instr_en_d = (csr_we_int && (csr_addr == CSR_CPUCTRL)) ?
|
||||
cpuctrl_wdata.dummy_instr_en : dummy_instr_en_q;
|
||||
|
||||
assign dummy_instr_mask_d = (csr_we_int && (csr_addr == CSR_CPUCTRL)) ?
|
||||
cpuctrl_wdata.dummy_instr_mask : dummy_instr_mask_q;
|
||||
|
||||
always_ff @(posedge clk_i or negedge rst_ni) begin
|
||||
if (!rst_ni) begin
|
||||
dummy_instr_en_q <= 1'b0; // disabled on reset
|
||||
dummy_instr_mask_q <= 3'b000;
|
||||
end else begin
|
||||
dummy_instr_en_q <= dummy_instr_en_d;
|
||||
dummy_instr_mask_q <= dummy_instr_mask_d;
|
||||
end
|
||||
end
|
||||
|
||||
assign cpuctrl_rdata.dummy_instr_en = dummy_instr_en_q;
|
||||
assign cpuctrl_rdata.dummy_instr_mask = dummy_instr_mask_q;
|
||||
// Signal a write to the seed register
|
||||
assign dummy_instr_seed_en_o = csr_we_int && (csr_addr == CSR_SECURESEED);
|
||||
assign dummy_instr_seed_o = csr_wdata_int;
|
||||
|
|
@ -1122,48 +1312,41 @@ module ibex_cs_registers #(
|
|||
assign unused_dummy_mask = cpuctrl_wdata.dummy_instr_mask;
|
||||
|
||||
// field will always read as zero if not configured
|
||||
assign cpuctrl_rdata.dummy_instr_en = 1'b0;
|
||||
assign cpuctrl_rdata.dummy_instr_mask = 3'b000;
|
||||
assign dummy_instr_seed_en_o = 1'b0;
|
||||
assign dummy_instr_seed_o = '0;
|
||||
assign cpuctrl_d.dummy_instr_en = 1'b0;
|
||||
assign cpuctrl_d.dummy_instr_mask = 3'b000;
|
||||
assign dummy_instr_seed_en_o = 1'b0;
|
||||
assign dummy_instr_seed_o = '0;
|
||||
end
|
||||
|
||||
assign dummy_instr_en_o = cpuctrl_rdata.dummy_instr_en;
|
||||
assign dummy_instr_mask_o = cpuctrl_rdata.dummy_instr_mask;
|
||||
assign dummy_instr_en_o = cpuctrl_q.dummy_instr_en;
|
||||
assign dummy_instr_mask_o = cpuctrl_q.dummy_instr_mask;
|
||||
|
||||
// Generate icache enable bit
|
||||
if (ICache) begin : gen_icache_enable
|
||||
logic icache_enable_d, icache_enable_q;
|
||||
|
||||
// Update the value when cpuctrl register is written
|
||||
assign icache_enable_d = (csr_we_int & (csr_addr == CSR_CPUCTRL)) ?
|
||||
cpuctrl_wdata.icache_enable : icache_enable_q;
|
||||
|
||||
always_ff @(posedge clk_i or negedge rst_ni) begin
|
||||
if (!rst_ni) begin
|
||||
icache_enable_q <= 1'b0; // disabled on reset
|
||||
end else begin
|
||||
icache_enable_q <= icache_enable_d;
|
||||
end
|
||||
end
|
||||
|
||||
assign cpuctrl_rdata.icache_enable = icache_enable_q;
|
||||
|
||||
assign cpuctrl_d.icache_enable = cpuctrl_wdata.icache_enable;
|
||||
end else begin : gen_no_icache
|
||||
// tieoff for the unused icen bit
|
||||
logic unused_icen;
|
||||
assign unused_icen = cpuctrl_wdata.icache_enable;
|
||||
|
||||
// icen field will always read as zero if ICache not configured
|
||||
assign cpuctrl_rdata.icache_enable = 1'b0;
|
||||
assign cpuctrl_d.icache_enable = 1'b0;
|
||||
end
|
||||
|
||||
assign icache_enable_o = cpuctrl_rdata.icache_enable;
|
||||
|
||||
// tieoff for the currently unused bits of cpuctrl
|
||||
logic [31:6] unused_cpuctrl;
|
||||
assign unused_cpuctrl = {cpuctrl_wdata[31:6]};
|
||||
assign icache_enable_o = cpuctrl_q.icache_enable;
|
||||
|
||||
ibex_csr #(
|
||||
.Width ($bits(cpu_ctrl_t)),
|
||||
.ShadowCopy (1'b0),
|
||||
.ResetValue ('0)
|
||||
) u_cpuctrl_csr (
|
||||
.clk_i (clk_i),
|
||||
.rst_ni (rst_ni),
|
||||
.wr_data_i ({cpuctrl_d}),
|
||||
.wr_en_i (cpuctrl_we),
|
||||
.rd_data_o (cpuctrl_q),
|
||||
.rd_error_o ()
|
||||
);
|
||||
|
||||
////////////////
|
||||
// Assertions //
|
||||
|
|
|
|||
57
rtl/ibex_csr.sv
Normal file
57
rtl/ibex_csr.sv
Normal file
|
|
@ -0,0 +1,57 @@
|
|||
// Copyright lowRISC contributors.
|
||||
// Licensed under the Apache License, Version 2.0, see LICENSE for details.
|
||||
// SPDX-License-Identifier: Apache-2.0
|
||||
|
||||
/**
|
||||
* Control / status register primitive
|
||||
*/
|
||||
|
||||
`include "prim_assert.sv"
|
||||
|
||||
module ibex_csr #(
|
||||
parameter int unsigned Width = 32,
|
||||
parameter bit ShadowCopy = 1'b0,
|
||||
parameter bit [Width-1:0] ResetValue = '0
|
||||
) (
|
||||
input logic clk_i,
|
||||
input logic rst_ni,
|
||||
|
||||
input logic [Width-1:0] wr_data_i,
|
||||
input logic wr_en_i,
|
||||
output logic [Width-1:0] rd_data_o,
|
||||
|
||||
output logic rd_error_o
|
||||
);
|
||||
|
||||
logic [Width-1:0] rdata_q;
|
||||
|
||||
always_ff @(posedge clk_i or negedge rst_ni) begin
|
||||
if (!rst_ni) begin
|
||||
rdata_q <= ResetValue;
|
||||
end else if (wr_en_i) begin
|
||||
rdata_q <= wr_data_i;
|
||||
end
|
||||
end
|
||||
|
||||
assign rd_data_o = rdata_q;
|
||||
|
||||
if (ShadowCopy) begin : gen_shadow
|
||||
logic [Width-1:0] shadow_q;
|
||||
|
||||
always_ff @(posedge clk_i or negedge rst_ni) begin
|
||||
if (!rst_ni) begin
|
||||
shadow_q <= ~ResetValue;
|
||||
end else if (wr_en_i) begin
|
||||
shadow_q <= ~wr_data_i;
|
||||
end
|
||||
end
|
||||
|
||||
assign rd_error_o = rdata_q != ~shadow_q;
|
||||
|
||||
end else begin : gen_no_shadow
|
||||
assign rd_error_o = 1'b0;
|
||||
end
|
||||
|
||||
`ASSERT_KNOWN(IbexCSREnValid, wr_en_i)
|
||||
|
||||
endmodule
|
||||
Loading…
Add table
Add a link
Reference in a new issue