Enable the use of Verible through fusesoc

Run

```
fusesoc --cores-root . run --no-export --target=format --tool=veribleformat lowrisc:ibex:ibex_core
```

to format all source code with Verible's verilog_format tool.

azure-pipelines.yml

@@ -133,6 +133,19 @@ jobs:
     continueOnError: true
     displayName: Lint Verilog source files with Verible (experimental)
 
+  - bash: |
+      fusesoc --cores-root . run --no-export --target=format --tool=veribleformat lowrisc:ibex:ibex_core_tracing
+      if [ $? != 0 ]; then
+        echo -n "##vso[task.logissue type=error]"
+        echo "Verilog format with Verible failed. Run 'fusesoc --cores-root . run --no-export --target=format --tool=veribleformat lowrisc:ibex:ibex_core_tracing' to check and fix all errors."
+        echo "This flow is currently experimental and failures can be ignored."
+      fi
+      # Show diff of what verilog_format would have changed, and then revert.
+      git diff
+      git reset --hard HEAD
+    continueOnError: true
+    displayName: Format all source code with Verible format (experimental)
+
   - bash: |
       fork_origin=$(git merge-base --fork-point origin/master)
       changed_files=$(git diff --name-only $fork_origin | grep -v '^vendor' | grep -E '\.(cpp|cc|c|h)$')

ibex_core.core

@@ -108,3 +108,15 @@ targets:
         ruleset: default
         rules:
           - "-parameter-name-style"
+  format:
+    filesets:
+      - files_rtl
+    parameters:
+      - SYNTHESIS=true
+      - RVFI=true
+    default_tool: veribleformat
+    toplevel: ibex_core
+    tools:
+      veribleformat:
+        verible_format_args:
+          - "--inplace"

ibex_core_tracing.core

@@ -83,3 +83,15 @@ targets:
         ruleset: default
         rules:
           - "-parameter-name-style"
+  format:
+    filesets:
+      - files_rtl
+    parameters:
+      - SYNTHESIS=true
+      - RVFI=true
+    default_tool: veribleformat
+    toplevel: ibex_core
+    tools:
+      veribleformat:
+        verible_format_args:
+          - "--inplace"