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Add RV32IM test (#404)

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taoliug 2019-10-16 10:15:49 -07:00 • committed by GitHub
parent 59fdbb517f
commit 1b71320230
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dv/uvm/riscv_dv_extension/testlist.yaml
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@ -353,3 +353,14 @@
compare_opts:
compare_final_value_only: 1
verbose: 1
- test: riscv_rv32im_instr_test
description: >
Random instruction test without compressed instructions
iterations: 5
gen_test: riscv_rand_instr_test
gen_opts: >
+disable_compressed_instr=1
gcc_opts: >
-march=rv32im
rtl_test: core_ibex_base_test