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Remove mscratch and change the way csr works

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This commit is contained in:
Andreas Traber 2015-12-26 00:15:00 +01:00
parent 49532dfa79
commit 1b98c11e12
5 changed files with 29 additions and 51 deletions
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27
cs_registers.sv
View file

@ -116,8 +116,7 @@ module riscv_cs_registers
logic is_pcmr;
// Generic CSRs
logic [31:0] csr [0:`CSR_MAX_IDX];
logic [31:0] csr_n [0:`CSR_MAX_IDX];
logic [31:0] mepc_q, mepc_n;
// CSR update logic
logic [31:0] csr_wdata_int;
@ -147,10 +146,8 @@ module riscv_cs_registers
// mstatus: always M-mode, contains IE bit
12'h300: csr_rdata_int = {29'b0, 2'b11, irq_enable};
// mscratch
12'h340: csr_rdata_int = csr[`CSR_IDX_MSCRATCH];
// mepc: exception program counter
12'h341: csr_rdata_int = csr[`CSR_IDX_MEPC];
12'h341: csr_rdata_int = mepc_q;
// mcause: exception cause
12'h342: csr_rdata_int = {exc_cause[5], 26'b0, exc_cause[4:0]};
@ -175,7 +172,7 @@ module riscv_cs_registers
// write logic
always_comb
begin
csr_n = csr;
mepc_n = mepc_q;
irq_enable_n = irq_enable;
exc_cause_n = exc_cause;
hwlp_we_o = '0;
@ -185,10 +182,8 @@ module riscv_cs_registers
// mstatus: IE bit
12'h300: if (csr_we_int) irq_enable_n = csr_wdata_int[0];
// mscratch
12'h340: if (csr_we_int) csr_n[`CSR_IDX_MSCRATCH] = csr_wdata_int;
// mepc: exception program counter
12'h341: if (csr_we_int) csr_n[`CSR_IDX_MEPC] = csr_wdata_int;
12'h341: if (csr_we_int) mepc_n = csr_wdata_int;
// mcause
12'h342: if (csr_we_int) exc_cause_n = {csr_wdata_int[5], csr_wdata_int[4:0]};
@ -237,7 +232,7 @@ module riscv_cs_registers
// directly output some registers
assign irq_enable_o = irq_enable;
assign epcr_o = csr[`CSR_IDX_MEPC];
assign epcr_o = mepc_q;
// actual registers
@ -245,23 +240,25 @@ module riscv_cs_registers
begin
if (rst_n == 1'b0)
begin
csr <= '{default: 32'b0};
irq_enable <= 1'b0;
exc_cause <= 6'b0;
mepc_q <= '0;
exc_cause <= '0;
end
else
begin
// update CSRs
csr <= csr_n;
irq_enable <= irq_enable_n;
exc_cause <= exc_cause_n;
// exception controller gets priority over other writes
if (save_pc_id_i == 1'b1)
csr[`CSR_IDX_MEPC] <= curr_pc_id_i;
mepc_q <= curr_pc_id_i;
else
mepc_q <= mepc_n;
if (save_exc_cause_i)
exc_cause <= exc_cause_i;
else
exc_cause <= exc_cause_n;
end
end

9
docs/datasheet/content/csr.tex
View file

@ -15,7 +15,6 @@ as possible and avoid any overhead that we do not explicitely need.
\multicolumn{4}{|c|}{\textbf{CSR Address}} & \textbf{Hex} & \textbf{Name} & \textbf{Access} & \textbf{Description} \\ \hline
\textbf{[11:10]} & \textbf{[9:8]} & \textbf{[7:6]} & \textbf{[5:0]} & & & & \\ \toprule
00 & 11 & 00 & 000000 & 0x300 & MSTATUS & R/W & Machine Status Register \\ \hline
00 & 11 & 01 & 000000 & 0x340 & MSCRATCH & R/W & Scratch Register for machine trap handlers \\ \hline
00 & 11 & 01 & 000001 & 0x341 & MEPC & R/W & Machine exception program counter \\ \hline
00 & 11 & 01 & 000010 & 0x342 & MCAUSE & R/W & Machine trap cause \\ \hline
01 & 11 & 00 & 0XXXXX & 0x780 - 0x79F & PCCRs & R/W & Performance Counter Counter Registers \\ \hline
@ -44,14 +43,6 @@ as possible and avoid any overhead that we do not explicitely need.
Note that \signal{PRV[1:0]} is statically \signal{2'b11} and cannot be altered (read-only).
\subsection{MSCRATCH}
\csrDesc{0x340}{0x0000\_0000}{MSRATCH}{
\begin{bytefield}[endianness=big]{32}
\bitheader{31,0} \\
\bitbox{32}{ mscratch }
\end{bytefield}
}
\subsection{MEPC}
\csrDesc{0x341}{0x0000\_0000}{MEPC}{
\begin{bytefield}[endianness=big]{32}

21
ex_stage.sv
View file

@ -86,28 +86,21 @@ module riscv_ex_stage
logic [31:0] alu_result;
logic [31:0] alu_csr_result;
logic [31:0] mult_result;
logic alu_cmp_result;
logic [31:0] mult_result;
// EX stage result mux (ALU, MAC unit, CSR)
assign alu_csr_result = csr_access_i ? csr_rdata_i : alu_result;
assign regfile_alu_wdata_fw_o = mult_en_i ? mult_result : alu_csr_result;
assign regfile_alu_we_fw_o = regfile_alu_we_i;
assign regfile_alu_waddr_fw_o = regfile_alu_waddr_i;
// EX stage result mux (ALU, MAC unit, CSR)
always_comb
begin
regfile_alu_wdata_fw_o = alu_result;
if (mult_en_i == 1'b1)
regfile_alu_wdata_fw_o = mult_result;
if (csr_access_i == 1'b1)
regfile_alu_wdata_fw_o = csr_rdata_i;
end
// branch handling
assign branch_decision_o = alu_cmp_result;
assign jump_target_o = alu_operand_c_i;

6
include/riscv_defines.sv
View file

@ -215,12 +215,6 @@
// |___/ //
/////////////////////////////////////////////////////////
// internal CSR addresses
`define CSR_IDX_MSCRATCH 0
`define CSR_IDX_MEPC 1
`define CSR_MAX_IDX 1
// CSR operations
`define CSR_OP_NONE 2'b00
`define CSR_OP_WRITE 2'b01

5
riscv_core.sv
View file

@ -159,6 +159,7 @@ module riscv_core
logic csr_access;
logic [1:0] csr_op;
logic [11:0] csr_addr;
logic [11:0] csr_addr_int;
logic [31:0] csr_rdata;
logic [31:0] csr_wdata;
@ -648,13 +649,15 @@ module riscv_core
// Mux for CSR access through Debug Unit
assign csr_access = (dbg_sp_mux == 1'b0) ? csr_access_ex : 1'b1;
assign csr_addr = (dbg_sp_mux == 1'b0) ? alu_operand_b_ex[11:0] : dbg_reg_addr;
assign csr_addr = (dbg_sp_mux == 1'b0) ? csr_addr_int : dbg_reg_addr;
assign csr_wdata = (dbg_sp_mux == 1'b0) ? alu_operand_a_ex : dbg_reg_wdata;
assign csr_op = (dbg_sp_mux == 1'b0) ? csr_op_ex
: (dbg_reg_we == 1'b1 ? `CSR_OP_WRITE
: `CSR_OP_NONE );
assign dbg_rdata = (dbg_sp_mux == 1'b0) ? dbg_reg_rdata : csr_rdata;
assign csr_addr_int = csr_access_ex ? alu_operand_b_ex[11:0] : '0;
/////////////////////////////////////////////////////////////
// ____ _____ ____ _ _ ____ _ _ _ _ ___ _____ //