Update opentitan vendor imports to lowRISC/opentitan@249b4c31

This commit was generated by running

    for hj in $(grep -l opentitan vendor/*.vendor.hjson); do
      $opentitan/util/vendor.py -U -c $hj
    done

and then squashing together all the resulting commits. It will be
followed by a patch that combines these vendor.hjson files (using the
vendor tool's new "mapping" functionality), but we need a patch first
to get everything in sync before squashing together.

Individual commit messages below:

*****

Update common_ifs to lowRISC/opentitan@249b4c31

Update code from subdir hw/dv/sv/common_ifs in upstream repository
https://github.com/lowRISC/opentitan to revision
249b4c316cd6626d13e17edd8a52ca60c004af96

* [dv] This fixes a padctrl reset issue in the chip level tb (Michael
  Schaffner)

*****

Update csr_utils to lowRISC/opentitan@249b4c31

Update code from subdir hw/dv/sv/csr_utils in upstream repository
https://github.com/lowRISC/opentitan to revision
249b4c316cd6626d13e17edd8a52ca60c004af96

* [dv] csr_excl_item printed msg cleanup (Srikrishna Iyer)
* [dv] Fix top-level mem test (Weicai Yang)
* [doc] Fix typo in CSR exclusions (Michael Schaffner)
* [dv] Fix failures in test csr_mem_rw_with_rand_reset (Weicai Yang)

*****

Update dv_lib to lowRISC/opentitan@249b4c31

Update code from subdir hw/dv/sv/dv_lib in upstream repository
https://github.com/lowRISC/opentitan to revision
249b4c316cd6626d13e17edd8a52ca60c004af96

* [dv/chip] fix csr_hw_reset X assertion issue (Cindy Chen)
* [dv] Use phase_ready_to_end to handle end of test (Weicai Yang)
* [dv] Fix failures in test csr_mem_rw_with_rand_reset (Weicai Yang)

*****

Update dv_utils to lowRISC/opentitan@249b4c31

Update code from subdir hw/dv/sv/dv_utils in upstream repository
https://github.com/lowRISC/opentitan to revision
249b4c316cd6626d13e17edd8a52ca60c004af96

* [dv] Use uvm_config_db to control tlul_assert (Weicai Yang)
* [dv] Add begin...end around if statement in macro (Weicai Yang)
* [dv] Fix timeout due to too many non-blocking TL accesses (Weicai
  Yang)
* [spi_device/dv] Add interrupt seq (Weicai Yang)

*****

Update dvsim to lowRISC/opentitan@249b4c31

Update code from subdir util/dvsim in upstream repository
https://github.com/lowRISC/opentitan to revision
249b4c316cd6626d13e17edd8a52ca60c004af96

* [dvsim] Enable round-trip of env variables into log (Philipp Wagner)
* [dvsim] Support for running pre-built SW tests (Srikrishna Iyer)
* [dvsim] Print what cmd is executed in the log (Srikrishna Iyer)
* [dvsim] Specify encoding of opened files as UTF-8 (Philipp Wagner)
* [dvsim] Simplify factory methods for FlowCfg (Rupert Swarbrick)
* [dvsim] small fix on css style (Cindy Chen)
* [dvsim] support css format for email (Cindy Chen)
* [doc] Rename Hardware -> Development Stages (Sam Elliott)

*****

Update uvmdvgen to lowRISC/opentitan@249b4c31

Update code from subdir util/uvmdvgen in upstream repository
https://github.com/lowRISC/opentitan to revision
249b4c316cd6626d13e17edd8a52ca60c004af96

* [uvmdvgen] Minor env gen fix (Srikrishna Iyer)
* [doc] Rename Hardware -> Development Stages (Sam Elliott)
* [dv] Use uvm_config_db to control tlul_assert (Weicai Yang)
* [uvmdvgen] Automate checklist gen, fixes (Srikrishna Iyer)
* [doc] Unify dashboard, manual spec table (Srikrishna Iyer)
* [dvsim] Added fusesoc generator for RAL (Srikrishna Iyer)

vendor/lowrisc_common_ifs.lock.hjson

@@ -9,7 +9,7 @@
   upstream:
   {
     url: https://github.com/lowRISC/opentitan
-    rev: 0d7f7ac755d4e00811257027dd814edb2afca050
+    rev: 249b4c316cd6626d13e17edd8a52ca60c004af96
     only_subdir: hw/dv/sv/common_ifs
   }
 }

vendor/lowrisc_csr_utils.lock.hjson

@@ -9,7 +9,7 @@
   upstream:
   {
     url: https://github.com/lowRISC/opentitan
-    rev: 0d7f7ac755d4e00811257027dd814edb2afca050
+    rev: 249b4c316cd6626d13e17edd8a52ca60c004af96
     only_subdir: hw/dv/sv/csr_utils
   }
 }

vendor/lowrisc_dv_lib.lock.hjson

@@ -9,7 +9,7 @@
   upstream:
   {
     url: https://github.com/lowRISC/opentitan
-    rev: 1d17b1225d324c81da522c69317335a83edd5ddb
+    rev: 249b4c316cd6626d13e17edd8a52ca60c004af96
     only_subdir: hw/dv/sv/dv_lib
   }
 }

vendor/lowrisc_dv_utils.lock.hjson

@@ -9,7 +9,7 @@
   upstream:
   {
     url: https://github.com/lowRISC/opentitan
-    rev: 0d7f7ac755d4e00811257027dd814edb2afca050
+    rev: 249b4c316cd6626d13e17edd8a52ca60c004af96
     only_subdir: hw/dv/sv/dv_utils
   }
 }

vendor/lowrisc_dvsim.lock.hjson

@@ -9,7 +9,7 @@
   upstream:
   {
     url: https://github.com/lowRISC/opentitan
-    rev: 1d17b1225d324c81da522c69317335a83edd5ddb
+    rev: 249b4c316cd6626d13e17edd8a52ca60c004af96
     only_subdir: util/dvsim
   }
 }

vendor/lowrisc_ip/common_ifs/clk_rst_if.sv

@@ -159,6 +159,11 @@ interface clk_rst_if #(
     end
   endfunction
 
+  // can be used to override clk/rst pins, e.g. at the beginning of the simulation
+  task automatic drive_rst_pin(logic val = 1'b0);
+    o_rst_n = val;
+  endtask
+
   // apply reset with specified scheme
   // TODO make this enum?
   // rst_n_scheme

vendor/lowrisc_ip/csr_utils/README.md

@@ -140,7 +140,7 @@ Examples of useful functions in this class are:
       CsrExclWriteCheck = 3'b010, // exclude csr from write-read check
       CsrExclCheck      = 3'b011, // exclude csr from init or write-read check
       CsrExclWrite      = 3'b100, // exclude csr from write
-      CsrExclAll        = 3'b111  // exclude csr from init or write or writ-read check
+      CsrExclAll        = 3'b111  // exclude csr from init or write or write-read check
     } csr_excl_type_e;
     ```
 

vendor/lowrisc_ip/csr_utils/csr_excl_item.sv

@@ -97,12 +97,12 @@ class csr_excl_item extends uvm_object;
   // print all exclusions for ease of debug (call this ideally after adding all exclusions)
   virtual function void print_exclusions(uvm_verbosity verbosity = UVM_HIGH);
     string test_names;
-    for (int i = 0; i < NUM_CSR_TESTS; i++) begin
+    for (int i = NUM_CSR_TESTS - 1; i >= 0; i--) begin
       csr_test_type_e csr_test = csr_test_type_e'(1 << i);
-      test_names = {test_names, csr_test.name(), " "};
+      test_names = {test_names, csr_test.name(),  (i > 0) ? " " : ""};
     end
     foreach (exclusions[item]) begin
-      `uvm_info(`gfn, $sformatf("CSR/field [%0s] excluded with %0s in csr_tests: {%s}={%0b}",
+      `uvm_info(`gfn, $sformatf("CSR/field [%0s] excluded with %0s in csr_tests: {%s} = {%0b}",
                                 item, exclusions[item].csr_excl_type.name(), test_names,
                                 exclusions[item].csr_test_type), verbosity)
     end

vendor/lowrisc_ip/csr_utils/csr_seq_lib.sv

@@ -259,6 +259,7 @@ class csr_rw_seq extends csr_base_seq;
                        .compare_vs_ral(1'b1));
         end
       end
+      wait_if_max_outstanding_accesses_reached();
     end
   endtask
 

vendor/lowrisc_ip/csr_utils/csr_utils_pkg.sv

@@ -18,6 +18,7 @@ package csr_utils_pkg;
   string     msg_id                      = "csr_utils";
   bit        default_csr_blocking        = 1;
   bit        under_reset                 = 0;
+  int        max_outstanding_accesses    = 100;
 
   // global paramters for number of csr tests (including memory test)
   parameter uint NUM_CSR_TESTS = 4;
@@ -50,7 +51,7 @@ package csr_utils_pkg;
     CsrExclWriteCheck = 3'b010, // exclude csr from write-read check
     CsrExclCheck      = 3'b011, // exclude csr from init or write-read check
     CsrExclWrite      = 3'b100, // exclude csr from write
-    CsrExclAll        = 3'b111  // exclude csr from init or write or writ-read check
+    CsrExclAll        = 3'b111  // exclude csr from init or write or write-read check
   } csr_excl_type_e;
 
   function automatic void increment_outstanding_access();
@@ -69,6 +70,12 @@ package csr_utils_pkg;
     outstanding_accesses = 0;
   endfunction
 
+  // timeout may happen if we issue too many non-blocking accesses at once
+  // limit the nonblocking items to be up to max outstanding
+  task automatic wait_if_max_outstanding_accesses_reached(int max = max_outstanding_accesses);
+    wait(outstanding_accesses <= max);
+  endtask
+
   function automatic void reset_asserted();
     under_reset = 1;
   endfunction
@@ -91,7 +98,6 @@ package csr_utils_pkg;
   function automatic void get_mem_addr_ranges(uvm_reg_block ral, ref addr_range_t mem_ranges[$]);
     uvm_mem mems[$];
     ral.get_memories(mems);
-    mems.delete();
     foreach (mems[i]) begin
       addr_range_t mem_range;
       mem_range.start_addr = mems[i].get_address();
@@ -101,6 +107,21 @@ package csr_utils_pkg;
     end
   endfunction
 
+  // get mem object from address
+  function automatic uvm_mem get_mem_by_addr(uvm_reg_block ral, uvm_reg_addr_t addr);
+    uvm_mem mem;
+    addr[1:0] = 0;
+    mem = ral.default_map.get_mem_by_offset(addr);
+    `DV_CHECK_NE_FATAL(mem, null, $sformatf("Can't find any mem with addr 0x%0h", addr), msg_id)
+    return mem;
+  endfunction
+
+  // get mem access like RW, RO
+  function automatic string get_mem_access_by_addr(uvm_reg_block ral, uvm_reg_addr_t addr);
+    uvm_mem mem = get_mem_by_addr(ral, addr);
+    return mem.get_access();
+  endfunction
+
   // This fucntion return mirrored value of reg/field of given RAL
   function automatic uvm_reg_data_t get_reg_fld_mirror_value(uvm_reg_block ral,
                                                              string        reg_name,

vendor/lowrisc_ip/dv_lib/dv_base_agent_cfg.sv

@@ -9,6 +9,9 @@ class dv_base_agent_cfg extends uvm_object;
   bit         en_cov    = 1'b1;   // enable coverage
   if_mode_e   if_mode;            // interface mode - Host or Device
 
+  // use for phase_ready_to_end to add additional delay after ok_to_end is set
+  int ok_to_end_delay_ns = 1000;
+
   `uvm_object_utils_begin(dv_base_agent_cfg)
     `uvm_field_int (is_active,          UVM_DEFAULT)
     `uvm_field_int (en_cov,             UVM_DEFAULT)

vendor/lowrisc_ip/dv_lib/dv_base_env_cfg.sv

@@ -17,9 +17,6 @@ class dv_base_env_cfg #(type RAL_T = dv_base_reg_block) extends uvm_object;
   RAL_T                 ral;
   bit [TL_AW-1:0]       csr_addrs[$];
   addr_range_t          mem_ranges[$];
-  // mem access support, if not enabled, will trigger error
-  bit                   en_mem_byte_write = 0;
-  bit                   en_mem_read       = 1;
 
   // ral base address and size
   bit [TL_AW-1:0]       csr_base_addr;     // base address where csr map begins

vendor/lowrisc_ip/dv_lib/dv_base_mem.sv

@@ -8,6 +8,9 @@ class dv_base_mem extends uvm_mem;
   // uvm_mem::m_access is local variable. Create it again in order to use "access" in current class
   local string m_access;
 
+  // if mem doesn't support partial write, doing that will result d_error = 1
+  local bit mem_partial_write_support;
+
   function new(string           name,
                longint unsigned size,
                int unsigned     n_bits,
@@ -17,6 +20,14 @@ class dv_base_mem extends uvm_mem;
     m_access = access;
   endfunction : new
 
+  function void set_mem_partial_write_support(bit enable);
+    mem_partial_write_support = enable;
+  endfunction : set_mem_partial_write_support
+
+  function bit get_mem_partial_write_support();
+    return mem_partial_write_support;
+  endfunction : get_mem_partial_write_support
+
   // rewrite this function to support "WO" access type for mem
   function void configure(uvm_reg_block  parent,
                           string         hdl_path="");

vendor/lowrisc_ip/dv_lib/dv_base_monitor.sv

@@ -10,6 +10,13 @@ class dv_base_monitor #(type ITEM_T = uvm_sequence_item,
   CFG_T cfg;
   COV_T cov;
 
+  // extended monitor needs to drive ok_to_end = 0 when bus is busy, set to 1 when it's not busy
+  protected bit ok_to_end = 1;
+
+  // make sure at least we add ok_to_end_delay_ns once and invoke monitor_ready_to_end once
+  // after enter phase_ready_to_end
+  protected bit watchdog_done;
+
   // Analysis port for the collected transfer.
   uvm_analysis_port #(ITEM_T) analysis_port;
 
@@ -31,5 +38,64 @@ class dv_base_monitor #(type ITEM_T = uvm_sequence_item,
     `uvm_fatal(`gfn, "this method is not supposed to be called directly!")
   endtask
 
+  virtual function void phase_ready_to_end(uvm_phase phase);
+    if (phase.is(uvm_run_phase::get())) begin
+      if (watchdog_done) fork
+          monitor_ready_to_end();
+      join_none
+      if (!ok_to_end || !watchdog_done) begin
+        phase.raise_objection(this, $sformatf("%s objection raised", `gfn));
+        `uvm_info(`gfn, $sformatf("Raised objection, because ok_to_end: %0b, watchdog_done: %0b",
+                                  ok_to_end, watchdog_done), UVM_MEDIUM)
+
+        fork
+          begin
+            // wait until ok_to_end is set plus the delay of ok_to_end_delay_ns
+            watchdog_ok_to_end();
+            phase.drop_objection(this, $sformatf("%s objection dropped", `gfn));
+            `uvm_info(`gfn, $sformatf("Dropped objection"), UVM_MEDIUM)
+          end
+        join_none;
+      end
+    end
+  endfunction
+
+  // This watchdog will wait for ok_to_end_delay_ns while checking for any
+  // traffic on the bus during this period.
+  // If traffic is seen before ok_to_end_delay_ns, the watchdog will keep
+  // repeating this process until the traffic has stopped.
+  virtual task watchdog_ok_to_end();
+    fork
+      begin : isolation_fork
+        bit watchdog_reset;
+
+        fork
+          forever begin
+            // check the bus interface for any traffic. If any, extend timer for one more
+            // ok_to_end_delay_ns
+            @(ok_to_end or watchdog_reset);
+            if (!ok_to_end && !watchdog_reset) watchdog_reset = 1;
+          end
+          forever begin
+            #(cfg.ok_to_end_delay_ns * 1ns);
+            if (!watchdog_reset) begin
+              break;
+            end else begin
+              `uvm_info(`gfn, "Resetting phase watchdog timer", UVM_HIGH)
+              watchdog_reset = 0;
+            end
+          end
+        join_any;
+        disable fork;
+
+        watchdog_done = 1;
+      end : isolation_fork
+    join
+  endtask
+
+  // this task will be invoked as non-blocking thread when phase first enters phase_ready_to_end
+  // extended class can override this task to update ok_to_end
+  virtual task monitor_ready_to_end();
+  endtask
 endclass
 

vendor/lowrisc_ip/dv_lib/dv_base_test.sv

@@ -65,7 +65,6 @@ class dv_base_test #(type CFG_T = dv_base_env_cfg,
     phase.raise_objection(this, $sformatf("%s objection raised", `gn));
     test_seq.start(env.virtual_sequencer);
     phase.drop_objection(this, $sformatf("%s objection dropped", `gn));
-    phase.phase_done.display_objections();
     `uvm_info(`gfn, {"Finished test sequence ", test_seq_s}, UVM_MEDIUM)
   endtask
 

vendor/lowrisc_ip/dv_lib/dv_base_vseq.sv

@@ -30,6 +30,11 @@ class dv_base_vseq #(type RAL_T               = dv_base_reg_block,
   // knobs to enable post_start routines
   bit do_dut_shutdown   = 1'b1;
 
+  // various knobs to enable certain routines
+  // this knob allows user to disable assertions in csr_hw_reset before random write sequence,
+  // the assertions will turn back on after the hw reset deasserted
+  bit enable_asserts_in_hw_reset_rand_wr  = 1'b1;
+
   `uvm_object_new
 
   task pre_start();
@@ -165,14 +170,15 @@ class dv_base_vseq #(type RAL_T               = dv_base_reg_block,
       m_csr_write_seq.models.push_back(ral);
       m_csr_write_seq.set_csr_excl_item(csr_excl);
       m_csr_write_seq.external_checker = cfg.en_scb;
+      if (!enable_asserts_in_hw_reset_rand_wr) $assertoff;
       m_csr_write_seq.start(null);
 
       // run dut_shutdown before asserting reset
       dut_shutdown();
-
       // issue reset
       void'($value$plusargs("do_reset=%0s", reset_type));
       dut_init(reset_type);
+      if (!enable_asserts_in_hw_reset_rand_wr) $asserton;
     end
 
     // create base csr seq and pass our ral

vendor/lowrisc_ip/dv_utils/dv_macros.svh

@@ -23,10 +23,12 @@
 // throw error if cast fails
 `ifndef downcast
   `define downcast(EXT_, BASE_, MSG_="", SEV_=fatal, ID_=`gfn) \
+    begin \
       if (!$cast(EXT_, BASE_)) begin \
         `uvm_``SEV_(ID_, $sformatf({"Cast failed: base class variable %0s ", \
                                     "does not hold extended class %0s handle %s"}, \
                                     `"BASE_`", `"EXT_`", MSG_)) \
+      end \
     end
 `endif
 
@@ -59,72 +61,90 @@
 // Note: Should not be called by user code
 `ifndef DV_CHECK
   `define DV_CHECK(T_, MSG_="", SEV_=error, ID_=`gfn) \
+    begin \
       if (!(T_)) begin \
         `uvm_``SEV_(ID_, $sformatf("Check failed (%s) %s ", `"T_`", MSG_)) \
+      end \
     end
 `endif
 
 `ifndef DV_CHECK_EQ
   `define DV_CHECK_EQ(ACT_, EXP_, MSG_="", SEV_=error, ID_=`gfn) \
+    begin \
       if (!(ACT_ == EXP_)) begin \
         `uvm_``SEV_(ID_, $sformatf("Check failed %s == %s (%0d [0x%0h] vs %0d [0x%0h]) %s", \
                                     `"ACT_`", `"EXP_`", ACT_, ACT_, EXP_, EXP_, MSG_)) \
+      end \
     end
 `endif
 
 `ifndef DV_CHECK_NE
   `define DV_CHECK_NE(ACT_, EXP_, MSG_="", SEV_=error, ID_=`gfn) \
+    begin \
       if (!(ACT_ != EXP_)) begin \
         `uvm_``SEV_(ID_, $sformatf("Check failed %s != %s (%0d [0x%0h] vs %0d [0x%0h]) %s", \
                                     `"ACT_`", `"EXP_`", ACT_, ACT_, EXP_, EXP_, MSG_)) \
+      end \
     end
 `endif
 
 `ifndef DV_CHECK_CASE_EQ
   `define DV_CHECK_CASE_EQ(ACT_, EXP_, MSG_="", SEV_=error, ID_=`gfn) \
+    begin \
       if (!(ACT_ === EXP_)) begin \
         `uvm_``SEV_(ID_, $sformatf("Check failed %s === %s (0x%0h [%0b] vs 0x%0h [%0b]) %s", \
                                     `"ACT_`", `"EXP_`", ACT_, ACT_, EXP_, EXP_, MSG_)) \
+      end \
     end
 `endif
 
 `ifndef DV_CHECK_CASE_NE
   `define DV_CHECK_CASE_NE(ACT_, EXP_, MSG_="", SEV_=error, ID_=`gfn) \
+    begin \
       if (!(ACT_ !== EXP_)) begin \
         `uvm_``SEV_(ID_, $sformatf("Check failed %s !== %s (%0d [0x%0h] vs %0d [0x%0h]) %s", \
                                     `"ACT_`", `"EXP_`", ACT_, ACT_, EXP_, EXP_, MSG_)) \
+      end \
     end
 `endif
 
 `ifndef DV_CHECK_LT
   `define DV_CHECK_LT(ACT_, EXP_, MSG_="", SEV_=error, ID_=`gfn) \
+    begin \
       if (!(ACT_ < EXP_)) begin \
         `uvm_``SEV_(ID_, $sformatf("Check failed %s < %s (%0d [0x%0h] vs %0d [0x%0h]) %s", \
                                     `"ACT_`", `"EXP_`", ACT_, ACT_, EXP_, EXP_, MSG_)) \
+      end \
     end
 `endif
 
 `ifndef DV_CHECK_GT
   `define DV_CHECK_GT(ACT_, EXP_, MSG_="", SEV_=error, ID_=`gfn) \
+    begin \
       if (!(ACT_ > EXP_)) begin \
         `uvm_``SEV_(ID_, $sformatf("Check failed %s > %s (%0d [0x%0h] vs %0d [0x%0h]) %s", \
                                     `"ACT_`", `"EXP_`", ACT_, ACT_, EXP_, EXP_, MSG_)) \
+      end \
     end
 `endif
 
 `ifndef DV_CHECK_LE
   `define DV_CHECK_LE(ACT_, EXP_, MSG_="", SEV_=error, ID_=`gfn) \
+    begin \
       if (!(ACT_ <= EXP_)) begin \
         `uvm_``SEV_(ID_, $sformatf("Check failed %s <= %s (%0d [0x%0h] vs %0d [0x%0h]) %s", \
                                     `"ACT_`", `"EXP_`", ACT_, ACT_, EXP_, EXP_, MSG_)) \
+      end \
     end
 `endif
 
 `ifndef DV_CHECK_GE
   `define DV_CHECK_GE(ACT_, EXP_, MSG_="", SEV_=error, ID_=`gfn) \
+    begin \
       if (!(ACT_ >= EXP_)) begin \
         `uvm_``SEV_(ID_, $sformatf("Check failed %s >= %s (%0d [0x%0h] vs %0d [0x%0h]) %s", \
                                     `"ACT_`", `"EXP_`", ACT_, ACT_, EXP_, EXP_, MSG_)) \
+      end \
     end
 `endif
 
@@ -203,60 +223,72 @@
 // print static/dynamic 1d array or queue
 `ifndef DV_PRINT_ARR_CONTENTS
 `define DV_PRINT_ARR_CONTENTS(ARR_, V_=UVM_MEDIUM, ID_=`gfn) \
+  begin \
     foreach (ARR_[i]) begin \
       `uvm_info(ID_, $sformatf("%s[%0d] = 0x%0d[0x%0h]", `"ARR_`", i, ARR_[i], ARR_[i]), V_) \
+    end \
   end
 `endif
 
 // print non-empty tlm fifos that were uncompared at end of test
 `ifndef DV_EOT_PRINT_TLM_FIFO_CONTENTS
 `define DV_EOT_PRINT_TLM_FIFO_CONTENTS(TYP_, FIFO_, SEV_=error, ID_=`gfn) \
+  begin \
     while (!FIFO_.is_empty()) begin \
       TYP_ item; \
       void'(FIFO_.try_get(item)); \
       `uvm_``SEV_(ID_, $sformatf("%s item uncompared:\n%s", `"FIFO_`", item.sprint())) \
+    end \
   end
 `endif
 
 // print non-empty tlm fifos that were uncompared at end of test
 `ifndef DV_EOT_PRINT_TLM_FIFO_ARR_CONTENTS
 `define DV_EOT_PRINT_TLM_FIFO_ARR_CONTENTS(TYP_, FIFO_, SEV_=error, ID_=`gfn) \
+  begin \
     foreach (FIFO_[i]) begin \
       while (!FIFO_[i].is_empty()) begin \
         TYP_ item; \
         void'(FIFO_[i].try_get(item)); \
         `uvm_``SEV_(ID_, $sformatf("%s[%0d] item uncompared:\n%s", `"FIFO_`", i, item.sprint())) \
       end \
+    end \
   end
 `endif
 
 // print non-empty tlm fifos that were uncompared at end of test
 `ifndef DV_EOT_PRINT_Q_CONTENTS
 `define DV_EOT_PRINT_Q_CONTENTS(TYP_, Q_, SEV_=error, ID_=`gfn) \
+  begin \
     while (Q_.size() != 0) begin \
       TYP_ item = Q_.pop_front(); \
       `uvm_``SEV_(ID_, $sformatf("%s item uncompared:\n%s", `"Q_`", item.sprint())) \
+    end \
   end
 `endif
 
 // print non-empty tlm fifos that were uncompared at end of test
 `ifndef DV_EOT_PRINT_Q_ARR_CONTENTS
 `define DV_EOT_PRINT_Q_ARR_CONTENTS(TYP_, Q_, SEV_=error, ID_=`gfn) \
+  begin \
     foreach (Q_[i]) begin \
       while (Q_[i].size() != 0) begin \
         TYP_ item = Q_[i].pop_front(); \
         `uvm_``SEV_(ID_, $sformatf("%s[%0d] item uncompared:\n%s", `"Q_`", i, item.sprint())) \
       end \
+    end \
   end
 `endif
 
 // check for non-empty mailbox and print items that were uncompared at end of test
 `ifndef DV_EOT_PRINT_MAILBOX_CONTENTS
 `define DV_EOT_PRINT_MAILBOX_CONTENTS(TYP_, MAILBOX_, SEV_=error, ID_=`gfn) \
+  begin \
     while (MAILBOX_.num() != 0) begin \
       TYP_ item; \
       void'(MAILBOX_.try_get(item)); \
       `uvm_``SEV_(ID_, $sformatf("%s item uncompared:\n%s", `"MAILBOX_`", item.sprint())) \
+    end \
   end
 `endif
 
@@ -273,7 +305,8 @@
 //                ...
 //              end)
 `ifndef DV_SPINWAIT
-`define DV_SPINWAIT(WAIT_, MSG_ = "", TIMEOUT_NS_ = default_timeout_ns, ID_ =`gfn) \
+`define DV_SPINWAIT(WAIT_, MSG_ = "", TIMEOUT_NS_ = default_spinwait_timeout_ns, ID_ =`gfn) \
+  begin \
     fork begin \
       fork \
         begin \
@@ -284,5 +317,6 @@
         end \
       join_any \
       disable fork; \
-  end join
+    end join \
+  end
 `endif

vendor/lowrisc_ip/dv_utils/dv_utils_pkg.sv

@@ -25,7 +25,6 @@ package dv_utils_pkg;
   // typedef parameterized pins_if for ease of implementation for interrupts and alerts
   typedef virtual pins_if #(NUM_MAX_INTERRUPTS) intr_vif;
   typedef virtual pins_if #(1)                  devmode_vif;
-  typedef virtual pins_if #(1)                  tlul_assert_ctrl_vif;
 
   // interface direction / mode - Host or Device
   typedef enum bit {
@@ -76,6 +75,16 @@ package dv_utils_pkg;
 
   string msg_id = "dv_utils_pkg";
 
+  // return the smaller value of 2 inputs
+  function automatic int min2(int a, int b);
+      return (a < b) ? a : b;
+  endfunction
+
+  // return the bigger value of 2 inputs
+  function automatic int max2(int a, int b);
+    return (a > b) ? a : b;
+  endfunction
+
   // Simple function to set max errors before quitting sim
   function automatic void set_max_quit_count(int n);
     uvm_report_server report_server = uvm_report_server::get_server();

vendor/lowrisc_ip/dvsim/Deploy.py

@@ -174,13 +174,18 @@ class Deploy():
                 self.odir_limiter(odir=self.odir)
             os.system("mkdir -p " + self.odir)
             # Dump all env variables for ease of debug.
-            with open(self.odir + "/env_vars", "w") as f:
+            with open(self.odir + "/env_vars",
+                      "w",
+                      encoding="UTF-8",
+                      errors="surrogateescape") as f:
                 for var in sorted(self.exports.keys()):
                     f.write("{}={}\n".format(var, self.exports[var]))
                 f.close()
             os.system("ln -s " + self.odir + " " + self.sim_cfg.links['D'] +
                       '/' + self.odir_ln)
-            f = open(self.log, "w")
+            f = open(self.log, "w", encoding="UTF-8", errors="surrogateescape")
+            f.write("[Executing]:\n{}\n\n".format(self.cmd))
+            f.flush()
             self.process = subprocess.Popen(args,
                                             bufsize=4096,
                                             universal_newlines=True,
@@ -657,8 +662,8 @@ class RunTest(Deploy):
             "uvm_test": False,
             "uvm_test_seq": False,
             "run_opts": False,
-            "sw_dir": False,
+            "sw_test": False,
-            "sw_name": False,
+            "sw_test_is_prebuilt": False,
             "sw_build_device": False,
             "sw_build_dir": False,
             "run_dir": False,

vendor/lowrisc_ip/dvsim/FlowCfg.py

@@ -79,7 +79,7 @@ class FlowCfg():
         self.results_server_prefix = ""
         self.results_server_url_prefix = ""
         self.results_server_cmd = ""
-        self.results_server_css_path = ""
+        self.css_file = os.path.join(os.path.dirname(os.path.realpath(__file__)), "style.css")
         self.results_server_path = ""
         self.results_server_dir = ""
         self.results_server_html = ""
@@ -99,11 +99,11 @@ class FlowCfg():
                 log.error("Parse error!\n%s", self.cfgs)
                 sys.exit(1)
 
-    @staticmethod
+    def create_instance(self, flow_cfg_file):
-    def create_instance(flow_cfg_file, proj_root, args):
+        '''Create a new instance of this class for the given config file.
-        '''Create a new instance of this class as with given parameters.
+
         '''
-        return FlowCfg(flow_cfg_file, proj_root, args)
+        return type(self)(flow_cfg_file, self.proj_root, self.args)
 
     def kill(self):
         '''kill running processes and jobs gracefully
@@ -254,18 +254,14 @@ class FlowCfg():
                     cfg_file = subst_wildcards(entry,
                                                self.__dict__,
                                                ignore_error=True)
-                    self.cfgs.append(
+                    self.cfgs.append(self.create_instance(cfg_file))
-                        self.create_instance(cfg_file, self.proj_root,
-                                             self.args))
 
                 elif type(entry) is dict:
                     # Treat this as a cfg expanded in-line
                     temp_cfg_file = self._conv_inline_cfg_to_hjson(entry)
                     if not temp_cfg_file:
                         continue
-                    self.cfgs.append(
+                    self.cfgs.append(self.create_instance(temp_cfg_file))
-                        self.create_instance(temp_cfg_file, self.proj_root,
-                                             self.args))
 
                     # Delete the temp_cfg_file once the instance is created
                     try:
@@ -482,8 +478,7 @@ class FlowCfg():
             gen_results = self.results_summary_md
         else:
             gen_results = self.results_md
-        results_html = md_results_to_html(self.results_title, self.results_server_css_path,
+        results_html = md_results_to_html(self.results_title, self.css_file, gen_results)
-                                          gen_results)
         results_html_file = self.scratch_root + "/email.html"
         f = open(results_html_file, 'w')
         f.write(results_html)
@@ -612,8 +607,7 @@ class FlowCfg():
         results_html_file = self.scratch_path + "/results_" + self.timestamp + ".html"
         f = open(results_html_file, 'w')
         f.write(
-            md_results_to_html(self.results_title,
+            md_results_to_html(self.results_title, self.css_file, results_md))
-                               self.results_server_css_path, results_md))
         f.close()
         rm_cmd += "/bin/rm -rf " + results_html_file + "; "
 
@@ -650,9 +644,7 @@ class FlowCfg():
         # First, write the results html file temporarily to the scratch area.
         f = open(results_html_file, 'w')
         f.write(
-            md_results_to_html(self.results_title,
+            md_results_to_html(self.results_title, self.css_file, self.results_summary_md))
-                               self.results_server_css_path,
-                               self.results_summary_md))
         f.close()
         rm_cmd = "/bin/rm -rf " + results_html_file + "; "
 

vendor/lowrisc_ip/dvsim/LintCfg.py

@@ -50,12 +50,6 @@ class LintCfg(OneShotCfg):
         else:
             self.results_title = self.name.upper() + " Lint Results"
 
-    @staticmethod
-    def create_instance(flow_cfg_file, proj_root, args):
-        '''Create a new instance of this class as with given parameters.
-        '''
-        return LintCfg(flow_cfg_file, proj_root, args)
-
     def gen_results_summary(self):
         '''
         Gathers the aggregated results from all sub configs

vendor/lowrisc_ip/dvsim/Modes.py

@@ -271,8 +271,8 @@ class RunModes(Modes):
         self.uvm_test_seq = ""
         self.build_mode = ""
         self.en_run_modes = []
-        self.sw_dir = ""
+        self.sw_test = ""
-        self.sw_name = ""
+        self.sw_test_is_prebuilt = ""
         self.sw_build_device = ""
 
         super().__init__(rdict)
@@ -298,8 +298,8 @@ class Tests(RunModes):
         "uvm_test": "",
         "uvm_test_seq": "",
         "build_mode": "",
-        "sw_dir": "",
+        "sw_test": "",
-        "sw_name": "",
+        "sw_test_is_prebuilt": "",
         "sw_build_device": "",
     }
 

vendor/lowrisc_ip/dvsim/OneShotCfg.py

@@ -120,12 +120,6 @@ class OneShotCfg(FlowCfg):
         # Run some post init checks
         super().__post_init__()
 
-    @staticmethod
-    def create_instance(flow_cfg_file, proj_root, args):
-        '''Create a new instance of this class as with given parameters.
-        '''
-        return OneShotCfg(flow_cfg_file, proj_root, args)
-
     # Purge the output directories. This operates on self.
     def _purge(self):
         if self.scratch_path:

vendor/lowrisc_ip/dvsim/SimCfg.py

@@ -124,7 +124,7 @@ class SimCfg(FlowCfg):
         # TODO: Find a way to set these in sim cfg instead
         ignored_wildcards = [
             "build_mode", "index", "test", "seed", "uvm_test", "uvm_test_seq",
-            "cov_db_dirs", "sw_dir", "sw_name", "sw_build_device"
+            "cov_db_dirs", "sw_test", "sw_test_is_prebuilt", "sw_build_device"
         ]
         self.__dict__ = find_and_substitute_wildcards(self.__dict__,
                                                       self.__dict__,
@@ -167,12 +167,6 @@ class SimCfg(FlowCfg):
         # Run some post init checks
         super().__post_init__()
 
-    @staticmethod
-    def create_instance(flow_cfg_file, proj_root, args):
-        '''Create a new instance of this class as with given parameters.
-        '''
-        return SimCfg(flow_cfg_file, proj_root, args)
-
     def kill(self):
         '''kill running processes and jobs gracefully
         '''

vendor/lowrisc_ip/dvsim/SynCfg.py

@@ -26,12 +26,6 @@ class SynCfg(OneShotCfg):
         # Set the title for synthesis results.
         self.results_title = self.name.upper() + " Synthesis Results"
 
-    @staticmethod
-    def create_instance(flow_cfg_file, proj_root, args):
-        '''Create a new instance of this class as with given parameters.
-        '''
-        return SynCfg(flow_cfg_file, proj_root, args)
-
     def gen_results_summary(self):
         '''
         Gathers the aggregated results from all sub configs

vendor/lowrisc_ip/dvsim/style.css

@@ -4,11 +4,7 @@
  */
 
 /* CSS for reports.opentitan.org.
- * This is currently uploaded to reports.opentitan.org/css/style,css. It is
+ * This is referenced by all results published to the reports server for some basic styling.
- * referenced by all results published to the reports server for some basic
- * styling. After making any change to this file, it needs to be manually
- * copied over so that the new changes are reflected in the results pages.
- * gsutil cp <this-file> gs://reports.opentitan.org/css/style.css
  */
 
 .results {
@@ -18,10 +14,8 @@
   padding-right: 40px;
   margin: 0 auto;
   position: relative;
-  display: flex;
-  flex-direction: column;
-  min-height: 100vh;
   font-family: "Trebuchet MS", Arial, Helvetica, sans-serif;
+  padding-top: 15px;
 }
 
 .results p {
@@ -31,13 +25,11 @@
 .results pre {
    overflow-x: auto;
    white-space: pre-wrap;
-   white-space: -moz-pre-wrap;
-   white-space: -pre-wrap;
-   white-space: -o-pre-wrap;
 }
 
 .results h1, .results h2, .results h3 {
   text-align: center;
+  padding-bottom: 15px;
 }
 
 .results table {
@@ -48,7 +40,7 @@
   text-align: center;
   vertical-align: middle;
   display: table;
-  table-layout: auto
+  table-layout: auto;
 }
 
 .results th {
@@ -74,7 +66,7 @@
 
 /* Color encoding for percentages. */
 .cna  {
-  color: 000000;
+  color: #000000;
   background-color: #f8f8f8;
 }
 

vendor/lowrisc_ip/dvsim/testplanner/README.md

@@ -43,7 +43,7 @@ intent of a planned test:
 * **tests: list of actual written tests that maps to this planned test**
 
     Testplan is written in the initial work stage of the verification
-    [life-cycle]({{< relref "doc/project/hw_stages#hardware-verification-stages" >}}).
+    [life-cycle]({{< relref "doc/project/development_stages#hardware-verification-stages" >}}).
     When the DV engineer gets to actually developing the test, it may not map 1:1 to
     the planned test - it may be possible that an already written test that mapped
     to another planned test also satisfies the current one; OR it may also be

vendor/lowrisc_ip/dvsim/utils.py

@@ -16,6 +16,7 @@ from collections import OrderedDict
 
 import hjson
 import mistletoe
+from premailer import transform
 
 # For verbose logging
 VERBOSE = 15
@@ -186,7 +187,7 @@ def find_and_substitute_wildcards(sub_dict,
     return sub_dict
 
 
-def md_results_to_html(title, css_path, md_text):
+def md_results_to_html(title, css_file, md_text):
     '''Convert results in md format to html. Add a little bit of styling.
     '''
     html_text = "<!DOCTYPE html>\n"
@@ -194,9 +195,6 @@ def md_results_to_html(title, css_path, md_text):
     html_text += "<head>\n"
     if title != "":
         html_text += "  <title>{}</title>\n".format(title)
-    if css_path != "":
-        html_text += "  <link rel=\"stylesheet\" type=\"text/css\""
-        html_text += " href=\"{}\"/>\n".format(css_path)
     html_text += "</head>\n"
     html_text += "<body>\n"
     html_text += "<div class=\"results\">\n"
@@ -205,6 +203,10 @@ def md_results_to_html(title, css_path, md_text):
     html_text += "</body>\n"
     html_text += "</html>\n"
     html_text = htmc_color_pc_cells(html_text)
+    # this function converts css style to inline html style
+    html_text = transform(html_text,
+                          external_styles=css_file,
+                          cssutils_logging_level=log.ERROR)
     return html_text
 
 

vendor/lowrisc_ip/uvmdvgen/checklist.md.tpl

@@ -0,0 +1,234 @@
+---
+title: "${name.upper()} Checklist"
+---
+
+<!--
+NOTE: This is a template checklist document that is required to be copied over to the 'doc'
+directory for a new design that transitions from L0 (Specification) to L1 (Development)
+stage, and updated as needed. Once done, please remove this comment before checking it in.
+-->
+This checklist is for [Hardware Stage]({{< relref "/doc/project/development_stages.md" >}}) transitions for the [${name.upper()} peripheral.]({{< relref "hw/ip/${name}/doc" >}})
+All checklist items refer to the content in the [Checklist.]({{< relref "/doc/project/checklist.md" >}})
+
+## Design Checklist
+
+### D1
+
+Type          | Item                  | Resolution  | Note/Collaterals
+--------------|-----------------------|-------------|------------------
+Documentation | [SPEC_COMPLETE][]     | Not Started | [${name.upper()} Design Spec]({{<relref "hw/ip/${name}/doc" >}})
+Documentation | [CSR_DEFINED][]       | Not Started |
+RTL           | [CLKRST_CONNECTED][]  | Not Started |
+RTL           | [IP_TOP][]            | Not Started |
+RTL           | [IP_INSTANTIABLE][]   | Not Started |
+RTL           | [MEM_INSTANCED_80][]  | Not Started |
+RTL           | [FUNC_IMPLEMENTED][]  | Not Started |
+RTL           | [ASSERT_KNOWN_ADDED][]| Not Started |
+Code Quality  | [LINT_SETUP][]        | Not Started |
+Review        | Reviewer(s)           | Not Started |
+Review        | Signoff date          | Not Started |
+
+[SPEC_COMPLETE]:      {{<relref "/doc/project/checklist.md#spec-complete" >}}
+[CSR_DEFINED]:        {{<relref "/doc/project/checklist.md#csr-defined" >}}
+[CLKRST_CONNECTED]:   {{<relref "/doc/project/checklist.md#clkrst-connected" >}}
+[IP_TOP]:             {{<relref "/doc/project/checklist.md#ip-top" >}}
+[IP_INSTANTIABLE]:    {{<relref "/doc/project/checklist.md#ip-instantiable" >}}
+[MEM_INSTANCED_80]:   {{<relref "/doc/project/checklist.md#mem-instanced-80" >}}
+[FUNC_IMPLEMENTED]:   {{<relref "/doc/project/checklist.md#func-implemented" >}}
+[ASSERT_KNOWN_ADDED]: {{<relref "/doc/project/checklist.md#assert-known-added" >}}
+[LINT_SETUP]:         {{<relref "/doc/project/checklist.md#lint-setup" >}}
+
+### D2
+
+Type          | Item                    | Resolution  | Note/Collaterals
+--------------|-------------------------|-------------|------------------
+Documentation | [NEW_FEATURES][]        | Not Started |
+Documentation | [BLOCK_DIAGRAM][]       | Not Started |
+Documentation | [DOC_INTERFACE][]       | Not Started |
+Documentation | [MISSING_FUNC][]        | Not Started |
+Documentation | [FEATURE_FROZEN][]      | Not Started |
+RTL           | [FEATURE_COMPLETE][]    | Not Started |
+RTL           | [AREA_SANITY_CHECK][]   | Not Started |
+RTL           | [PORT_FROZEN][]         | Not Started |
+RTL           | [ARCHITECTURE_FROZEN][] | Not Started |
+RTL           | [REVIEW_TODO][]         | Not Started |
+RTL           | [STYLE_X][]             | Not Started |
+Code Quality  | [LINT_PASS][]           | Not Started |
+Code Quality  | [CDC_SETUP][]           | Not Started |
+Code Quality  | [FPGA_TIMING][]         | Not Started |
+Code Quality  | [CDC_SYNCMACRO][]       | Not Started |
+Review        | Reviewer(s)             | Not Started |
+Review        | Signoff date            | Not Started |
+
+[NEW_FEATURES]:        {{<relref "/doc/project/checklist.md#new-features" >}}
+[BLOCK_DIAGRAM]:       {{<relref "/doc/project/checklist.md#block-diagram" >}}
+[DOC_INTERFACE]:       {{<relref "/doc/project/checklist.md#doc-interface" >}}
+[MISSING_FUNC]:        {{<relref "/doc/project/checklist.md#missing-func" >}}
+[FEATURE_FROZEN]:      {{<relref "/doc/project/checklist.md#feature-frozen" >}}
+[FEATURE_COMPLETE]:    {{<relref "/doc/project/checklist.md#feature-complete" >}}
+[AREA_SANITY_CHECK]:   {{<relref "/doc/project/checklist.md#area-sanity-check" >}}
+[PORT_FROZEN]:         {{<relref "/doc/project/checklist.md#port-frozen" >}}
+[ARCHITECTURE_FROZEN]: {{<relref "/doc/project/checklist.md#architecture-frozen" >}}
+[REVIEW_TODO]:         {{<relref "/doc/project/checklist.md#review-todo" >}}
+[STYLE_X]:             {{<relref "/doc/project/checklist.md#style-x" >}}
+[LINT_PASS]:           {{<relref "/doc/project/checklist.md#lint-pass" >}}
+[CDC_SETUP]:           {{<relref "/doc/project/checklist.md#cdc-setup" >}}
+[CDC_SYNCMACRO]:       {{<relref "/doc/project/checklist.md#cdc-syncmacro" >}}
+[FPGA_TIMING]:         {{<relref "/doc/project/checklist.md#fpga-timing" >}}
+
+### D3
+
+ Type         | Item                    | Resolution  | Note/Collaterals
+--------------|-------------------------|-------------|------------------
+Documentation | [NEW_FEATURES_D3][]     | Not Started |
+RTL           | [TODO_COMPLETE][]       | Not Started |
+Code Quality  | [LINT_COMPLETE][]       | Not Started |
+Code Quality  | [CDC_COMPLETE][]        | Not Started |
+Review        | [REVIEW_RTL][]          | Not Started |
+Review        | [REVIEW_DELETED_FF][]   | Not Started |
+Review        | [REVIEW_SW_CSR][]       | Not Started |
+Review        | [REVIEW_SW_FATAL_ERR][] | Not Started |
+Review        | [REVIEW_SW_CHANGE][]    | Not Started |
+Review        | [REVIEW_SW_ERRATA][]    | Not Started |
+Review        | Reviewer(s)             | Not Started |
+Review        | Signoff date            | Not Started |
+
+[NEW_FEATURES_D3]:      {{<relref "/doc/project/checklist.md#new-features-d3" >}}
+[TODO_COMPLETE]:        {{<relref "/doc/project/checklist.md#todo-complete" >}}
+[LINT_COMPLETE]:        {{<relref "/doc/project/checklist.md#lint-complete" >}}
+[CDC_COMPLETE]:         {{<relref "/doc/project/checklist.md#cdc-complete" >}}
+[REVIEW_RTL]:           {{<relref "/doc/project/checklist.md#review-rtl" >}}
+[REVIEW_DBG]:           {{<relref "/doc/project/checklist.md#review-dbg" >}}
+[REVIEW_DELETED_FF]:    {{<relref "/doc/project/checklist.md#review-deleted-ff" >}}
+[REVIEW_SW_CSR]:        {{<relref "/doc/project/checklist.md#review-sw-csr" >}}
+[REVIEW_SW_FATAL_ERR]:  {{<relref "/doc/project/checklist.md#review-sw-fatal-err" >}}
+[REVIEW_SW_CHANGE]:     {{<relref "/doc/project/checklist.md#review-sw-change" >}}
+[REVIEW_SW_ERRATA]:     {{<relref "/doc/project/checklist.md#review-sw-errata" >}}
+
+## Verification Checklist
+
+### V1
+
+ Type         | Item                                  | Resolution  | Note/Collaterals
+--------------|---------------------------------------|-------------|------------------
+Documentation | [DV_PLAN_DRAFT_COMPLETED][]           | Not Started | [${name.upper()} DV Plan]({{<relref "hw/ip/${name}/doc/dv_plan" >}})
+Documentation | [TESTPLAN_COMPLETED][]                | Not Started | [${name.upper()} Testplan]({{<relref "hw/ip/${name}/doc/dv_plan/index.md#testplan" >}})
+Testbench     | [TB_TOP_CREATED][]                    | Not Started |
+Testbench     | [PRELIMINARY_ASSERTION_CHECKS_ADDED][]| Not Started |
+Testbench     | [SIM_TB_ENV_CREATED][]                | Not Started |
+Testbench     | [SIM_RAL_MODEL_GEN_AUTOMATED][]       | Not Started |
+Testbench     | [CSR_CHECK_GEN_AUTOMATED][]           | Not Started |
+Testbench     | [TB_GEN_AUTOMATED][]                  | Not Started |
+Tests         | [SIM_SANITY_TEST_PASSING][]           | Not Started |
+Tests         | [SIM_CSR_MEM_TEST_SUITE_PASSING][]    | Not Started |
+Tests         | [FPV_MAIN_ASSERTIONS_PROVEN][]        | Not Started |
+Tool Setup    | [SIM_ALT_TOOL_SETUP][]                | Not Started |
+Regression    | [SIM_SANITY_REGRESSION_SETUP][]       | Not Started |
+Regression    | [SIM_NIGHTLY_REGRESSION_SETUP][]      | Not Started |
+Regression    | [FPV_REGRESSION_SETUP][]              | Not Started |
+Coverage      | [SIM_COVERAGE_MODEL_ADDED][]          | Not Started |
+Integration   | [PRE_VERIFIED_SUB_MODULES_V1][]       | Not Started |
+Review        | [DESIGN_SPEC_REVIEWED][]              | Not Started |
+Review        | [DV_PLAN_TESTPLAN_REVIEWED][]         | Not Started |
+Review        | [STD_TEST_CATEGORIES_PLANNED][]       | Not Started | Exception (?)
+Review        | [V2_CHECKLIST_SCOPED][]               | Not Started |
+Review        | Reviewer(s)                           | Not Started |
+Review        | Signoff date                          | Not Started |
+
+[DV_PLAN_DRAFT_COMPLETED]:            {{<relref "/doc/project/checklist.md#dv-plan-draft-completed" >}}
+[TESTPLAN_COMPLETED]:                 {{<relref "/doc/project/checklist.md#testplan-completed" >}}
+[TB_TOP_CREATED]:                     {{<relref "/doc/project/checklist.md#tb-top-created" >}}
+[PRELIMINARY_ASSERTION_CHECKS_ADDED]: {{<relref "/doc/project/checklist.md#preliminary-assertion-checks-added" >}}
+[SIM_TB_ENV_CREATED]:                 {{<relref "/doc/project/checklist.md#sim-tb-env-created" >}}
+[SIM_RAL_MODEL_GEN_AUTOMATED]:        {{<relref "/doc/project/checklist.md#sim-ral-model-gen-automated" >}}
+[CSR_CHECK_GEN_AUTOMATED]:            {{<relref "/doc/project/checklist.md#csr-check-gen-automated" >}}
+[TB_GEN_AUTOMATED]:                   {{<relref "/doc/project/checklist.md#tb-gen-automated" >}}
+[SIM_SANITY_TEST_PASSING]:            {{<relref "/doc/project/checklist.md#sim-sanity-test-passing" >}}
+[SIM_CSR_MEM_TEST_SUITE_PASSING]:     {{<relref "/doc/project/checklist.md#sim-csr-mem-test-suite-passing" >}}
+[FPV_MAIN_ASSERTIONS_PROVEN]:         {{<relref "/doc/project/checklist.md#fpv-main-assertions-proven" >}}
+[SIM_ALT_TOOL_SETUP]:                 {{<relref "/doc/project/checklist.md#sim-alt-tool-setup" >}}
+[SIM_SANITY_REGRESSION_SETUP]:        {{<relref "/doc/project/checklist.md#sim-sanity-regression-setup" >}}
+[SIM_NIGHTLY_REGRESSION_SETUP]:       {{<relref "/doc/project/checklist.md#sim-nightly-regression-setup" >}}
+[FPV_REGRESSION_SETUP]:               {{<relref "/doc/project/checklist.md#fpv-regression-setup" >}}
+[SIM_COVERAGE_MODEL_ADDED]:           {{<relref "/doc/project/checklist.md#sim-coverage-model-added" >}}
+[PRE_VERIFIED_SUB_MODULES_V1]:        {{<relref "/doc/project/checklist.md#pre-verified-sub-modules-v1" >}}
+[DESIGN_SPEC_REVIEWED]:               {{<relref "/doc/project/checklist.md#design-spec-reviewed" >}}
+[DV_PLAN_TESTPLAN_REVIEWED]:          {{<relref "/doc/project/checklist.md#dv-plan-testplan-reviewed" >}}
+[STD_TEST_CATEGORIES_PLANNED]:        {{<relref "/doc/project/checklist.md#std-test-categories-planned" >}}
+[V2_CHECKLIST_SCOPED]:                {{<relref "/doc/project/checklist.md#v2-checklist-scoped" >}}
+
+### V2
+
+ Type         | Item                                    | Resolution  | Note/Collaterals
+--------------|-----------------------------------------|-------------|------------------
+Documentation | [DESIGN_DELTAS_CAPTURED_V2][]           | Not started |
+Documentation | [DV_PLAN_COMPLETED][]                   | Not started |
+Testbench     | [ALL_INTERFACES_EXERCISED][]            | Not started |
+Testbench     | [ALL_ASSERTION_CHECKS_ADDED][]          | Not started |
+Testbench     | [SIM_TB_ENV_COMPLETED][]                | Not started |
+Tests         | [SIM_ALL_TESTS_PASSING][]               | Not started |
+Tests         | [FPV_ALL_ASSERTIONS_WRITTEN][]          | Not started |
+Tests         | [FPV_ALL_ASSUMPTIONS_REVIEWED][]        | Not started |
+Tests         | [SIM_FW_SIMULATED][]                    | Not started |
+Regression    | [SIM_NIGHTLY_REGRESSION_V2][]           | Not started |
+Coverage      | [SIM_CODE_COVERAGE_V2][]                | Not started |
+Coverage      | [SIM_FUNCTIONAL_COVERAGE_V2][]          | Not started |
+Coverage      | [FPV_CODE_COVERAGE_V2][]                | Not started |
+Coverage      | [FPV_COI_COVERAGE_V2][]                 | Not started |
+Issues        | [NO_HIGH_PRIORITY_ISSUES_PENDING][]     | Not started |
+Issues        | [ALL_LOW_PRIORITY_ISSUES_ROOT_CAUSED][] | Not started |
+Integration   | [PRE_VERIFIED_SUB_MODULES_V2][]         | Not started |
+Review        | [V3_CHECKLIST_SCOPED][]                 | Not started |
+Review        | Reviewer(s)                             | Not started |
+Review        | Signoff date                            | Not started |
+
+[DESIGN_DELTAS_CAPTURED_V2]:          {{<relref "/doc/project/checklist.md#design-deltas-captured-v2" >}}
+[DV_PLAN_COMPLETED]:                  {{<relref "/doc/project/checklist.md#dv-plan-completed" >}}
+[ALL_INTERFACES_EXERCISED]:           {{<relref "/doc/project/checklist.md#all-interfaces-exercised" >}}
+[ALL_ASSERTION_CHECKS_ADDED]:         {{<relref "/doc/project/checklist.md#all-assertion-checks-added" >}}
+[SIM_TB_ENV_COMPLETED]:               {{<relref "/doc/project/checklist.md#sim-tb-env-completed" >}}
+[SIM_ALL_TESTS_PASSING]:              {{<relref "/doc/project/checklist.md#sim-all-tests-passing" >}}
+[FPV_ALL_ASSERTIONS_WRITTEN]:         {{<relref "/doc/project/checklist.md#fpv-all-assertions-written" >}}
+[FPV_ALL_ASSUMPTIONS_REVIEWED]:       {{<relref "/doc/project/checklist.md#fpv-all-assumptions-reviewed" >}}
+[SIM_FW_SIMULATED]:                   {{<relref "/doc/project/checklist.md#sim-fw-simulated" >}}
+[SIM_NIGHTLY_REGRESSION_V2]:          {{<relref "/doc/project/checklist.md#sim-nightly-regression-v2" >}}
+[SIM_CODE_COVERAGE_V2]:               {{<relref "/doc/project/checklist.md#sim-code-coverage-v2" >}}
+[SIM_FUNCTIONAL_COVERAGE_V2]:         {{<relref "/doc/project/checklist.md#sim-functional-coverage-v2" >}}
+[FPV_CODE_COVERAGE_V2]:               {{<relref "/doc/project/checklist.md#fpv-code-coverage-v2" >}}
+[FPV_COI_COVERAGE_V2]:                {{<relref "/doc/project/checklist.md#fpv-coi-coverage-v2" >}}
+[NO_HIGH_PRIORITY_ISSUES_PENDING]:    {{<relref "/doc/project/checklist.md#no-high-priority-issues-pending" >}}
+[ALL_LOW_PRIORITY_ISSUES_ROOT_CAUSED]:{{<relref "/doc/project/checklist.md#all-low-priority-issues-root-caused" >}}
+[PRE_VERIFIED_SUB_MODULES_V2]:        {{<relref "/doc/project/checklist.md#pre-verified-sub-modules-v2" >}}
+[V3_CHECKLIST_SCOPED]:                {{<relref "/doc/project/checklist.md#v3-checklist-scoped" >}}
+
+### V3
+
+ Type         | Item                              | Resolution  | Note/Collaterals
+--------------|-----------------------------------|-------------|------------------
+Documentation | [DESIGN_DELTAS_CAPTURED_V3][]     | Not started |
+Testbench     | [ALL_TODOS_RESOLVED][]            | Not started |
+Tests         | [X_PROP_ANALYSIS_COMPLETED][]     | Not started |
+Tests         | [FPV_ASSERTIONS_PROVEN_AT_V3][]   | Not started |
+Regression    | [SIM_NIGHTLY_REGRESSION_AT_V3][]  | Not started |
+Coverage      | [SIM_CODE_COVERAGE_AT_100][]      | Not started |
+Coverage      | [SIM_FUNCTIONAL_COVERAGE_AT_100][]| Not started |
+Coverage      | [FPV_CODE_COVERAGE_AT_100][]      | Not started |
+Coverage      | [FPV_COI_COVERAGE_AT_100][]       | Not started |
+Issues        | [NO_ISSUES_PENDING][]             | Not started |
+Code Quality  | [NO_TOOL_WARNINGS_THROWN][]       | Not started |
+Integration   | [PRE_VERIFIED_SUB_MODULES_V3][]   | Not started |
+Review        | Reviewer(s)                       | Not started |
+Review        | Signoff date                      | Not started |
+
+[DESIGN_DELTAS_CAPTURED_V3]:     {{<relref "/doc/project/checklist.md#design-deltas-captured-v3" >}}
+[ALL_TODOS_RESOLVED]:            {{<relref "/doc/project/checklist.md#all-todos-resolved" >}}
+[X_PROP_ANALYSIS_COMPLETED]:     {{<relref "/doc/project/checklist.md#x-prop-analysis-completed" >}}
+[FPV_ASSERTIONS_PROVEN_AT_V3]:   {{<relref "/doc/project/checklist.md#fpv-assertions-proven-at-v3" >}}
+[SIM_NIGHTLY_REGRESSION_AT_V3]:  {{<relref "/doc/project/checklist.md#sim-nightly-regression-at-v3" >}}
+[SIM_CODE_COVERAGE_AT_100]:      {{<relref "/doc/project/checklist.md#sim-code-coverage-at-100" >}}
+[SIM_FUNCTIONAL_COVERAGE_AT_100]:{{<relref "/doc/project/checklist.md#sim-functional-coverage-at-100" >}}
+[FPV_CODE_COVERAGE_AT_100]:      {{<relref "/doc/project/checklist.md#fpv-code-coverage-at-100" >}}
+[FPV_COI_COVERAGE_AT_100]:       {{<relref "/doc/project/checklist.md#fpv-coi-coverage-at-100" >}}
+[NO_ISSUES_PENDING]:             {{<relref "/doc/project/checklist.md#no-issues-pending" >}}
+[NO_TOOL_WARNINGS_THROWN]:       {{<relref "/doc/project/checklist.md#no-tool-warnings-thrown" >}}
+[PRE_VERIFIED_SUB_MODULES_V3]:   {{<relref "/doc/project/checklist.md#pre-verified-sub-modules-v3" >}}

vendor/lowrisc_ip/uvmdvgen/env.core.tpl

@@ -7,6 +7,9 @@ description: "${name.upper()} DV UVM environment"
 filesets:
   files_dv:
     depend:
+% if has_ral:
+      - lowrisc:dv:ralgen
+% endif
 % if is_cip:
       - lowrisc:dv:cip_lib
 % else:
@@ -15,16 +18,11 @@ filesets:
 % for agent in env_agents:
       - lowrisc:dv:${agent}_agent
 % endfor
-% if has_ral:
-      - lowrisc:dv:gen_ral_pkg
-% endif
     files:
       - ${name}_env_pkg.sv
       - ${name}_env_cfg.sv: {is_include_file: true}
       - ${name}_env_cov.sv: {is_include_file: true}
-% if env_agents != []:
       - ${name}_virtual_sequencer.sv: {is_include_file: true}
-% endif
       - ${name}_scoreboard.sv: {is_include_file: true}
       - ${name}_env.sv: {is_include_file: true}
       - seq_lib/${name}_vseq_list.sv: {is_include_file: true}
@@ -33,7 +31,20 @@ filesets:
       - seq_lib/${name}_sanity_vseq.sv: {is_include_file: true}
     file_type: systemVerilogSource
 
+% if has_ral:
+generate:
+  ral:
+    generator: ralgen
+    parameters:
+      name: ${name}
+      ip_hjson: ../../data/${name}.hjson
+% endif
+
 targets:
   default:
     filesets:
       - files_dv
+% if has_ral:
+    generate:
+      - ral
+% endif

vendor/lowrisc_ip/uvmdvgen/gen_env.py

@@ -33,7 +33,8 @@ def gen_env(name, is_cip, has_ral, has_interrupts, has_alerts, env_agents,
                 ('dv/cov',          '',         '',                   ''),
                 ('dv',              '',         'Makefile',           ''),
                 ('dv',              name + '_', 'sim_cfg',            '.hjson'),
-                ('doc',             name + '_', 'dv_plan',            '.md'),
+                ('doc/dv_plan',     '',         'index',              '.md'),
+                ('doc',             '',         'checklist',          '.md'),
                 ('data',            name + '_', 'testplan',           '.hjson'),
                 ('dv',              name + '_', 'sim',                '.core')]
     # yapf: enable
@@ -48,16 +49,20 @@ def gen_env(name, is_cip, has_ral, has_interrupts, has_alerts, env_agents,
         if src == 'Makefile' and not add_makefile: continue
 
         ftpl = src + src_suffix + '.tpl'
-        fname = src_prefix + src + src_suffix
+        file_name = src_prefix + src + src_suffix
 
         if not os.path.exists(path_dir): os.system("mkdir -p " + path_dir)
-        if fname == "": continue
+        if file_name == "": continue
+
+        # Skip the checklist if it already exists.
+        file_path = os.path.join(path_dir, file_name)
+        if src == 'checklist' and os.path.exists(file_path): continue
 
         # read template
         tpl = Template(filename=resource_filename('uvmdvgen', ftpl))
 
         # create rendered file
-        with open(path_dir + "/" + fname, 'w') as fout:
+        with open(file_path, 'w') as fout:
             try:
                 fout.write(
                     tpl.render(name=name,

vendor/lowrisc_ip/uvmdvgen/index.md.tpl

@@ -19,8 +19,8 @@ ${'##'} Goals
   * Verify TileLink device protocol compliance with an SVA based testbench
 
 ${'##'} Current status
-* [Design & verification stage]({{< relref "doc/project/hw_dashboard" >}})
+* [Design & verification stage]({{< relref "hw" >}})
-  * [HW development stages]({{< relref "doc/project/hw_stages" >}})
+  * [HW development stages]({{< relref "doc/project/development_stages" >}})
 * [Simulation results](https://reports.opentitan.org/hw/ip/${name}/dv/latest/results.html)
 
 ${'##'} Design features
@@ -57,18 +57,17 @@ All common types and methods defined at the package level can be found in
 [list a few parameters, types & methods; no need to mention all]
 ```
 % if is_cip:
-
 ${'###'} TL_agent
 ${name.upper()} testbench instantiates (already handled in CIP base env) [tl_agent]({{< relref "hw/dv/sv/tl_agent/README.md" >}})
 which provides the ability to drive and independently monitor random traffic via
 TL host interface into ${name.upper()} device.
-% endif
 
+% endif
 % for agent in env_agents:
 ${'### '} ${agent.upper()} Agent
 [Describe here or add link to its README]
-% endfor
 
+% endfor
 ${'###'} UVC/agent 1
 [Describe here or add link to its README]
 
@@ -77,12 +76,11 @@ ${'###'} UVC/agent 2
 
 % if has_ral:
 ${'###'} UVM RAL Model
-The ${name.upper()} RAL model is created with the `hw/dv/tools/gen_ral_pkg.py` wrapper script at the start of the simulation automatically and is placed in the build area, along with a corresponding `fusesoc` core file.
+The ${name.upper()} RAL model is created with the [`ralgen`]({{< relref "hw/dv/tools/ralgen/README.md" >}}) FuseSoC generator script automatically when the simulation is at the build stage.
-The wrapper script invokes the [regtool.py]({{< relref "util/reggen/README.md" >}}) script from within to generate the RAL model.
+
+It can be created manually (separately) by running `make` in the the `hw/` area.
 
-It can be created manually by running `make ral` command from the `dv` area.
 % endif
-
 ${'###'} Reference models
 [Describe reference models in use if applicable, example: SHA256/HMAC]
 

vendor/lowrisc_ip/uvmdvgen/tb.sv.tpl

@@ -76,8 +76,6 @@ module tb;
         "vif", alert_names);
 % endif
     uvm_config_db#(devmode_vif)::set(null, "*.env", "devmode_vif", devmode_if);
-    uvm_config_db#(tlul_assert_ctrl_vif)::set(null, "*.env", "tlul_assert_ctrl_vif",
-        dut.tlul_assert_device.tlul_assert_ctrl_if);
     uvm_config_db#(virtual tl_if)::set(null, "*.env.m_tl_agent*", "vif", tl_if);
 % endif
 % for agent in env_agents:

vendor/lowrisc_ip/uvmdvgen/uvmdvgen.py

@@ -87,7 +87,6 @@ def main():
     parser.add_argument(
         "-ao",
         "--agent_outdir",
-        default="name",
         metavar="[hw/dv/sv]",
         help="""Path to place the agent code. A directory called <name>_agent is
                               created at this location. (default set to './<name>')"""
@@ -96,7 +95,6 @@ def main():
     parser.add_argument(
         "-eo",
         "--env_outdir",
-        default="name",
         metavar="[hw/ip/<ip>]",
         help=
         """Path to place the full tetsbench code. It creates 3 directories - dv, data and doc.
@@ -118,14 +116,16 @@ def main():
     )
 
     args = parser.parse_args()
-    if args.agent_outdir == "name": args.agent_outdir = args.name
+    if not args.agent_outdir: args.agent_outdir = args.name
-    if args.env_outdir == "name": args.env_outdir = args.name
+    if not args.env_outdir: args.env_outdir = args.name
 
-    """ The has_ral option must be set if either is_cip or has_interrupts is set,
+    # The has_ral option must be set if either is_cip or has_interrupts is set,
-        as both require use of a RAL model. As such, it is disallowed to not have
+    # as both require use of a RAL model. As such, it is disallowed to not have
-        has_ral set if one of these options is set."""
+    # has_ral set if one of these options is set.
-    if not args.has_ral:
+    if not args.has_ral and (args.is_cip or args.has_interrupts):
-        args.has_ral = args.is_cip or args.has_interrupts
+        args.has_ral = True
+        print("NOTE: --has_ral switch is enabled since either "
+              "--is_cip or --has_interrupts is set.")
 
     if args.gen_agent:
         gen_agent.gen_agent(args.name, \

vendor/lowrisc_uvmdvgen.lock.hjson

@@ -9,7 +9,7 @@
   upstream:
   {
     url: https://github.com/lowRISC/opentitan
-    rev: 0d7f7ac755d4e00811257027dd814edb2afca050
+    rev: 249b4c316cd6626d13e17edd8a52ca60c004af96
     only_subdir: util/uvmdvgen
   }
 }