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[rtl] Remove/reword comments referring to specific specifications
Referring to specific parts of a specific version of the specification can be brittle as all of these references need to be updated when we shift specification versions. It's also redundant it should be generally understood Ibex implements the RISC-V specifications and many lines could have comments that point to the part of the specification they are implementing. Rather than having a few of these for no particular reason easier to just remove them all.
This commit is contained in:
Greg Chadwick
Greg Chadwick
parent
423264ce5f
commit
1c5e6b10f5
3 changed files with 13 additions and 37 deletions
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@ -231,7 +231,7 @@ module ibex_controller #(
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// Is there an instruction in ID or WB that has yet to complete?
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assign id_wb_pending = instr_valid_i | ~ready_wb_i;
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// Exception/fault prioritisation is taken from Table 3.7 of Priviledged Spec v1.11
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// Logic to determine which exception takes priority where multiple are possible.
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if (WritebackStage) begin : g_wb_exceptions
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always_comb begin
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instr_fetch_err_prio = 0;
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@ -398,7 +398,7 @@ module ibex_controller #(
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assign irq_nm = irq_nm_ext_i | irq_nm_int;
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// Interrupts including NMI are ignored,
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// - while in debug mode [Debug Spec v0.13.2, p.39],
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// - while in debug mode,
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// - while in NMI mode (nested NMIs are not supported, NMI has highest priority and
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// cannot be interrupted by regular interrupts).
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assign handle_irq = ~debug_mode_q & ~nmi_mode_q &
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@ -615,7 +615,7 @@ module ibex_controller #(
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csr_save_if_o = 1'b1;
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csr_save_cause_o = 1'b1;
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// interrupt priorities according to Privileged Spec v1.11 p.31
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// Prioritise interrupts as required by the architecture
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if (irq_nm && !nmi_mode_q) begin
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exc_cause_o =
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irq_nm_ext_i ? ExcCauseIrqNm :
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@ -677,7 +677,7 @@ module ibex_controller #(
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// 2. EBREAK with forced entry into debug mode (ebreakm or ebreaku set).
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// regular ebreak's go through FLUSH.
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//
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// for 1. do not update dcsr and dpc, for 2. do so [Debug Spec v0.13.2, p.39]
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// for 1. do not update dcsr and dpc, for 2. do so
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// jump to debug exception handler in debug memory
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flush_id = 1'b1;
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pc_mux_o = PC_EXC;
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@ -746,34 +746,17 @@ module ibex_controller #(
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end
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ebrk_insn_prio: begin
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if (debug_mode_q | ebreak_into_debug) begin
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/*
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* EBREAK in debug mode re-enters debug mode
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*
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* "The only exception is EBREAK. When that is executed in Debug
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* Mode, it halts the hart again but without updating dpc or
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* dcsr." [Debug Spec v0.13.2, p.39]
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*/
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// EBREAK enters debug mode when dcsr.ebreakm or dcsr.ebreaku is set and we're in
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// M or U mode respectively. If we're already in debug mode we re-enter debug mode.
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/*
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* dcsr.ebreakm == 1:
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* "EBREAK instructions in M-mode enter Debug Mode."
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* [Debug Spec v0.13.2, p.42]
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*/
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pc_set_o = 1'b0;
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csr_save_id_o = 1'b0;
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csr_save_cause_o = 1'b0;
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ctrl_fsm_ns = DBG_TAKEN_ID;
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flush_id = 1'b0;
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end else begin
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/*
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* "The EBREAK instruction is used by debuggers to cause control
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* to be transferred back to a debugging environment. It
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* generates a breakpoint exception and performs no other
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* operation. [...] ECALL and EBREAK cause the receiving
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* privilege mode's epc register to be set to the address of the
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* ECALL or EBREAK instruction itself, not the address of the
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* following instruction." [Privileged Spec v1.11, p.40]
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*/
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// If EBREAK won't enter debug mode (dcsr.ebreakm/u not set) then raise a breakpoint
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// exception.
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exc_cause_o = ExcCauseBreakpoint;
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end
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end
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@ -811,7 +794,7 @@ module ibex_controller #(
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// Entering debug mode due to either single step or debug_req. Ensure
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// registers are set for exception but then enter debug handler rather
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// than exception handler [Debug Spec v0.13.2, p.44]
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// than exception handler
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// Leave all other signals as is to ensure CSRs and PC get set as if
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// core was entering exception handler, entry to debug mode will then
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// see the appropriate state and setup dpc correctly.
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@ -819,7 +802,7 @@ module ibex_controller #(
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// If an EBREAK instruction is causing us to enter debug mode on the
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// same cycle as a debug_req or single step, honor the EBREAK and
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// proceed to DBG_TAKEN_ID, as it has the highest priority.
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// [Debug Spec v1.0.0-STABLE, p.53]
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//
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// cause==EBREAK -> prio 3 (highest)
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// cause==debug_req -> prio 2
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// cause==step -> prio 1 (lowest)
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@ -5,9 +5,6 @@
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/**
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* Control and Status Registers
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*
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* Control and Status Registers (CSRs) following the RISC-V Privileged
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* Specification, draft version 1.11
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*/
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`include "prim_assert.sv"
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@ -303,7 +300,6 @@ module ibex_cs_registers #(
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assign mhpmcounter_idx = csr_addr[4:0];
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assign illegal_csr_dbg = dbg_csr & ~debug_mode_i;
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// See RISC-V Privileged Specification, version 1.11, Section 2.1
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assign illegal_csr_priv = (csr_addr[9:8] > {priv_lvl_q});
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assign illegal_csr_write = (csr_addr[11:10] == 2'b11) && csr_wr;
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assign illegal_csr_insn_o = csr_access_i & (illegal_csr | illegal_csr_write | illegal_csr_priv |
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@ -724,8 +720,8 @@ module ibex_cs_registers #(
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depc_d = exception_pc;
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depc_en = 1'b1;
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end else if (!debug_mode_i) begin
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// In debug mode, "exceptions do not update any registers. That
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// includes cause, epc, tval, dpc and mstatus." [Debug Spec v0.13.2, p.39]
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// Exceptions do not update CSRs in debug mode, so ony write these CSRs if we're not in
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// debug mode.
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mtval_en = 1'b1;
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mtval_d = csr_mtval_i;
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mstatus_en = 1'b1;
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@ -782,7 +778,6 @@ module ibex_cs_registers #(
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mcause_d = mstack_cause_q;
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end else begin
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// otherwise just set mstatus.MPIE/MPP
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// See RISC-V Privileged Specification, version 1.11, Section 3.1.6.1
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mstatus_d.mpie = 1'b1;
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mstatus_d.mpp = PRIV_LVL_U;
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end
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@ -1091,7 +1086,6 @@ module ibex_cs_registers #(
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pmp_cfg[i].exec, pmp_cfg[i].write, pmp_cfg[i].read};
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// Address field read data depends on the current programmed mode and the granularity
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// See RISC-V Privileged Specification, version 1.11, Section 3.6.1
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if (PMPGranularity == 0) begin : g_pmp_g0
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// If G == 0, read data is unmodified
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assign pmp_addr_rdata[i] = pmp_addr[i];
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@ -535,8 +535,7 @@ module ibex_id_stage #(
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// Controller //
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////////////////
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// "Executing DRET outside of Debug Mode causes an illegal instruction exception."
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// [Debug Spec v0.13.2, p.41]
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// Executing DRET outside of Debug Mode causes an illegal instruction exception.
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assign illegal_dret_insn = dret_insn_dec & ~debug_mode_o;
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// Some instructions can only be executed in M-Mode
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assign illegal_umode_insn = (priv_mode_i != PRIV_LVL_M) &
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