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[cosim,dv] Add support to set mcount registers

Browse source 
Extends RVFI connections further to include 30 mhpmcounterX registers.
Sets them up before every cosim step to let Spike know their real values.

Signed-off-by: Canberk Topal <ctopal@lowrisc.org>
This commit is contained in:
Canberk Topal 2022-07-14 21:32:46 +01:00 • committed by Canberk Topal
parent a6c182e7be
commit 1e613cc7f4
16 changed files with 180 additions and 91 deletions
Download patch file Download diff file Expand all files Collapse all files

4
dv/cosim/cosim.h
View file

@ -110,6 +110,10 @@ class Cosim {
// A full 64-bit value is provided setting both the mcycle and mcycleh CSRs.
virtual void set_mcycle(uint64_t mcycle) = 0;
// Set the value of a CSR. This is used when it is needed to have direct
// communication between DUT and Spike (e.g. Performance counters).
virtual void set_csr(const int csr_num, const uint32_t new_val) = 0;
// Tell the co-simulation model about observed transactions on the dside
// memory interface of the DUT. Accesses are notified once the response to a
// transaction is seen.

7
dv/cosim/cosim_dpi.cc
View file

@ -41,6 +41,13 @@ void riscv_cosim_set_mcycle(Cosim *cosim, svBitVecVal *mcycle) {
cosim->set_mcycle(mcycle_full);
}
void riscv_cosim_set_csr(Cosim *cosim, const int csr_id,
const svBitVecVal *csr_val) {
assert(cosim);
cosim->set_csr(csr_id, (uint32_t)csr_val[0]);
}
void riscv_cosim_notify_dside_access(Cosim *cosim, svBit store,
svBitVecVal *addr, svBitVecVal *data,
svBitVecVal *be, svBit error,

2
dv/cosim/cosim_dpi.h
View file

@ -19,6 +19,8 @@ void riscv_cosim_set_mip(Cosim *cosim, const svBitVecVal *mip);
void riscv_cosim_set_nmi(Cosim *cosim, svBit nmi);
void riscv_cosim_set_debug_req(Cosim *cosim, svBit debug_req);
void riscv_cosim_set_mcycle(Cosim *cosim, svBitVecVal *mcycle);
void riscv_cosim_set_csr(Cosim *cosim, const int csr_id,
const svBitVecVal *csr_val);
void riscv_cosim_notify_dside_access(Cosim *cosim, svBit store,
svBitVecVal *addr, svBitVecVal *data,
svBitVecVal *be, svBit error,

2
dv/cosim/cosim_dpi.svh
View file

@ -16,6 +16,8 @@ import "DPI-C" function void riscv_cosim_set_mip(chandle cosim_handle, bit [31:0
import "DPI-C" function void riscv_cosim_set_nmi(chandle cosim_handle, bit nmi);
import "DPI-C" function void riscv_cosim_set_debug_req(chandle cosim_handle, bit debug_req);
import "DPI-C" function void riscv_cosim_set_mcycle(chandle cosim_handle, bit [63:0] mcycle);
import "DPI-C" function void riscv_cosim_set_csr(chandle cosim_handle, int csr_id,
bit [31:0] csr_val);
import "DPI-C" function void riscv_cosim_notify_dside_access(chandle cosim_handle, bit store,
bit [31:0] addr, bit [31:0] data, bit [3:0] be, bit error, bit misaligned_first,
bit misaligned_second);

10
dv/cosim/spike_cosim.cc
View file

@ -366,6 +366,16 @@ void SpikeCosim::set_mcycle(uint64_t mcycle) {
processor->get_state()->mcycle->write(mcycle + 1);
}
void SpikeCosim::set_csr(const int csr_num, const uint32_t new_val) {
// Note that this is tested with ibex-cosim-v0.3 version of Spike. 'set_csr'
// method might have a hardwired zero for mhpmcounterX registers.
#ifdef OLD_SPIKE
processor->set_csr(csr_num, new_val);
#else
processor->put_csr(csr_num, new_val);
#endif
}
void SpikeCosim::notify_dside_access(const DSideAccessInfo &access_info) {
// Address must be 32-bit aligned
assert((access_info.addr & 0x3) == 0);

1
dv/cosim/spike_cosim.h
View file

@ -92,6 +92,7 @@ class SpikeCosim : public simif_t, public Cosim {
void set_nmi(bool nmi) override;
void set_debug_req(bool debug_req) override;
void set_mcycle(uint64_t mcycle) override;
void set_csr(const int csr_num, const uint32_t new_val) override;
void notify_dside_access(const DSideAccessInfo &access_info) override;
// The spike co-simulator assumes iside and dside accesses within a step are
// disjoint. If both access the same address within a step memory faults may

7
dv/uvm/core_ibex/common/ibex_cosim_agent/ibex_cosim_scoreboard.sv
View file

@ -6,6 +6,7 @@
`include "cosim_dpi.svh"
class ibex_cosim_scoreboard extends uvm_scoreboard;
import ibex_pkg::*;
chandle cosim_handle;
core_ibex_cosim_cfg cfg;
@ -124,6 +125,12 @@ class ibex_cosim_scoreboard extends uvm_scoreboard;
riscv_cosim_set_debug_req(cosim_handle, rvfi_instr.debug_req);
riscv_cosim_set_mcycle(cosim_handle, rvfi_instr.mcycle);
// Set performance counters through a pseudo-backdoor write
for (int i=0; i < 10; i++) begin
riscv_cosim_set_csr(cosim_handle, CSR_MHPMCOUNTER3 + i, rvfi_instr.mhpmcounters[i]);
riscv_cosim_set_csr(cosim_handle, CSR_MHPMCOUNTER3H + i, rvfi_instr.mhpmcountersh[i]);
end
if (!riscv_cosim_step(cosim_handle, rvfi_instr.rd_addr, rvfi_instr.rd_wdata, rvfi_instr.pc,
rvfi_instr.trap)) begin
// cosim instruction step doesn't match rvfi captured instruction, report a fatal error

5
dv/uvm/core_ibex/common/ibex_cosim_agent/ibex_rvfi_monitor.sv
View file

@ -41,6 +41,11 @@ class ibex_rvfi_monitor extends uvm_monitor;
trans_collected.debug_req = vif.monitor_cb.ext_debug_req;
trans_collected.mcycle = vif.monitor_cb.ext_mcycle;
for (int i=0; i < 10; i++) begin
trans_collected.mhpmcounters[i] = vif.monitor_cb.ext_mhpmcounters[i];
trans_collected.mhpmcountersh[i] = vif.monitor_cb.ext_mhpmcountersh[i];
end
`uvm_info(get_full_name(), $sformatf("Seen instruction:\n%s", trans_collected.sprint()),
UVM_HIGH)

5
dv/uvm/core_ibex/common/ibex_cosim_agent/ibex_rvfi_seq_item.sv
View file

@ -13,6 +13,9 @@ class ibex_rvfi_seq_item extends uvm_sequence_item;
bit debug_req;
bit [63:0] mcycle;
bit [31:0] mhpmcounters [10];
bit [31:0] mhpmcountersh [10];
`uvm_object_utils_begin(ibex_rvfi_seq_item)
`uvm_field_int (trap, UVM_DEFAULT)
`uvm_field_int (pc, UVM_DEFAULT)
@ -23,6 +26,8 @@ class ibex_rvfi_seq_item extends uvm_sequence_item;
`uvm_field_int (nmi, UVM_DEFAULT)
`uvm_field_int (debug_req, UVM_DEFAULT)
`uvm_field_int (mcycle, UVM_DEFAULT)
`uvm_field_sarray_int (mhpmcounters, UVM_DEFAULT)
`uvm_field_sarray_int (mhpmcountersh, UVM_DEFAULT)
`uvm_object_utils_end
`uvm_object_new

5
dv/uvm/core_ibex/env/core_ibex_rvfi_if.sv vendored
View file

@ -31,6 +31,9 @@ interface core_ibex_rvfi_if(input logic clk);
logic [31:0] ext_debug_req;
logic [63:0] ext_mcycle;
logic [31:0] ext_mhpmcounters [10];
logic [31:0] ext_mhpmcountersh [10];
clocking monitor_cb @(posedge clk);
input reset;
input valid;
@ -58,6 +61,8 @@ interface core_ibex_rvfi_if(input logic clk);
input ext_nmi;
input ext_debug_req;
input ext_mcycle;
input ext_mhpmcounters;
input ext_mhpmcountersh;
endclocking
task automatic wait_clks(input int num);

50
dv/uvm/core_ibex/tb/core_ibex_tb_top.sv
View file

@ -156,30 +156,32 @@ module core_ibex_tb_top;
assign instr_mem_vif.be = 0;
assign instr_mem_vif.wdata = 0;
// RVFI interface connections
assign rvfi_if.reset = ~rst_n;
assign rvfi_if.valid = dut.rvfi_valid;
assign rvfi_if.order = dut.rvfi_order;
assign rvfi_if.insn = dut.rvfi_insn;
assign rvfi_if.trap = dut.rvfi_trap;
assign rvfi_if.intr = dut.rvfi_intr;
assign rvfi_if.mode = dut.rvfi_mode;
assign rvfi_if.ixl = dut.rvfi_ixl;
assign rvfi_if.rs1_addr = dut.rvfi_rs1_addr;
assign rvfi_if.rs2_addr = dut.rvfi_rs2_addr;
assign rvfi_if.rs1_rdata = dut.rvfi_rs1_rdata;
assign rvfi_if.rs2_rdata = dut.rvfi_rs2_rdata;
assign rvfi_if.rd_addr = dut.rvfi_rd_addr;
assign rvfi_if.rd_wdata = dut.rvfi_rd_wdata;
assign rvfi_if.pc_rdata = dut.rvfi_pc_rdata;
assign rvfi_if_pc_wdata = dut.rvfi_pc_wdata;
assign rvfi_if.mem_addr = dut.rvfi_mem_addr;
assign rvfi_if.mem_rmask = dut.rvfi_mem_rmask;
assign rvfi_if.mem_rdata = dut.rvfi_mem_rdata;
assign rvfi_if.mem_wdata = dut.rvfi_mem_wdata;
assign rvfi_if.ext_mip = dut.rvfi_ext_mip;
assign rvfi_if.ext_nmi = dut.rvfi_ext_nmi;
assign rvfi_if.ext_debug_req = dut.rvfi_ext_debug_req;
assign rvfi_if.ext_mcycle = dut.rvfi_ext_mcycle;
assign rvfi_if.reset = ~rst_n;
assign rvfi_if.valid = dut.rvfi_valid;
assign rvfi_if.order = dut.rvfi_order;
assign rvfi_if.insn = dut.rvfi_insn;
assign rvfi_if.trap = dut.rvfi_trap;
assign rvfi_if.intr = dut.rvfi_intr;
assign rvfi_if.mode = dut.rvfi_mode;
assign rvfi_if.ixl = dut.rvfi_ixl;
assign rvfi_if.rs1_addr = dut.rvfi_rs1_addr;
assign rvfi_if.rs2_addr = dut.rvfi_rs2_addr;
assign rvfi_if.rs1_rdata = dut.rvfi_rs1_rdata;
assign rvfi_if.rs2_rdata = dut.rvfi_rs2_rdata;
assign rvfi_if.rd_addr = dut.rvfi_rd_addr;
assign rvfi_if.rd_wdata = dut.rvfi_rd_wdata;
assign rvfi_if.pc_rdata = dut.rvfi_pc_rdata;
assign rvfi_if_pc_wdata = dut.rvfi_pc_wdata;
assign rvfi_if.mem_addr = dut.rvfi_mem_addr;
assign rvfi_if.mem_rmask = dut.rvfi_mem_rmask;
assign rvfi_if.mem_rdata = dut.rvfi_mem_rdata;
assign rvfi_if.mem_wdata = dut.rvfi_mem_wdata;
assign rvfi_if.ext_mip = dut.rvfi_ext_mip;
assign rvfi_if.ext_nmi = dut.rvfi_ext_nmi;
assign rvfi_if.ext_debug_req = dut.rvfi_ext_debug_req;
assign rvfi_if.ext_mcycle = dut.rvfi_ext_mcycle;
assign rvfi_if.ext_mhpmcounters = dut.rvfi_ext_mhpmcounters;
assign rvfi_if.ext_mhpmcountersh = dut.rvfi_ext_mhpmcountersh;
// Irq interface connections
assign irq_vif.reset = ~rst_n;
// Dut_if interface connections

7
dv/verilator/simple_system_cosim/ibex_simple_system_cosim_checker.sv
View file

@ -18,6 +18,7 @@ module ibex_simple_system_cosim_checker (
input logic host_dmem_err
);
import "DPI-C" function chandle get_spike_cosim;
import ibex_pkg::*;
chandle cosim_handle;
@ -31,6 +32,12 @@ module ibex_simple_system_cosim_checker (
riscv_cosim_set_mip(cosim_handle, u_top.rvfi_ext_mip);
riscv_cosim_set_debug_req(cosim_handle, u_top.rvfi_ext_debug_req);
riscv_cosim_set_mcycle(cosim_handle, u_top.rvfi_ext_mcycle);
for (int i=0; i < 10; i++) begin
riscv_cosim_set_csr(cosim_handle, int'(CSR_MHPMCOUNTER3) + i,
u_top.rvfi_ext_mhpmcounters[i]);
riscv_cosim_set_csr(cosim_handle, int'(CSR_MHPMCOUNTER3H) + i,
u_top.rvfi_ext_mhpmcountersh[i]);
end
if (riscv_cosim_step(cosim_handle, u_top.rvfi_rd_addr, u_top.rvfi_rd_wdata,
u_top.rvfi_pc_rdata, u_top.rvfi_trap) == 0)

95
rtl/ibex_core.sv
View file

@ -139,7 +139,9 @@ module ibex_core import ibex_pkg::*; #(
output logic rvfi_ext_nmi,
output logic rvfi_ext_debug_req,
output logic [63:0] rvfi_ext_mcycle,
`endif
output logic [31:0] rvfi_ext_mhpmcounters [10],
output logic [31:0] rvfi_ext_mhpmcountersh [10],
`endif
// CPU Control Signals
// SEC_CM: FETCH.CTRL.LC_GATED
@ -1171,11 +1173,12 @@ module ibex_core import ibex_pkg::*; #(
// RVFI extension for co-simulation support
// debug_req and MIP captured at IF -> ID transition so one extra stage
ibex_pkg::irqs_t rvfi_ext_stage_mip [RVFI_STAGES+1];
logic rvfi_ext_stage_nmi [RVFI_STAGES+1];
logic rvfi_ext_stage_debug_req [RVFI_STAGES+1];
logic [63:0] rvfi_ext_stage_mcycle [RVFI_STAGES];
ibex_pkg::irqs_t rvfi_ext_stage_mip [RVFI_STAGES+1];
logic rvfi_ext_stage_nmi [RVFI_STAGES+1];
logic rvfi_ext_stage_debug_req [RVFI_STAGES+1];
logic [63:0] rvfi_ext_stage_mcycle [RVFI_STAGES];
logic [31:0] rvfi_ext_stage_mhpmcounters [RVFI_STAGES][10];
logic [31:0] rvfi_ext_stage_mhpmcountersh [RVFI_STAGES][10];
logic rvfi_stage_valid_d [RVFI_STAGES];
@ -1218,9 +1221,11 @@ module ibex_core import ibex_pkg::*; #(
rvfi_ext_mip[CSR_MFIX_BIT_HIGH:CSR_MFIX_BIT_LOW] = rvfi_ext_stage_mip[RVFI_STAGES].irq_fast;
end
assign rvfi_ext_nmi = rvfi_ext_stage_nmi[RVFI_STAGES];
assign rvfi_ext_debug_req = rvfi_ext_stage_debug_req[RVFI_STAGES];
assign rvfi_ext_mcycle = rvfi_ext_stage_mcycle[RVFI_STAGES-1];
assign rvfi_ext_nmi = rvfi_ext_stage_nmi [RVFI_STAGES];
assign rvfi_ext_debug_req = rvfi_ext_stage_debug_req [RVFI_STAGES];
assign rvfi_ext_mcycle = rvfi_ext_stage_mcycle [RVFI_STAGES-1];
assign rvfi_ext_mhpmcounters = rvfi_ext_stage_mhpmcounters [RVFI_STAGES-1];
assign rvfi_ext_mhpmcountersh = rvfi_ext_stage_mhpmcountersh [RVFI_STAGES-1];
// When an instruction takes a trap the `rvfi_trap` signal will be set. Instructions that take
// traps flush the pipeline so ordinarily wouldn't be seen to be retire. The RVFI tracking
@ -1352,33 +1357,35 @@ module ibex_core import ibex_pkg::*; #(
for (genvar i = 0; i < RVFI_STAGES; i = i + 1) begin : g_rvfi_stages
always_ff @(posedge clk_i or negedge rst_ni) begin
if (!rst_ni) begin
rvfi_stage_halt[i] <= '0;
rvfi_stage_trap[i] <= '0;
rvfi_stage_intr[i] <= '0;
rvfi_stage_order[i] <= '0;
rvfi_stage_insn[i] <= '0;
rvfi_stage_mode[i] <= {PRIV_LVL_M};
rvfi_stage_ixl[i] <= CSR_MISA_MXL;
rvfi_stage_rs1_addr[i] <= '0;
rvfi_stage_rs2_addr[i] <= '0;
rvfi_stage_rs3_addr[i] <= '0;
rvfi_stage_pc_rdata[i] <= '0;
rvfi_stage_pc_wdata[i] <= '0;
rvfi_stage_mem_rmask[i] <= '0;
rvfi_stage_mem_wmask[i] <= '0;
rvfi_stage_valid[i] <= '0;
rvfi_stage_rs1_rdata[i] <= '0;
rvfi_stage_rs2_rdata[i] <= '0;
rvfi_stage_rs3_rdata[i] <= '0;
rvfi_stage_rd_wdata[i] <= '0;
rvfi_stage_rd_addr[i] <= '0;
rvfi_stage_mem_rdata[i] <= '0;
rvfi_stage_mem_wdata[i] <= '0;
rvfi_stage_mem_addr[i] <= '0;
rvfi_ext_stage_mip[i+1] <= '0;
rvfi_ext_stage_nmi[i+1] <= '0;
rvfi_ext_stage_debug_req[i+1] <= '0;
rvfi_ext_stage_mcycle[i] <= '0;
rvfi_stage_halt[i] <= '0;
rvfi_stage_trap[i] <= '0;
rvfi_stage_intr[i] <= '0;
rvfi_stage_order[i] <= '0;
rvfi_stage_insn[i] <= '0;
rvfi_stage_mode[i] <= {PRIV_LVL_M};
rvfi_stage_ixl[i] <= CSR_MISA_MXL;
rvfi_stage_rs1_addr[i] <= '0;
rvfi_stage_rs2_addr[i] <= '0;
rvfi_stage_rs3_addr[i] <= '0;
rvfi_stage_pc_rdata[i] <= '0;
rvfi_stage_pc_wdata[i] <= '0;
rvfi_stage_mem_rmask[i] <= '0;
rvfi_stage_mem_wmask[i] <= '0;
rvfi_stage_valid[i] <= '0;
rvfi_stage_rs1_rdata[i] <= '0;
rvfi_stage_rs2_rdata[i] <= '0;
rvfi_stage_rs3_rdata[i] <= '0;
rvfi_stage_rd_wdata[i] <= '0;
rvfi_stage_rd_addr[i] <= '0;
rvfi_stage_mem_rdata[i] <= '0;
rvfi_stage_mem_wdata[i] <= '0;
rvfi_stage_mem_addr[i] <= '0;
rvfi_ext_stage_mip[i+1] <= '0;
rvfi_ext_stage_nmi[i+1] <= '0;
rvfi_ext_stage_debug_req[i+1] <= '0;
rvfi_ext_stage_mcycle[i] <= '0;
rvfi_ext_stage_mhpmcounters[i] <= '{10{'0}};
rvfi_ext_stage_mhpmcountersh[i] <= '{10{'0}};
end else begin
rvfi_stage_valid[i] <= rvfi_stage_valid_d[i];
@ -1411,6 +1418,12 @@ module ibex_core import ibex_pkg::*; #(
rvfi_ext_stage_nmi[i+1] <= rvfi_ext_stage_nmi[i];
rvfi_ext_stage_debug_req[i+1] <= rvfi_ext_stage_debug_req[i];
rvfi_ext_stage_mcycle[i] <= cs_registers_i.mcycle_counter_i.counter_val_o;
// This is done this way because SystemVerilog does not support looping through gen_cntrs[k]
// within a for loop.
for (int k=0; k < 10; k++) begin
rvfi_ext_stage_mhpmcounters[i][k] <= cs_registers_i.mhpmcounter[k+3][31:0];
rvfi_ext_stage_mhpmcountersh[i][k] <= cs_registers_i.mhpmcounter[k+3][63:32];
end
end
end else begin
if (rvfi_wb_done) begin
@ -1442,10 +1455,12 @@ module ibex_core import ibex_pkg::*; #(
rvfi_stage_rd_wdata[i] <= rvfi_rd_wdata_d;
rvfi_stage_mem_rdata[i] <= rvfi_mem_rdata_d;
rvfi_ext_stage_mip[i+1] <= rvfi_ext_stage_mip[i];
rvfi_ext_stage_nmi[i+1] <= rvfi_ext_stage_nmi[i];
rvfi_ext_stage_debug_req[i+1] <= rvfi_ext_stage_debug_req[i];
rvfi_ext_stage_mcycle[i] <= rvfi_ext_stage_mcycle[i-1];
rvfi_ext_stage_mip[i+1] <= rvfi_ext_stage_mip[i];
rvfi_ext_stage_nmi[i+1] <= rvfi_ext_stage_nmi[i];
rvfi_ext_stage_debug_req[i+1] <= rvfi_ext_stage_debug_req[i];
rvfi_ext_stage_mcycle[i] <= rvfi_ext_stage_mcycle[i-1];
rvfi_ext_stage_mhpmcounters[i] <= rvfi_ext_stage_mhpmcounters[i-1];
rvfi_ext_stage_mhpmcountersh[i] <= rvfi_ext_stage_mhpmcountersh[i-1];
end
end
end

56
rtl/ibex_lockstep.sv
View file

@ -399,33 +399,35 @@ module ibex_lockstep import ibex_pkg::*; #(
.double_fault_seen_o (shadow_outputs_d.double_fault_seen),
`ifdef RVFI
.rvfi_valid (),
.rvfi_order (),
.rvfi_insn (),
.rvfi_trap (),
.rvfi_halt (),
.rvfi_intr (),
.rvfi_mode (),
.rvfi_ixl (),
.rvfi_rs1_addr (),
.rvfi_rs2_addr (),
.rvfi_rs3_addr (),
.rvfi_rs1_rdata (),
.rvfi_rs2_rdata (),
.rvfi_rs3_rdata (),
.rvfi_rd_addr (),
.rvfi_rd_wdata (),
.rvfi_pc_rdata (),
.rvfi_pc_wdata (),
.rvfi_mem_addr (),
.rvfi_mem_rmask (),
.rvfi_mem_wmask (),
.rvfi_mem_rdata (),
.rvfi_mem_wdata (),
.rvfi_ext_mip (),
.rvfi_ext_nmi (),
.rvfi_ext_debug_req (),
.rvfi_ext_mcycle (),
.rvfi_valid (),
.rvfi_order (),
.rvfi_insn (),
.rvfi_trap (),
.rvfi_halt (),
.rvfi_intr (),
.rvfi_mode (),
.rvfi_ixl (),
.rvfi_rs1_addr (),
.rvfi_rs2_addr (),
.rvfi_rs3_addr (),
.rvfi_rs1_rdata (),
.rvfi_rs2_rdata (),
.rvfi_rs3_rdata (),
.rvfi_rd_addr (),
.rvfi_rd_wdata (),
.rvfi_pc_rdata (),
.rvfi_pc_wdata (),
.rvfi_mem_addr (),
.rvfi_mem_rmask (),
.rvfi_mem_wmask (),
.rvfi_mem_rdata (),
.rvfi_mem_wdata (),
.rvfi_ext_mip (),
.rvfi_ext_nmi (),
.rvfi_ext_debug_req (),
.rvfi_ext_mcycle (),
.rvfi_ext_mhpmcounters (),
.rvfi_ext_mhpmcountersh (),
`endif
.fetch_enable_i (shadow_inputs_q[0].fetch_enable),

4
rtl/ibex_top.sv
View file

@ -120,6 +120,8 @@ module ibex_top import ibex_pkg::*; #(
output logic rvfi_ext_nmi,
output logic rvfi_ext_debug_req,
output logic [63:0] rvfi_ext_mcycle,
output logic [31:0] rvfi_ext_mhpmcounters [10],
output logic [31:0] rvfi_ext_mhpmcountersh [10],
`endif
// CPU Control Signals
@ -364,6 +366,8 @@ module ibex_top import ibex_pkg::*; #(
.rvfi_ext_nmi,
.rvfi_ext_debug_req,
.rvfi_ext_mcycle,
.rvfi_ext_mhpmcounters,
.rvfi_ext_mhpmcountersh,
`endif
.fetch_enable_i (fetch_enable_buf),

11
rtl/ibex_top_tracing.sv
View file

@ -124,6 +124,13 @@ module ibex_top_tracing import ibex_pkg::*; #(
logic rvfi_ext_debug_req;
logic [63:0] rvfi_ext_mcycle;
logic [31:0] rvfi_ext_mhpmcounters [10];
logic [31:0] rvfi_ext_mhpmcountersh [10];
logic [31:0] unused_perf_regs [10];
logic [31:0] unused_perf_regsh [10];
logic [31:0] unused_rvfi_ext_mip;
logic unused_rvfi_ext_nmi;
logic unused_rvfi_ext_debug_req;
@ -135,6 +142,8 @@ module ibex_top_tracing import ibex_pkg::*; #(
assign unused_rvfi_ext_nmi = rvfi_ext_nmi;
assign unused_rvfi_ext_debug_req = rvfi_ext_debug_req;
assign unused_rvfi_ext_mcycle = rvfi_ext_mcycle;
assign unused_perf_regs = rvfi_ext_mhpmcounters;
assign unused_perf_regsh = rvfi_ext_mhpmcountersh;
ibex_top #(
.PMPEnable ( PMPEnable ),
@ -232,6 +241,8 @@ module ibex_top_tracing import ibex_pkg::*; #(
.rvfi_ext_nmi,
.rvfi_ext_debug_req,
.rvfi_ext_mcycle,
.rvfi_ext_mhpmcounters,
.rvfi_ext_mhpmcountersh,
.fetch_enable_i,
.alert_minor_o,