Remove COMPILE_OPTS from Makefile

Again, this isn't used by anything and just adds complexity.

dv/uvm/core_ibex/Makefile

@@ -43,8 +43,6 @@ export cov_merge_dir := $(OUT-SEED)/cov_merge
 export cov_merge_db_dir := $(cov_merge_dir)/merged
 export cov_report_dir := $(OUT-SEED)/cov_report
 
-# Compile time options for ibex RTL simulation
-COMPILE_OPTS        +=
 # Run time options for ibex RTL simulation
 SIM_OPTS            :=
 # Enable waveform dumping
@@ -162,7 +160,6 @@ include $(sim-cfg-mk)
 
 .PHONY: test-cfg
 test-cfg:
-	@echo "COMPILE_OPTS" $(COMPILE_OPTS)
 	@echo "SIM_OPTS" $(SIM_OPTS)
 
 ###############################################################################
@@ -393,7 +390,7 @@ all-verilog = \
   $(shell find ../../../rtl -name '*.v' -o -name '*.sv' -o -name '*.svh') \
   $(shell find ../.. -name '*.v' -o -name '*.sv' -o -name '*.svh')
 
-tb-compile-var-deps := COMMON_OPTS SIMULATOR COV WAVES COMPILE_OPTS COSIM
+tb-compile-var-deps := COMMON_OPTS SIMULATOR COV WAVES COSIM
 -include $(OUT-DIR)rtl_sim/.rtl.tb_compile.vars.mk
 tb-compile-vars-prereq = $(call vars-prereq,comp,compiling TB,$(tb-compile-var-deps))
 
@@ -412,8 +409,7 @@ $(OUT-DIR)rtl_sim/.rtl.tb_compile.stamp: \
 	         --steps=compile \
 	         ${COMMON_OPTS} \
 	         --simulator="${SIMULATOR}" \
-	         $(cov-arg) $(wave-arg) $(cosim-arg) \
-	         --cmp_opts="${COMPILE_OPTS}"
+	         $(cov-arg) $(wave-arg) $(cosim-arg)
 	$(call dump-vars,$(OUT-DIR)rtl_sim/.rtl.tb_compile.vars.mk,comp,$(tb-compile-var-deps))
 	@touch $@
 

dv/uvm/core_ibex/riscv_dv_extension/ml_testlist.yaml

@@ -23,7 +23,6 @@
 # gen_test        : Test name used by the instruction generator
 # asm_tests       : Path to directed, hand-coded assembly test file or directory
 # rtl_test        : RTL simulation test name
-# cmp_opts        : Compile options passed to the instruction generator
 # sim_opts        : Simulation options passed to the instruction generator
 # no_post_compare : Enable/disable comparison of trace log and ISS log (Optional)
 # compare_opts    : Options for the RTL & ISS trace comparison

dv/uvm/core_ibex/sim.py

@@ -54,12 +54,11 @@ def subst_vars(string, var_dict):
     return string
 
 
-def rtl_compile(compile_cmds, output_dir, lsf_cmd, opts):
+def rtl_compile(compile_cmds, output_dir, lsf_cmd):
     """Compile the testbench RTL
 
     compile_cmds is a list of commands (each a string), which will have <out>
-    and <cmp_opts> substituted. Running them in sequence should compile the
-    testbench.
+    substituted. Running them in sequence should compile the testbench.
 
     output_dir is the directory in which to generate the testbench (usually
     something like 'out/rtl_sim'). This will be substituted for <out> in the
@@ -69,17 +68,10 @@ def rtl_compile(compile_cmds, output_dir, lsf_cmd, opts):
     run them through LSF. Here, this is not used for parallelism, but might
     still be needed for licence servers.
 
-    opts is a string giving extra compilation options. This is substituted for
-    <cmp_opts> in the commands.
-
     """
     logging.info("Compiling TB")
     for cmd in compile_cmds:
-        cmd = subst_vars(cmd,
-                         {
-                             'out': output_dir,
-                             'cmp_opts': opts
-                         })
+        cmd = subst_vars(cmd, {'out': output_dir})
 
         if lsf_cmd is not None:
             cmd = lsf_cmd + ' ' + cmd
@@ -178,8 +170,6 @@ def main():
                         help="RTL simulator to use (default: vcs)")
     parser.add_argument("-v", "--verbose", dest="verbose", action="store_true",
                         help="Verbose logging")
-    parser.add_argument("--cmp_opts", type=str, default="",
-                        help="Compile options for the generator")
     parser.add_argument("--en_cov", action='store_true',
                         help="Enable coverage dump")
     parser.add_argument("--en_wave", action='store_true',
@@ -220,7 +210,7 @@ def main():
         }
         compile_cmds, sim_cmd = get_simulator_cmd(args.simulator, enables)
 
-        rtl_compile(compile_cmds, output_dir, args.lsf_cmd, args.cmp_opts)
+        rtl_compile(compile_cmds, output_dir, args.lsf_cmd)
 
     # Generate merged coverage directory and load it into appropriate GUI
     if steps['cov']:

dv/uvm/core_ibex/yaml/rtl_simulation.yaml

@@ -32,7 +32,7 @@
          -debug_access+pp
          -xlrm uniq_prior_final
          -CFLAGS '--std=c99 -fno-extended-identifiers'
-         -lca -kdb <cmp_opts> <wave_opts> <cov_opts> <cosim_opts>"
+         -lca -kdb <wave_opts> <cov_opts> <cosim_opts>"
     cov_opts: >
       -cm line+tgl+assert+fsm+branch
       -cm_tgl portsonly
@@ -81,7 +81,7 @@
               +define+UVM
               -timescale \"1 ns / 1 ps \"
               -writetoplevels <out>/top.list
-              -l <out>/compile.log <cmp_opts>"
+              -l <out>/compile.log"
   sim:
     cmd: >
       vsim -64 -c <cov_opts> -do "run -a; quit -f" +designfile -f <out>/top.list <sim_opts>  -sv_seed <seed> +access +r+w +UVM_TESTNAME=<rtl_test> +UVM_VERBOSITY=UVM_LOW +bin=<binary> +ibex_tracer_file_base="<sim_dir>/trace_core" -l <sim_dir>/sim.log
@@ -116,7 +116,6 @@
     cmd:
       - "vlib <out>/work"
       - "vlog -work <out>/work
-        <cmp_opts>
         -uvmver 1.2
         +define+UVM
         -f ibex_dv.f"
@@ -160,7 +159,6 @@
               -elaborate
               -l <out>/compile.log
               -xmlibdirpath <out>
-              <cmp_opts>
               <cov_opts>
               <wave_opts>"
     cov_opts: >