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[rtl] Switch to tc_clk_gating from pulp tech_cells_generic

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Michael Rogenmoser 2020-12-10 18:10:57 +01:00 • committed by Pirmin Vogel
parent 28be76be62
commit 24e3d1d090
2 changed files with 4 additions and 4 deletions
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2
rtl/ibex_core.sv
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@ -391,7 +391,7 @@ module ibex_core #(
// main clock gate of the core
// generates all clocks except the one for the debug unit which is
// independent
cluster_clock_gating core_clock_gate_i (
tc_clk_gating core_clock_gate_i (
.clk_i ( clk_i ),
.en_i ( clock_en ),
.test_en_i ( test_en_i ),

6
rtl/ibex_register_file_latch.sv
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@ -67,7 +67,7 @@ module ibex_register_file_latch #(
// WRITE //
///////////
// Global clock gating
cluster_clock_gating cg_we_global (
tc_clk_gating cg_we_global (
.clk_i ( clk_i ),
.en_i ( we_a_i ),
.test_en_i ( test_en_i ),
@ -99,7 +99,7 @@ module ibex_register_file_latch #(
// Individual clock gating (if integrated clock-gating cells are available)
for (genvar x = 1; x < NUM_WORDS; x++) begin : gen_cg_word_iter
cluster_clock_gating cg_i (
tc_clk_gating cg_i (
.clk_i ( clk_int ),
.en_i ( waddr_onehot_a[x] ),
.test_en_i ( test_en_i ),
@ -129,7 +129,7 @@ module ibex_register_file_latch #(
assign we_r0_dummy = we_a_i & dummy_instr_id_i;
// R0 clock gate
cluster_clock_gating cg_i (
tc_clk_gating cg_i (
.clk_i ( clk_int ),
.en_i ( we_r0_dummy ),
.test_en_i ( test_en_i ),