Fix

controller.sv

@@ -931,10 +931,13 @@ module riscv_controller
   // Assertions
   //----------------------------------------------------------------------------
 
+  // CONFIG_REGION: MERGE_ID_EX
+  `ifdef MERGE_ID_EX
   // make sure that taken branches do not happen back-to-back, as this is not
   // possible without branch prediction in the IF stage
   assert property (
     @(posedge clk) (branch_taken_ex_i) |=> (~branch_taken_ex_i) ) else $warning("Two branches back-to-back are taken");
+  `endif // MERGE_ID_EX
   assert property (
     @(posedge clk) (~(dbg_req_i & ext_req_i)) ) else $warning("Both dbg_req_i and ext_req_i are active");
 

load_store_unit.sv

@@ -93,6 +93,10 @@ module riscv_load_store_unit
     `endif
 
     input  logic         ex_valid_i,
+    // CONFIG_REGION: MERGE_ID_EX
+    `ifdef MERGE_ID_EX
+    input  logic         id_wait_i,
+    `endif
 
     output logic         busy_o
 );
@@ -447,12 +451,17 @@ module riscv_load_store_unit
       // starts from not active and stays in IDLE until request was granted
       IDLE:
       begin
-        // CONFIG_REGION: SPLITTED_ADDER
-        `ifdef  SPLITTED_ADDER
-        if(data_req_ex_i & alu_ready_i) begin
-        `else 
-        if(data_req_ex_i) begin
-        `endif
+          // CONFIG_REGION: SPLITTED_ADDER
+          `ifdef  SPLITTED_ADDER
+          if (data_req_ex_i & alu_ready_i) begin
+          `else 
+          // CONFIG_REGION: MERGE_ID_EX
+          `ifdef MERGE_ID_EX
+          if (data_req_ex_i & ~id_wait_i) begin
+          `else
+          if (data_req_ex_i) begin
+          `endif
+          `endif
           data_req_o = data_req_ex_i;
           lsu_ready_ex_o = 1'b0;
 
@@ -481,7 +490,12 @@ module riscv_load_store_unit
           `ifdef  SPLITTED_ADDER
           if (data_req_ex_i & alu_ready_i) begin
           `else 
+          // CONFIG_REGION: MERGE_ID_EX
+          `ifdef MERGE_ID_EX
+          if (data_req_ex_i & ~id_wait_i) begin
+          `else
           if (data_req_ex_i) begin
+          `endif
           `endif
             data_req_o = data_req_ex_i;
             lsu_ready_ex_o = 1'b0;

riscv_core.sv

@@ -864,6 +864,10 @@ module riscv_core
     `endif
 
     .ex_valid_i            ( ex_valid           ),
+    // CONFIG_REGION: MERGE_ID_EX
+    `ifdef MERGE_ID_EX
+    .id_wait_i             ( id_wait            ),
+    `endif
     .busy_o                ( lsu_busy           )
   );