Update google_riscv-dv to google/riscv-dv@c6acc18

Update code from upstream repository https://github.com/google/riscv-
dv to revision c6acc1897429f5245cc89b2ecee2e3eefdefd18d

* Add plusarg to enable ECALL insn in main randomized body (Harry
  Callahan)

Signed-off-by: Harry Callahan <hcallahan@lowrisc.org>
This commit is contained in:
Harry Callahan 2022-10-11 16:50:16 +01:00
parent 4608df4606
commit 25d81afef6
3 changed files with 8 additions and 1 deletions

View file

@ -9,6 +9,6 @@
upstream:
{
url: https://github.com/google/riscv-dv
rev: 9c2b007eea5baed25dc9b4c3181c2f328f98a2af
rev: c6acc1897429f5245cc89b2ecee2e3eefdefd18d
}
}

View file

@ -161,6 +161,9 @@ class riscv_instr extends uvm_object;
end
end
end
if (!cfg.no_ecall) begin
basic_instr = {basic_instr, ECALL};
end
if (cfg.no_dret == 0) begin
basic_instr = {basic_instr, DRET};
end

View file

@ -161,6 +161,8 @@ class riscv_instr_gen_config extends uvm_object;
bit no_load_store; // No load/store instruction
bit no_csr_instr; // No csr instruction
bit no_ebreak = 1; // No ebreak instruction
// Only enable ecall if you have overriden the test_done mechanism.
bit no_ecall = 1; // No ecall instruction
bit no_dret = 1; // No dret instruction
bit no_fence; // No fence instruction
bit no_wfi = 1; // No WFI instruction
@ -485,6 +487,7 @@ class riscv_instr_gen_config extends uvm_object;
`uvm_field_int(no_load_store, UVM_DEFAULT)
`uvm_field_int(no_csr_instr, UVM_DEFAULT)
`uvm_field_int(no_ebreak, UVM_DEFAULT)
`uvm_field_int(no_ecall, UVM_DEFAULT)
`uvm_field_int(no_dret, UVM_DEFAULT)
`uvm_field_int(no_fence, UVM_DEFAULT)
`uvm_field_int(no_wfi, UVM_DEFAULT)
@ -552,6 +555,7 @@ class riscv_instr_gen_config extends uvm_object;
get_int_arg_value("+num_of_sub_program=", num_of_sub_program);
get_int_arg_value("+instr_cnt=", instr_cnt);
get_bool_arg_value("+no_ebreak=", no_ebreak);
get_bool_arg_value("+no_ecall=", no_ecall);
get_bool_arg_value("+no_dret=", no_dret);
get_bool_arg_value("+no_wfi=", no_wfi);
get_bool_arg_value("+no_branch_jump=", no_branch_jump);