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[rtl] Decouple mip and mie CSRs

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This commit modifies the `mip` CSR to not depend on the `mie` CSR. While
the values of both these CSRs are combined to decide whether an
interrupt shall be handled, the RISC-V spec does not state that the
content of of `mip` should depend on `mie`. This commit better aligns
Ibex with other open-source RISC-V cores.

This resolves lowRISC/ibex#567 reported by @pfmooney.

Signed-off-by: Pirmin Vogel <vogelpi@lowrisc.org>
This commit is contained in:
Pirmin Vogel 2020-01-29 16:11:35 +01:00
parent 6708ba62ac
commit 2a42c23eaf
7 changed files with 54 additions and 79 deletions
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2
lint/verilator_waiver.vlt
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@ -58,7 +58,7 @@ lint_off -msg UNUSED -file "*/rtl/ibex_register_file_fpga.sv" -lines 20
// Signal unoptimizable: Feedback to clock or circular logic:
// ibex_core.cs_registers_i.mie_q
// Issue lowrisc/ibex#212
lint_off -msg UNOPTFLAT -file "*/rtl/ibex_cs_registers.sv" -lines 170
lint_off -msg UNOPTFLAT -file "*/rtl/ibex_cs_registers.sv" -lines 158
// Bits of signal are not used: instr_alu[24:15,11:7]
// instr flops are duplicated to reduce fan-out, neater to just leave unused