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updated vendored riscv-test-env repo

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This commit is contained in:
Saad Khalid 2023-02-09 16:40:20 +00:00 • committed by Greg Chadwick
parent 95c388ba90
commit 2c1b3c91fd
5 changed files with 49 additions and 8 deletions
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26
vendor/patches/riscv_test_env/changes.patch vendored
View file

@ -1,5 +1,5 @@
diff --git a/p/riscv_test.h b/p/riscv_test.h
index fe14f086..18fdc0a7 100644
index a8c50c7a5..f57fb4423 100644
--- a/p/riscv_test.h
+++ b/p/riscv_test.h
@@ -1,9 +1,11 @@
@ -15,7 +15,23 @@ index fe14f086..18fdc0a7 100644
//-----------------------------------------------------------------------
// Begin Macro
@@ -190,14 +192,13 @@ handle_exception: \
@@ -153,14 +155,12 @@
#define EXTRA_TVEC_MACHINE
#define EXTRA_INIT
#define EXTRA_INIT_TIMER
-#define FILTER_TRAP
-#define FILTER_PAGE_FAULT
#define INTERRUPT_HANDLER j other_exception /* No interrupts should occur */
#define RVTEST_CODE_BEGIN \
.section .text.init; \
- .align 6; \
+ .org 0x80; \
.weak stvec_handler; \
.weak mtvec_handler; \
.globl _start; \
@@ -192,14 +192,13 @@ handle_exception: \
1: ori TESTNUM, TESTNUM, 1337; \
write_tohost: \
sw TESTNUM, tohost, t5; \
@ -32,7 +48,7 @@ index fe14f086..18fdc0a7 100644
li TESTNUM, 0; \
la t0, trap_vector; \
csrw mtvec, t0; \
@@ -212,7 +213,7 @@ reset_vector: \
@@ -214,7 +213,7 @@ reset_vector: \
(1 << CAUSE_MISALIGNED_FETCH) | \
(1 << CAUSE_USER_ECALL) | \
(1 << CAUSE_BREAKPOINT); \
@ -41,7 +57,7 @@ index fe14f086..18fdc0a7 100644
1: csrwi mstatus, 0; \
init; \
EXTRA_INIT; \
@@ -236,20 +237,24 @@ reset_vector: \
@@ -238,20 +237,24 @@ reset_vector: \
#define RVTEST_PASS \
fence; \
@ -76,7 +92,7 @@ index fe14f086..18fdc0a7 100644
//-----------------------------------------------------------------------
// Data Section Macro
@@ -260,8 +265,8 @@ reset_vector: \
@@ -262,8 +265,8 @@ reset_vector: \
#define RVTEST_DATA_BEGIN \
EXTRA_DATA \
.pushsection .tohost,"aw",@progbits; \

2
vendor/riscv-test-env/p/riscv_test.h vendored
View file

@ -160,7 +160,7 @@
#define RVTEST_CODE_BEGIN \
.section .text.init; \
.align 6; \
.org 0x80; \
.weak stvec_handler; \
.weak mtvec_handler; \
.globl _start; \

10
vendor/riscv-test-env/v/riscv_test.h vendored
View file

@ -24,6 +24,16 @@
extra_boot: \
EXTRA_INIT \
ret; \
.global trap_filter; \
trap_filter: \
FILTER_TRAP \
li a0, 0; \
ret; \
.global pf_filter; \
pf_filter: \
FILTER_PAGE_FAULT \
li a0, 0; \
ret; \
.global userstart; \
userstart: \
init

15
vendor/riscv-test-env/v/vm.c vendored
View file

@ -136,8 +136,14 @@ static void evict(unsigned long addr)
}
}
extern int pf_filter(uintptr_t addr, uintptr_t *pte, int *copy);
extern int trap_filter(trapframe_t *tf);
void handle_fault(uintptr_t addr, uintptr_t cause)
{
uintptr_t filter_encodings = 0;
int copy_page = 1;
assert(addr >= PGSIZE && addr < MAX_TEST_PAGES * PGSIZE);
addr = addr/PGSIZE*PGSIZE;
@ -159,6 +165,11 @@ void handle_fault(uintptr_t addr, uintptr_t cause)
freelist_tail = 0;
uintptr_t new_pte = (node->addr >> PGSHIFT << PTE_PPN_SHIFT) | PTE_V | PTE_U | PTE_R | PTE_W | PTE_X;
if (pf_filter(addr, &filter_encodings, &copy_page)) {
new_pte = (node->addr >> PGSHIFT << PTE_PPN_SHIFT) | filter_encodings;
}
user_llpt[addr/PGSIZE] = new_pte | PTE_A | PTE_D;
flush_page(addr);
@ -177,6 +188,10 @@ void handle_fault(uintptr_t addr, uintptr_t cause)
void handle_trap(trapframe_t* tf)
{
if (trap_filter(tf)) {
pop_tf(tf);
}
if (tf->cause == CAUSE_USER_ECALL)
{
int n = tf->gpr[10];

4
vendor/riscv_test_env.lock.hjson vendored
View file

@ -8,8 +8,8 @@
{
upstream:
{
url: https://github.com/riscv/riscv-test-env
rev: 34a1175291f9531e85afdb89aaa77707f45fc8e4
url: https://github.com/riscv/riscv-test-env/
rev: 982f93f5c55f6e7931c01afb082f5ca42cffddab
}
patch_dir: "patches/riscv_test_env"
}