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Map hardware loop registers to CSR, so they can be saved/restored for
irqs
This commit is contained in:
Andreas Traber
parent
5678ed7a75
commit
2c5e9b9407
3 changed files with 78 additions and 19 deletions
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@ -27,6 +27,8 @@
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module riscv_cs_registers
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#(
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parameter N_HWLP = 2,
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parameter N_HWLP_BITS = $clog2(N_HWLP),
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parameter N_EXT_PERF_COUNTERS = 0
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)
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(
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@ -55,6 +57,15 @@ module riscv_cs_registers
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input logic [5:0] exc_cause_i,
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input logic save_exc_cause_i,
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// Hardware loops
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input logic [N_HWLP-1:0] [31:0] hwlp_start_i,
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input logic [N_HWLP-1:0] [31:0] hwlp_end_i,
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input logic [N_HWLP-1:0] [31:0] hwlp_cnt_i,
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output logic [31:0] hwlp_data_o,
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output logic [N_HWLP_BITS-1:0] hwlp_regid_o,
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output logic [2:0] hwlp_we_o,
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// Performance Counters
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input logic id_valid_i, // ID stage is done
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input logic is_compressed_i, // compressed instruction in ID
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@ -143,6 +154,14 @@ module riscv_cs_registers
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12'hF01: csr_rdata_int = 32'h00_00_80_00;
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// mhartid: unique hardware thread id
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12'hF10: csr_rdata_int = {22'b0, cluster_id_i, core_id_i};
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// hardware loops
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12'h7B0: csr_rdata_int = hwlp_start_i[0];
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12'h7B1: csr_rdata_int = hwlp_end_i[0];
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12'h7B2: csr_rdata_int = hwlp_cnt_i[0];
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12'h7B4: csr_rdata_int = hwlp_start_i[1];
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12'h7B5: csr_rdata_int = hwlp_end_i[1];
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12'h7B6: csr_rdata_int = hwlp_cnt_i[1];
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endcase
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end
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@ -164,9 +183,19 @@ module riscv_cs_registers
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12'h341: if (csr_we_int) csr_n[`CSR_IDX_MEPC] = csr_wdata_int;
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// mcause
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12'h342: if (csr_we_int) exc_cause_n = {csr_wdata_int[5], csr_wdata_int[4:0]};
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// hardware loops
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12'h7B0: if (csr_we_int) begin hwlp_we_o = 2'b00; hwlp_regid_o = 1'b0; end
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12'h7B1: if (csr_we_int) begin hwlp_we_o = 2'b01; hwlp_regid_o = 1'b0; end
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12'h7B2: if (csr_we_int) begin hwlp_we_o = 2'b10; hwlp_regid_o = 1'b0; end
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12'h7B4: if (csr_we_int) begin hwlp_we_o = 2'b00; hwlp_regid_o = 1'b1; end
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12'h7B5: if (csr_we_int) begin hwlp_we_o = 2'b01; hwlp_regid_o = 1'b1; end
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12'h7B6: if (csr_we_int) begin hwlp_we_o = 2'b10; hwlp_regid_o = 1'b1; end
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endcase
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end
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assign hwlp_data_o = csr_wdata_int;
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// CSR operation logic
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always_comb
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44
id_stage.sv
44
id_stage.sv
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@ -119,6 +119,11 @@ module riscv_id_stage
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output logic [N_HWLP-1:0] [31:0] hwlp_end_o,
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output logic [N_HWLP-1:0] [31:0] hwlp_cnt_o,
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// hwloop signals from CS register
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input logic [N_HWLP_BITS-1:0] csr_hwlp_regid_i,
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input logic [2:0] csr_hwlp_we_i,
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input logic [31:0] csr_hwlp_data_i,
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// Interface to load store unit
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output logic data_req_ex_o,
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output logic data_we_ex_o,
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@ -259,16 +264,16 @@ module riscv_id_stage
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logic data_req_id;
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// hwloop signals
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logic [N_HWLP_BITS-1:0] hwloop_regid;
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logic [2:0] hwloop_we;
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logic hwloop_target_mux_sel;
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logic hwloop_start_mux_sel;
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logic hwloop_cnt_mux_sel;
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logic [N_HWLP_BITS-1:0] hwloop_regid, hwloop_regid_int;
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logic [2:0] hwloop_we, hwloop_we_int;
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logic hwloop_target_mux_sel;
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logic hwloop_start_mux_sel;
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logic hwloop_cnt_mux_sel;
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logic [31:0] hwloop_target;
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logic [31:0] hwloop_start;
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logic [31:0] hwloop_end;
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logic [31:0] hwloop_cnt;
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logic [31:0] hwloop_target;
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logic [31:0] hwloop_start, hwloop_start_int;
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logic [31:0] hwloop_end;
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logic [31:0] hwloop_cnt, hwloop_cnt_int;
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// CSR control
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logic csr_access;
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@ -333,7 +338,7 @@ module riscv_id_stage
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///////////////////////////////////////////////
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// hwloop register id
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assign hwloop_regid = instr[8:7]; // rd contains hwloop register id
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assign hwloop_regid_int = instr[8:7]; // rd contains hwloop register id
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// hwloop target mux
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always_comb
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@ -348,23 +353,28 @@ module riscv_id_stage
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always_comb
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begin
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unique case (hwloop_start_mux_sel)
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1'b0: hwloop_start = hwloop_target; // for PC + I imm
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1'b1: hwloop_start = current_pc_if_i; // for next PC
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1'b0: hwloop_start_int = hwloop_target; // for PC + I imm
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1'b1: hwloop_start_int = current_pc_if_i; // for next PC
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endcase
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end
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// hwloop end mux
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assign hwloop_end = hwloop_target;
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// hwloop cnt mux
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always_comb
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begin : hwloop_cnt_mux
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unique case (hwloop_cnt_mux_sel)
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1'b0: hwloop_cnt = imm_iz_type;
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1'b1: hwloop_cnt = operand_a_fw_id;
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1'b0: hwloop_cnt_int = imm_iz_type;
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1'b1: hwloop_cnt_int = operand_a_fw_id;
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endcase;
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end
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// multiplex between access from instructions and access via CSR registers
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assign hwloop_start = hwloop_we_int[0] ? hwloop_start_int : csr_hwlp_data_i;
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assign hwloop_end = hwloop_we_int[1] ? hwloop_target : csr_hwlp_data_i;
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assign hwloop_cnt = hwloop_we_int[2] ? hwloop_cnt_int : csr_hwlp_data_i;
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assign hwloop_regid = (|hwloop_we_int) ? hwloop_regid_int : csr_hwlp_regid_i;
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assign hwloop_we = (|hwloop_we_int) ? hwloop_we_int : csr_hwlp_we_i;
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//////////////////////////////////////////////////////////////////
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// _ _____ _ //
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@ -601,7 +611,7 @@ module riscv_id_stage
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.data_reg_offset_o ( data_reg_offset_id ),
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// hwloop signals
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.hwloop_we_o ( hwloop_we ),
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.hwloop_we_o ( hwloop_we_int ),
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.hwloop_target_mux_sel_o ( hwloop_target_mux_sel ),
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.hwloop_start_mux_sel_o ( hwloop_start_mux_sel ),
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.hwloop_cnt_mux_sel_o ( hwloop_cnt_mux_sel ),
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@ -83,7 +83,8 @@ module riscv_core
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input logic [N_EXT_PERF_COUNTERS-1:0] ext_perf_counters_i
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);
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localparam N_HWLP = 2;
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localparam N_HWLP = 2;
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localparam N_HWLP_BITS = $clog2(N_HWLP);
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// IF/ID signals
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@ -198,6 +199,11 @@ module riscv_core
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logic [N_HWLP-1:0] [31:0] hwlp_end;
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logic [N_HWLP-1:0] [31:0] hwlp_cnt;
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// used to write from CS registers to hardware loop registers
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logic [N_HWLP_BITS-1:0] csr_hwlp_regid;
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logic [2:0] csr_hwlp_we;
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logic [31:0] csr_hwlp_data;
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// Debug Unit
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logic dbg_stall;
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@ -277,7 +283,7 @@ module riscv_core
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.exc_pc_mux_i ( exc_pc_mux_id ),
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.exc_vec_pc_mux_i ( exc_vec_pc_mux_id ),
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// from hwloop controller
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// from hwloop registers
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.hwlp_start_i ( hwlp_start ),
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.hwlp_end_i ( hwlp_end ),
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.hwlp_cnt_i ( hwlp_cnt ),
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@ -393,6 +399,11 @@ module riscv_core
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.hwlp_end_o ( hwlp_end ),
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.hwlp_cnt_o ( hwlp_cnt ),
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// hardware loop signals from CSR
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.csr_hwlp_regid_i ( csr_hwlp_regid ),
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.csr_hwlp_we_i ( csr_hwlp_we ),
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.csr_hwlp_data_i ( csr_hwlp_data ),
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// LSU
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.data_req_ex_o ( data_req_ex ), // to load store unit
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.data_we_ex_o ( data_we_ex ), // to load store unit
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@ -601,6 +612,15 @@ module riscv_core
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.exc_cause_i ( exc_cause ),
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.save_exc_cause_i ( save_exc_cause ),
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// from hwloop registers
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.hwlp_start_i ( hwlp_start ),
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.hwlp_end_i ( hwlp_end ),
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.hwlp_cnt_i ( hwlp_cnt ),
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.hwlp_regid_o ( csr_hwlp_regid ),
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.hwlp_we_o ( csr_hwlp_we ),
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.hwlp_data_o ( csr_hwlp_data ),
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// performance counter related signals
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.id_valid_i ( id_valid ),
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.is_compressed_i ( is_compressed_id ),
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