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Remove dead wb_stage file and module

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This commit is contained in:
Andreas Traber 2015-08-28 17:17:46 +02:00
parent 1cbbcfb90b
commit 2c93147fc3
2 changed files with 1 additions and 70 deletions
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21
riscv_core.sv
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@ -164,7 +164,6 @@ module riscv_core
logic data_req_ex;
logic [31:0] data_addr_ex;
logic data_misaligned_ex;
logic [31:0] data_rdata_int;
logic data_ack_int;
// Signals between instruction core interface and pipe (if and id stages)
@ -518,24 +517,6 @@ module riscv_core
);
/////////////////////////////////////////////////////////
// __ ______ ____ _____ _ ____ _____ //
// \ \ / / __ ) / ___|_ _|/ \ / ___| ____| //
// \ \ /\ / /| _ \ \___ \ | | / _ \| | _| _| //
// \ V V / | |_) | ___) || |/ ___ \ |_| | |___ //
// \_/\_/ |____/ |____/ |_/_/ \_\____|_____| //
// //
/////////////////////////////////////////////////////////
// TODO: the wb stage does absolutely nothing anymore, consider removing it
wb_stage wb_stage_i
(
// Mux inputs
.data_rdata_i ( data_rdata_int ),
// Mux output
.regfile_wdata_o ( regfile_wdata )
);
////////////////////////////////////////////////////////////////////////////////////////
// _ ___ _ ____ ____ _____ ___ ____ _____ _ _ _ _ ___ _____ //
// | | / _ \ / \ | _ \ / ___|_ _/ _ \| _ \| ____| | | | | \ | |_ _|_ _| //
@ -556,7 +537,7 @@ module riscv_core
.data_reg_offset_ex_i ( data_reg_offset_ex ),
.data_sign_ext_ex_i ( data_sign_ext_ex ), // sign extension
.data_rdata_ex_o ( data_rdata_int ),
.data_rdata_ex_o ( regfile_wdata ),
.data_req_ex_i ( data_req_ex ),
.data_addr_ex_i ( data_addr_ex ),
.data_ack_int_o ( data_ack_int ), // ack used in controller to stall

50
wb_stage.sv
View file

@ -1,50 +0,0 @@
////////////////////////////////////////////////////////////////////////////////
// Company: IIS @ ETHZ - Federal Institute of Technology //
// DEI @ UNIBO - University of Bologna //
// //
// Engineer: Renzo Andri - andrire@student.ethz.ch //
// //
// Additional contributions by: //
// Igor Loi - igor.loi@unibo.it //
// //
// //
// Create Date: 01/07/2014 //
// Design Name: Write Back stage //
// Module Name: wb_stage.sv //
// Project Name: RI5CY //
// Language: SystemVerilog //
// //
// Description: Execution stage: hosts a Multiplexer that select data to //
// write in the register file (from data interface or SP reg //
// //
// Revision: //
// Revision v0.1 - File Created //
// Revision v0.2 - (August 6th 2014) Changed port and signal names, addedd //
// comments //
// //
// //
// //
////////////////////////////////////////////////////////////////////////////////
// sp = special register
// id = instruction decode
// if = instruction fetch
// ex = execute stage
// wb = write back
// data = from data memory
`include "defines.sv"
module wb_stage
(
// MUX INPUTS
input logic [31:0] data_rdata_i, // read Data from data memory system
// MUX OUTPUT
output logic [31:0] regfile_wdata_o // write data for register file
);
assign regfile_wdata_o = data_rdata_i;
endmodule