[DV] Update csr description for U-mode changes (#387)

dv/uvm/riscv_dv_extension/csr_description.yaml

@@ -61,7 +61,7 @@
       msb: 25
       lsb: 0
 
-# TODO(udij) - clarify expected write behavior
+# Ibex's implementation of MHARTID is read-only
 # MHARTID
 #- csr: mhartid
 #  description: >
@@ -84,34 +84,51 @@
 #      msb: 3
 #      lsb: 0
 
+# TODO(udinator) - wait until riscv-config yaml format is ready to deal with xSTATUS CSRs, as mpp
+# fields need to be constrained such that their value after every operation is within the allowed
+# range of values - too much complexity for the current format
 # MSTATUS
-- csr: mstatus
-  descriptipn: >
-    Controls hart's current operating state
-  address: 0x300
-  privilege_mode: M
-  rv32:
-    - field_name: mpp
-      description: >
-        Previous privilege mode
-      type: R
-      reset_val: 0x3
-      msb: 12
-      lsb: 11
-    - field_name: mpie
-      description: >
-        Previous value of interrupt-enable bit
-      type: WARL
-      reset_val: 0
-      msb: 7
-      lsb: 7
-    - field_name: mie
-      description: >
-        M-mode interrupt enable
-      type: WARL
-      reset_val: 0
-      msb: 3
-      lsb: 3
+#- csr: mstatus
+#  description: >
+#    Controls hart's current operating state
+#  address: 0x300
+#  privilege_mode: M
+#  rv32:
+#    - field_name: tw
+#      description: >
+#        Timeout Wait (WFI from U-mode will trap to M-mode)
+#      type: WARL
+#      reset_val: 0
+#      msb: 21
+#      lsb: 21
+#    - field_name: mprv
+#      description: >
+#        Modify Privilege (Loads and stores use MPP for privilege checking)
+#      type: WARL
+#      reset_val: 0
+#      msb: 17
+#      lsb: 17
+#    - field_name: mpp
+#      desription : >
+#        Previous privilege mode
+#      type: R
+#      reset_val: 0
+#      msb: 12
+#      lsb: 11
+#    - field_name: mpie
+#      description: >
+#        Previous value of interrupt-enable bit
+#      type: WARL
+#      reset_val: 1
+#      msb: 7
+#      lsb: 7
+#    - field_name: mie
+#      description: >
+#        M-mode interrupt enable
+#      type: WARL
+#      reset_val: 0
+#      msb: 3
+#      lsb: 3
 
 # MIP
 - csr: mip