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changed module names into littleriscv

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This commit is contained in:
Pasquale Davide Schiavone 2017-01-18 10:41:40 +01:00
parent dee7ba63a1
commit 2d78d214de
27 changed files with 56 additions and 55 deletions
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2
alu.sv
View file

@ -27,7 +27,7 @@
import riscv_defines::*;
module riscv_alu
module littleriscv_alu
(
input logic clk,
input logic rst_n,

2
alu_div.sv
View file

@ -23,7 +23,7 @@
//
///////////////////////////////////////////////////////////////////////////////
module riscv_alu_div
module littleriscv_alu_div
#(
parameter C_WIDTH = 32,
parameter C_LOG_WIDTH = 6

2
alu_simplified.sv
View file

@ -25,7 +25,7 @@
import riscv_defines::*;
module riscv_alu_simplified
module littleriscv_alu_simplified
(
input logic clk,
input logic rst_n,

2
alu_simplified_splitted.sv
View file

@ -25,7 +25,7 @@
import riscv_defines::*;
module riscv_alu_simplified_splitted
module littleriscv_alu_simplified_splitted
(
input logic clk,
input logic rst_n,

2
compressed_decoder.sv
View file

@ -23,7 +23,7 @@
import riscv_defines::*;
module riscv_compressed_decoder
module littleriscv_compressed_decoder
(
input logic [31:0] instr_i,
output logic [31:0] instr_o,

6
controller.sv
View file

@ -29,7 +29,7 @@
import riscv_defines::*;
module riscv_controller
module littleriscv_controller
#(
parameter REG_ADDR_WIDTH = 5
)
@ -148,8 +148,8 @@ module riscv_controller
begin
// print warning in case of decoding errors
if (is_decoding_o && illegal_insn_i) begin
$display("%t: Illegal instruction (core %0d) at PC 0x%h:", $time, riscv_core.core_id_i,
riscv_id_stage.pc_id_i);
$display("%t: Illegal instruction (core %0d) at PC 0x%h:", $time, littleriscv_core.core_id_i,
littleriscv_id_stage.pc_id_i);
end
end
// synopsys translate_on

2
cs_registers.sv
View file

@ -33,7 +33,7 @@ import riscv_defines::*;
`endif
`endif
module riscv_cs_registers
module littleriscv_cs_registers
#(
parameter N_EXT_CNT = 0
)

2
debug_unit.sv
View file

@ -23,7 +23,7 @@
import riscv_defines::*;
module riscv_debug_unit
module littleriscv_debug_unit
#(
parameter REG_ADDR_WIDTH = 5
)

2
decoder.sv
View file

@ -29,7 +29,7 @@
import riscv_defines::*;
module riscv_decoder
module littleriscv_decoder
(
// singals running to/from controller
input logic deassert_we_i, // deassert we, we are stalled or not active

4
ex_stage.sv
View file

@ -31,7 +31,7 @@
import riscv_defines::*;
module riscv_ex_stage
module littleriscv_ex_stage
#(
parameter REG_ADDR_WIDTH = 5
)
@ -121,7 +121,7 @@ module riscv_ex_stage
riscv_alu_simplified alu_i
littleriscv_alu_simplified alu_i
(
.clk ( clk ),
.rst_n ( rst_n ),

2
exc_controller.sv
View file

@ -24,7 +24,7 @@
import riscv_defines::*;
module riscv_exc_controller
module littleriscv_exc_controller
(
input logic clk,
input logic rst_n,

2
hwloop_controller.sv
View file

@ -22,7 +22,7 @@
// //
////////////////////////////////////////////////////////////////////////////////
module riscv_hwloop_controller
module littleriscv_hwloop_controller
#(
parameter N_REGS = 2
)

2
hwloop_regs.sv
View file

@ -22,7 +22,7 @@
// //
////////////////////////////////////////////////////////////////////////////////
module riscv_hwloop_regs
module littleriscv_hwloop_regs
#(
parameter N_REGS = 2,
parameter N_REG_BITS = $clog2(N_REGS)

11
id_stage.sv
View file

@ -37,7 +37,7 @@ import riscv_defines::*;
`define REG_D 11:07
module riscv_id_stage
module littleriscv_id_stage
#(
parameter REG_ADDR_WIDTH = 5
@ -493,7 +493,7 @@ module riscv_id_stage
// //
/////////////////////////////////////////////////////////
riscv_register_file registers_i
littleriscv_register_file registers_i
(
.clk ( clk ),
.rst_n ( rst_n ),
@ -526,7 +526,7 @@ module riscv_id_stage
// //
///////////////////////////////////////////////
riscv_decoder decoder_i
littleriscv_decoder decoder_i
(
// controller related signals
.deassert_we_i ( deassert_we ),
@ -589,7 +589,7 @@ module riscv_id_stage
// //
////////////////////////////////////////////////////////////////////
riscv_controller controller_i
littleriscv_controller controller_i
(
.clk ( clk ),
.rst_n ( rst_n ),
@ -696,7 +696,7 @@ module riscv_id_stage
assign irq_ack_o = exc_ack;
riscv_exc_controller exc_controller_i
littleriscv_exc_controller exc_controller_i
(
.clk ( clk ),
.rst_n ( rst_n ),
@ -754,7 +754,6 @@ module riscv_id_stage
data_reg_offset_ex_o = 2'b0;
alu_operator_ex_o = alu_operator;
alu_operand_a_ex_o = alu_operand_a;
alu_operand_b_ex_o = alu_operand_b;

8
if_stage.sv
View file

@ -29,7 +29,7 @@
import riscv_defines::*;
module riscv_if_stage #(
module littleriscv_if_stage #(
parameter RDATA_WIDTH = 32
)
(
@ -134,7 +134,7 @@ module riscv_if_stage #(
generate
if (RDATA_WIDTH == 32) begin : prefetch_32
// prefetch buffer, caches a fixed number of instructions
riscv_prefetch_buffer prefetch_buffer_i
littleriscv_prefetch_buffer prefetch_buffer_i
(
.clk ( clk ),
.rst_n ( rst_n ),
@ -162,7 +162,7 @@ module riscv_if_stage #(
);
end else if (RDATA_WIDTH == 128) begin : prefetch_128
// prefetch buffer, caches a fixed number of instructions
riscv_prefetch_L0_buffer prefetch_buffer_i
littleriscv_prefetch_L0_buffer prefetch_buffer_i
(
.clk ( clk ),
.rst_n ( rst_n ),
@ -268,7 +268,7 @@ module riscv_if_stage #(
logic illegal_c_insn;
logic instr_compressed_int;
riscv_compressed_decoder compressed_decoder_i
littleriscv_compressed_decoder compressed_decoder_i
(
.instr_i ( fetch_rdata ),
.instr_o ( instr_decompressed ),

20
riscv_core.sv → littleriscv_core.sv
View file

@ -29,7 +29,7 @@
import riscv_defines::*;
module riscv_core
module littleriscv_core
#(
parameter N_EXT_PERF_COUNTERS = 0,
parameter INSTR_RDATA_WIDTH = 32,
@ -44,9 +44,9 @@ module riscv_core
input logic test_en_i, // enable all clock gates for testing
// Core ID, Cluster ID and boot address are considered more or less static
input logic [31:0] boot_addr_i,
input logic [ 3:0] core_id_i,
input logic [ 5:0] cluster_id_i,
input logic [31:0] boot_addr_i,
// Instruction memory interface
output logic instr_req_o,
@ -285,7 +285,7 @@ module riscv_core
// |___|_| |____/ |_/_/ \_\____|_____| //
// //
//////////////////////////////////////////////////
riscv_if_stage
littleriscv_if_stage
#(
.RDATA_WIDTH ( INSTR_RDATA_WIDTH )
)
@ -350,7 +350,7 @@ module riscv_core
// |___|____/ |____/ |_/_/ \_\____|_____| //
// //
/////////////////////////////////////////////////
riscv_id_stage
littleriscv_id_stage
#(
)
id_stage_i
@ -493,7 +493,7 @@ module riscv_core
// |_____/_/\_\ |____/ |_/_/ \_\____|_____| //
// //
/////////////////////////////////////////////////////
riscv_ex_stage ex_stage_i
littleriscv_ex_stage ex_stage_i
(
// Global signals: Clock and active low asynchronous reset
.clk ( clk ),
@ -553,7 +553,7 @@ module riscv_core
// //
////////////////////////////////////////////////////////////////////////////////////////
riscv_load_store_unit load_store_unit_i
littleriscv_load_store_unit load_store_unit_i
(
.clk ( clk ),
.rst_n ( rst_ni ),
@ -614,7 +614,7 @@ module riscv_core
// Control and Status Registers //
//////////////////////////////////////
riscv_cs_registers
littleriscv_cs_registers
#(
.N_EXT_CNT ( N_EXT_PERF_COUNTERS )
)
@ -689,7 +689,7 @@ module riscv_core
// //
/////////////////////////////////////////////////////////////
riscv_debug_unit debug_unit_i
littleriscv_debug_unit debug_unit_i
(
.clk ( clk_i ), // always-running clock for debug
.rst_n ( rst_ni ),
@ -749,7 +749,7 @@ module riscv_core
`ifdef TRACE_EXECUTION
riscv_tracer riscv_tracer_i
littleriscv_tracer riscv_tracer_i
(
.clk ( clk_i ), // always-running clock for tracing
.rst_n ( rst_ni ),
@ -807,7 +807,7 @@ module riscv_core
logic is_interrupt;
assign is_interrupt = (pc_mux_id == PC_EXCEPTION) && (exc_pc_mux_id == EXC_PC_IRQ);
riscv_simchecker riscv_simchecker_i
littleriscv_simchecker riscv_simchecker_i
(
.clk ( clk_i ), // always-running clock for tracing
.rst_n ( rst_ni ),

2
load_store_unit.sv
View file

@ -26,7 +26,7 @@
`include "riscv_config.sv"
module riscv_load_store_unit
module littleriscv_load_store_unit
(
input logic clk,
input logic rst_n,

2
mult.sv
View file

@ -25,7 +25,7 @@
import riscv_defines::*;
module riscv_mult
module littleriscv_mult
(
input logic clk,
input logic rst_n,

6
prefetch_L0_buffer.sv
View file

@ -26,7 +26,7 @@
`include "riscv_config.sv"
module riscv_prefetch_L0_buffer
module littleriscv_prefetch_L0_buffer
#(
parameter RDATA_IN_WIDTH = 128
)
@ -91,7 +91,7 @@ module riscv_prefetch_L0_buffer
logic aligned_is_compressed, unaligned_is_compressed;
prefetch_L0_buffer_L0
littleprefetch_L0_buffer_L0
#(
.RDATA_IN_WIDTH ( RDATA_IN_WIDTH )
)
@ -466,7 +466,7 @@ module riscv_prefetch_L0_buffer
endmodule // prefetch_L0_buffer
module prefetch_L0_buffer_L0
module littleprefetch_L0_buffer_L0
#(
parameter RDATA_IN_WIDTH = 128
)

6
prefetch_buffer.sv
View file

@ -26,7 +26,7 @@
// input port: send address one cycle before the data
// clear_i clears the FIFO for the following cycle. in_addr_i can be sent in
// this cycle already
module riscv_fetch_fifo
module littleriscv_fetch_fifo
(
input logic clk,
input logic rst_n,
@ -232,7 +232,7 @@ module riscv_fetch_fifo
endmodule
module riscv_prefetch_buffer
module littleriscv_prefetch_buffer
(
input logic clk,
input logic rst_n,
@ -283,7 +283,7 @@ module riscv_prefetch_buffer
// consumes addresses and rdata
//////////////////////////////////////////////////////////////////////////////
riscv_fetch_fifo fifo_i
littleriscv_fetch_fifo fifo_i
(
.clk ( clk ),
.rst_n ( rst_n ),

2
prefetch_buffer_only_aligned.sv
View file

@ -24,7 +24,7 @@
`include "riscv_config.sv"
module riscv_prefetch_buffer_only_aligned
module littleriscv_prefetch_buffer_only_aligned
(
input logic clk,
input logic rst_n,

2
prefetch_buffer_small.sv
View file

@ -24,7 +24,7 @@
`include "riscv_config.sv"
module riscv_prefetch_buffer_small
module littleriscv_prefetch_buffer_small
(
input logic clk,
input logic rst_n,

2
register_file.sv
View file

@ -27,7 +27,7 @@
`include "riscv_config.sv"
module riscv_register_file
module littleriscv_register_file
#(
parameter ADDR_WIDTH = 5,
parameter DATA_WIDTH = 32

2
register_file_ff.sv
View file

@ -25,7 +25,7 @@
`include "riscv_config.sv"
module riscv_register_file
module littleriscv_register_file
#(
parameter ADDR_WIDTH = 5,
parameter DATA_WIDTH = 32

2
riscv_simchecker.sv
View file

@ -35,7 +35,7 @@ import "DPI-C" function void riscv_checker_mem_access(input chandle cpu, inpu
import "DPI-C" function void riscv_checker_reg_access(input chandle cpu, input logic [31:0] addr, input logic [31:0] data);
`endif
module riscv_simchecker
module littleriscv_simchecker
#(
parameter REG_ADDR_WIDTH = 5
)

2
riscv_tracer.sv
View file

@ -34,7 +34,7 @@ import riscv_tracer_defines::*;
`define REG_D 11:07
module riscv_tracer
module littleriscv_tracer
#(
parameter REG_ADDR_WIDTH = 5
)

12
src_files.yml
View file

@ -1,4 +1,4 @@
riscv:
littleriscv:
incdirs: [
include,
]
@ -26,9 +26,9 @@ riscv:
prefetch_buffer_small.sv,
prefetch_buffer_only_aligned.sv,
prefetch_L0_buffer.sv,
riscv_core.sv,
littleriscv_core.sv,
]
riscv_vip_rtl:
littleriscv_vip_rtl:
targets: [
rtl,
]
@ -36,10 +36,12 @@ riscv_vip_rtl:
include,
]
files: [
include/riscv_defines.sv,
include/riscv_tracer_defines.sv,
riscv_tracer.sv,
riscv_simchecker.sv,
]
riscv_regfile_rtl:
littleriscv_regfile_rtl:
targets: [
rtl,
]
@ -49,7 +51,7 @@ riscv_regfile_rtl:
files: [
register_file.sv,
]
riscv_regfile_fpga:
littleriscv_regfile_fpga:
targets: [
xilinx,
]