github-mirrors/ibex
1
0
Fork 0
mirror of https://github.com/lowRISC/ibex.git synced 2025-04-20 11:57:12 -04:00
Code Issues Projects Releases Packages Wiki Activity Actions

parameters for RV32E and RV32M

Browse source
This commit is contained in:
Pasquale Davide Schiavone 2017-03-17 19:10:00 +01:00
parent 7ec2d7b41f
commit 311805d955
6 changed files with 61 additions and 37 deletions
Download patch file Download diff file Expand all files Collapse all files

15
decoder.sv
View file

@ -31,6 +31,9 @@
import zeroriscy_defines::*;
module zeroriscy_decoder
#(
parameter RV32M = 1
)
(
// singals running to/from controller
input logic deassert_we_i, // deassert we, we are stalled or not active
@ -406,48 +409,56 @@ module zeroriscy_decoder
multdiv_operator_o = MD_OP_MULL;
mult_int_en = 1'b1;
multdiv_signed_mode_o = 2'b00;
illegal_insn_o = RV32M ? 1'b0 : 1'b1;
end
{6'b00_0001, 3'b001}: begin // mulh
alu_operator_o = ALU_ADD;
multdiv_operator_o = MD_OP_MULH;
mult_int_en = 1'b1;
multdiv_signed_mode_o = 2'b11;
illegal_insn_o = RV32M ? 1'b0 : 1'b1;
end
{6'b00_0001, 3'b010}: begin // mulhsu
alu_operator_o = ALU_ADD;
multdiv_operator_o = MD_OP_MULH;
mult_int_en = 1'b1;
multdiv_signed_mode_o = 2'b01;
illegal_insn_o = RV32M ? 1'b0 : 1'b1;
end
{6'b00_0001, 3'b011}: begin // mulhu
alu_operator_o = ALU_ADD;
multdiv_operator_o = MD_OP_MULH;
mult_int_en = 1'b1;
multdiv_signed_mode_o = 2'b00;
illegal_insn_o = RV32M ? 1'b0 : 1'b1;
end
{6'b00_0001, 3'b100}: begin // div
alu_operator_o = ALU_ADD;
multdiv_operator_o = MD_OP_DIV;
div_int_en = 1'b1;
multdiv_signed_mode_o = 2'b11;
illegal_insn_o = RV32M ? 1'b0 : 1'b1;
end
{6'b00_0001, 3'b101}: begin // divu
alu_operator_o = ALU_ADD;
multdiv_operator_o = MD_OP_DIV;
div_int_en = 1'b1;
multdiv_signed_mode_o = 2'b00;
illegal_insn_o = RV32M ? 1'b0 : 1'b1;
end
{6'b00_0001, 3'b110}: begin // rem
alu_operator_o = ALU_ADD;
multdiv_operator_o = MD_OP_REM;
div_int_en = 1'b1;
multdiv_signed_mode_o = 2'b11;
illegal_insn_o = RV32M ? 1'b0 : 1'b1;
end
{6'b00_0001, 3'b111}: begin // remu
alu_operator_o = ALU_ADD;
multdiv_operator_o = MD_OP_REM;
div_int_en = 1'b1;
multdiv_signed_mode_o = 2'b00;
illegal_insn_o = RV32M ? 1'b0 : 1'b1;
end
default: begin
illegal_insn_o = 1'b1;
@ -562,8 +573,8 @@ module zeroriscy_decoder
// deassert we signals (in case of stalls)
assign regfile_we_o = (deassert_we_i) ? 1'b0 : regfile_we;
assign mult_int_en_o = (deassert_we_i) ? 1'b0 : mult_int_en;
assign div_int_en_o = (deassert_we_i) ? 1'b0 : div_int_en;
assign mult_int_en_o = RV32M ? ((deassert_we_i) ? 1'b0 : mult_int_en) : 1'b0;
assign div_int_en_o = RV32M ? ((deassert_we_i) ? 1'b0 : div_int_en ) : 1'b0;
assign data_req_o = (deassert_we_i) ? 1'b0 : data_req;
assign csr_op_o = (deassert_we_i) ? CSR_OP_NONE : csr_op;
assign jump_in_id_o = (deassert_we_i) ? 1'b0 : jump_in_id;

18
ex_stage.sv
View file

@ -33,6 +33,9 @@
import zeroriscy_defines::*;
module zeroriscy_ex_block
#(
parameter RV32M = 1
)
(
input logic clk,
@ -65,7 +68,7 @@ module zeroriscy_ex_block
output logic ex_ready_o // EX stage gets new data
);
localparam MULT_TYPE = 0; //0 is SLOW
localparam MULT_TYPE = 1; //0 is SLOW
logic [31:0] alu_result, multdiv_result;
@ -75,9 +78,20 @@ module zeroriscy_ex_block
logic multdiv_ready, multdiv_en_sel;
logic multdiv_en;
assign multdiv_en_sel = MULT_TYPE == 0 ? mult_en_i | div_en_i : div_en_i;
/*
The multdiv_i output is never selected if RV32M=0
At synthesis time, all the combinational and sequential logic
from the multdiv_i module are eliminated
*/
if (RV32M) begin
assign multdiv_en_sel = MULT_TYPE == 0 ? mult_en_i | div_en_i : div_en_i;
assign multdiv_en = mult_en_i | div_en_i;
end else begin
assign multdiv_en_sel = 1'b0;
assign multdiv_en = 1'b0;
end
assign regfile_wdata_ex_o = multdiv_en ? multdiv_result : alu_result;
// branch handling

24
id_stage.sv
View file

@ -39,6 +39,7 @@ import zeroriscy_defines::*;
module zeroriscy_id_stage
#(
parameter RV32M = 1,
parameter RV32E = 0
)
(
@ -286,9 +287,9 @@ module zeroriscy_id_stage
//---------------------------------------------------------------------------
assign regfile_alu_waddr_id = instr[`REG_D];
if(RV32E)
assign illegal_reg_rv32e = (regfile_addr_ra_id[4] | regfile_addr_rb_id[4] | regfile_alu_waddr_id[4]);
else
//if(RV32E)
// assign illegal_reg_rv32e = (regfile_addr_ra_id[4] | regfile_addr_rb_id[4] | regfile_alu_waddr_id[4]);
//else
assign illegal_reg_rv32e = 1'b0;
// kill instruction in the IF/ID stage by setting the instr_valid_id control
@ -297,9 +298,6 @@ else
assign branch_taken_ex = branch_in_id & branch_decision_i;
////////////////////////////////////////////////////////
// ___ _ _ //
// / _ \ _ __ ___ _ __ __ _ _ __ __| | / \ //
@ -450,7 +448,11 @@ else
// //
///////////////////////////////////////////////
zeroriscy_decoder decoder_i
zeroriscy_decoder
#(
.RV32M(RV32M)
)
decoder_i
(
// controller related signals
.deassert_we_i ( deassert_we ),
@ -629,7 +631,7 @@ else
/////////////////////////////////////
// ___ ____ _______ __ //
// |_ _| _ \ | ____\ \/ / //
// | || | | |_____| _| \ / // - merging network
// | || | | |_____| _| \ / //
// | || |_| |_____| |___ / \ //
// |___|____/ |_____/_/\_\ //
// //
@ -784,5 +786,9 @@ else
// make sure multicycles enable signals are unique
assert property (
@(posedge clk) ~(data_req_ex_o & multdiv_int_en )) else $display("Multicycles enable signals are not unique");
/*
// make sure no reg x16...x31 are accessed if RV32E is active
assert property (
@(posedge clk) ~(illegal_reg_rv32e)) else $display("Access to x16....x31 registers at time %t", $time);
*/
endmodule

6
if_stage.sv
View file

@ -29,9 +29,7 @@
import zeroriscy_defines::*;
module zeroriscy_if_stage #(
parameter RDATA_WIDTH = 32
)
module zeroriscy_if_stage
(
input logic clk,
input logic rst_n,
@ -44,7 +42,7 @@ module zeroriscy_if_stage #(
output logic [31:0] instr_addr_o,
input logic instr_gnt_i,
input logic instr_rvalid_i,
input logic [RDATA_WIDTH-1:0] instr_rdata_i,
input logic [31:0] instr_rdata_i,
// Output of IF Pipeline stage
output logic instr_valid_id_o, // instruction in IF/ID pipeline is valid
output logic [31:0] instr_rdata_id_o, // read instruction is sampled and sent to ID stage for decoding

5
register_file.sv
View file

@ -164,10 +164,5 @@ module zeroriscy_register_file
end
end
if(RV32E) begin
// make sure no reg x16...x31 are accessed
assert property (
@(posedge clk) ~(raddr_a_i[4] | raddr_b_i[4] | waddr_a_int[4])) else $display("Access to x16....x31 registers!");
end
endmodule

30
zeroriscy_core.sv
View file

@ -33,8 +33,8 @@ import zeroriscy_defines::*;
module zeroriscy_core
#(
parameter N_EXT_PERF_COUNTERS = 0,
parameter INSTR_RDATA_WIDTH = 32,
parameter RV32E = 0
parameter RV32E = 0,
parameter RV32M = 1
)
(
// Clock and Reset
@ -54,7 +54,7 @@ module zeroriscy_core
input logic instr_gnt_i,
input logic instr_rvalid_i,
output logic [31:0] instr_addr_o,
input logic [INSTR_RDATA_WIDTH-1:0] instr_rdata_i,
input logic [31:0] instr_rdata_i,
// Data memory interface
output logic data_req_o,
@ -154,7 +154,7 @@ module zeroriscy_core
logic [31:0] csr_rdata;
logic [31:0] csr_wdata;
// Data Memory Control: From ID stage (id-ex pipe) <--> load store unit
// Data Memory Control
logic data_we_ex;
logic [1:0] data_type_ex;
logic data_sign_ext_ex;
@ -193,9 +193,6 @@ module zeroriscy_core
logic exc_save_takenbranch_ex;
logic exc_restore_id;
// Debug Unit
logic [DBG_SETS_W-1:0] dbg_settings;
logic dbg_req;
@ -275,11 +272,7 @@ module zeroriscy_core
// |___|_| |____/ |_/_/ \_\____|_____| //
// //
//////////////////////////////////////////////////
zeroriscy_if_stage
#(
.RDATA_WIDTH ( INSTR_RDATA_WIDTH )
)
if_stage_i
zeroriscy_if_stage if_stage_i
(
.clk ( clk ),
.rst_n ( rst_ni ),
@ -341,7 +334,8 @@ module zeroriscy_core
/////////////////////////////////////////////////
zeroriscy_id_stage
#(
.RV32E(RV32E)
.RV32E(RV32E),
.RV32M(RV32M)
)
id_stage_i
(
@ -456,7 +450,13 @@ module zeroriscy_core
);
zeroriscy_ex_block ex_block_i
zeroriscy_ex_block
#(
//change the localparam MULT_TYPE to 0 or 1
//if you want a SLOW or FAST multiplier
.RV32M(RV32M)
)
ex_block_i
(
.clk ( clk ),
.rst_n ( rst_ni ),
@ -517,7 +517,7 @@ module zeroriscy_core
.data_type_ex_i ( data_type_ex ),
.data_wdata_ex_i ( data_wdata_ex ),
.data_reg_offset_ex_i ( data_reg_offset_ex ),
.data_sign_ext_ex_i ( data_sign_ext_ex ), // sign extension
.data_sign_ext_ex_i ( data_sign_ext_ex ),
.data_rdata_ex_o ( regfile_wdata_lsu ),
.data_req_ex_i ( data_req_ex ),