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Document mtvec as WARL rather than read-only

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mtvec is hard-wired, but isn't read-only as writes don't cause an
exception.
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Alex Bradbury 2019-07-10 06:39:20 +01:00 • committed by Alex Bradbury
parent ce042bd350
commit 33b7904a12
1 changed files with 3 additions and 2 deletions
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5
doc/cs_registers.rst
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@ -12,7 +12,7 @@ Ibex implements all the Control and Status Registers (CSRs) listed in the follow
+---------+--------------------+--------+-----------------------------------------------+
| 0x301 | ``misa`` | WARL | Machine ISA and Extensions |
+---------+--------------------+--------+-----------------------------------------------+
| 0x305 | ``mtvec`` | R | Machine Trap-Vector Base Address |
| 0x305 | ``mtvec`` | WARL | Machine Trap-Vector Base Address |
+---------+--------------------+--------+-----------------------------------------------+
| 0x320 | ``mcountinhibit`` | RW | Machine Counter-Inhibit Register |
+---------+--------------------+--------+-----------------------------------------------+
@ -100,7 +100,8 @@ Machine Trap-Vector Base Address (mtvec)
CSR Address: ``0x305``
When an exception is encountered, the core jumps to the corresponding handler using the content of ``mtvec`` as base address.
It is a read-only register which contains the boot address.
It is a WARL register which contains the boot address.
It contains a hard-wired value, so will remain unchanged after any writes.
``mtvec``.MODE is set to 2'b01 to indicate vectored interrupt handling.