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https://github.com/lowRISC/ibex.git
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Added support for pv.insert, pv.extract and pv.extractu
All untested so far
This commit is contained in:
Andreas Traber
parent
09d6de8e42
commit
3b127ca326
6 changed files with 82 additions and 21 deletions
68
alu.sv
68
alu.sv
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@ -35,6 +35,7 @@ module riscv_alu
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input logic [ 1:0] vector_mode_i,
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input logic [ 4:0] imm_bmask_a_i,
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input logic [ 4:0] imm_bmask_b_i,
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input logic [ 1:0] imm_vec_ext_i,
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output logic [31:0] result_o,
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output logic comparison_result_o
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@ -379,21 +380,21 @@ module riscv_alu
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begin
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sel_minmax[3:0] = is_greater ^ {4{do_min}};
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// if(operator_i == `ALU_INS)
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// begin
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// if(vector_mode_i == `VEC_MODE16)
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// begin
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// sel_minmax[1:0] = {2{vec_ext_i[0]}};
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// sel_minmax[3:2] = ~{2{vec_ext_i[0]}};
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// end
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// else // `VEC_MODE8
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// begin
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// sel_minmax[0] = (vec_ext_i != 2'b00);
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// sel_minmax[1] = (vec_ext_i != 2'b01);
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// sel_minmax[2] = (vec_ext_i != 2'b10);
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// sel_minmax[3] = (vec_ext_i != 2'b11);
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// end
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// end
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if(operator_i == `ALU_INS)
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begin
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if(vector_mode_i == `VEC_MODE16)
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begin
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sel_minmax[1:0] = {2{imm_vec_ext_i[0]}};
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sel_minmax[3:2] = ~{2{imm_vec_ext_i[0]}};
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end
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else // `VEC_MODE8
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begin
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sel_minmax[0] = (imm_vec_ext_i != 2'b00);
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sel_minmax[1] = (imm_vec_ext_i != 2'b01);
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sel_minmax[2] = (imm_vec_ext_i != 2'b10);
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sel_minmax[3] = (imm_vec_ext_i != 2'b11);
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end
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end
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end
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assign result_minmax[31:24] = (sel_minmax[3] == 1'b1) ? operand_a_i[31:24] : minmax_b[31:24];
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@ -413,23 +414,47 @@ module riscv_alu
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//////////////////////////////////////////////////
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logic [31:0] result_ext;
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logic [15:0] ext_half;
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always_comb
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begin
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case (vector_mode_i)
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`VEC_MODE16: begin
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if (imm_vec_ext_i[0])
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ext_half[15:0] = operand_a_i[31:16];
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else
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ext_half[15:0] = operand_a_i[15: 0];
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end
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`VEC_MODE8: begin
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case (imm_vec_ext_i[1:0])
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2'b11: ext_half[7:0] = operand_a_i[31:24];
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2'b10: ext_half[7:0] = operand_a_i[23:16];
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2'b01: ext_half[7:0] = operand_a_i[15: 8];
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2'b00: ext_half[7:0] = operand_a_i[ 7: 0];
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endcase
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end
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default: ext_half[15:0] = operand_a_i[15:0];
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endcase
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end
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always_comb
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begin
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// zero extend byte
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result_ext = {24'b0, operand_a_i[7:0]};
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result_ext = {24'b0, ext_half[7:0]};
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// sign extend byte
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if (operator_i == `ALU_EXTBS)
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result_ext = {{24 {operand_a_i[7]}}, operand_a_i[7:0]};
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result_ext = {{24 {operand_a_i[7]}}, ext_half[7:0]};
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// zero extend half word
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if(operator_i == `ALU_EXTHZ)
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result_ext = {16'b0, operand_a_i[15:0]};
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result_ext = {16'b0, ext_half[15:0]};
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// sign extend half word
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if(operator_i == `ALU_EXTHS)
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result_ext = {{16 {operand_a_i[15]}}, operand_a_i[15:0]};
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result_ext = {{16 {operand_a_i[15]}}, ext_half[15:0]};
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end
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@ -581,10 +606,11 @@ module riscv_alu
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`ALU_EXTHZ,
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`ALU_EXTHS: result_o = result_ext;
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// Min/Max/Abs
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// Min/Max/Abs/Ins
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`ALU_MIN, `ALU_MINU,
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`ALU_MAX, `ALU_MAXU,
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`ALU_ABS: result_o = result_minmax;
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`ALU_ABS,
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`ALU_INS: result_o = result_minmax;
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// Comparison Operations
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`ALU_EQ, `ALU_NE, `ALU_GTU, `ALU_GEU, `ALU_LTU, `ALU_LEU, `ALU_GTS, `ALU_GES, `ALU_LTS, `ALU_LES:
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21
decoder.sv
21
decoder.sv
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@ -574,6 +574,27 @@ module riscv_decoder
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6'b01101_0: begin alu_operator_o = `ALU_AND; immediate_mux_sel_o = `IMM_VS; end // pv.and
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6'b01110_0: begin alu_operator_o = `ALU_ABS; immediate_mux_sel_o = `IMM_VS; end // pv.abs
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6'b01111_0: begin // pv.extract
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if (instr_rdata_i[12])
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alu_operator_o = `ALU_EXTBS;
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else
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alu_operator_o = `ALU_EXTHS;
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end
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6'b10000_0: begin // pv.extractu
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if (instr_rdata_i[12])
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alu_operator_o = `ALU_EXTBZ;
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else
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alu_operator_o = `ALU_EXTHZ;
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end
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6'b10001_0: begin // pv.insert
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alu_operator_o = `ALU_INS;
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regc_used_o = 1'b1;
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regc_mux_o = `REGC_RD;
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alu_op_b_mux_sel_o = `OP_B_REGC_OR_FWD;
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end
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// comparisons, always have bit 26 set
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6'b00000_1: begin alu_operator_o = `ALU_EQ; immediate_mux_sel_o = `IMM_VS; end // pv.cmpeq
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6'b00001_1: begin alu_operator_o = `ALU_NE; immediate_mux_sel_o = `IMM_VS; end // pv.cmpne
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@ -41,6 +41,7 @@ module riscv_ex_stage
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input logic [31:0] alu_operand_c_i,
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input logic [ 4:0] imm_bmask_a_i,
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input logic [ 4:0] imm_bmask_b_i,
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input logic [ 1:0] imm_vec_ext_i,
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input logic [ 1:0] alu_vec_mode_i,
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// Multiplier signals
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@ -128,6 +129,7 @@ module riscv_ex_stage
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.vector_mode_i ( alu_vec_mode_i ),
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.imm_bmask_a_i ( imm_bmask_a_i ),
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.imm_bmask_b_i ( imm_bmask_b_i ),
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.imm_vec_ext_i ( imm_vec_ext_i ),
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.result_o ( alu_result ),
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.comparison_result_o ( alu_cmp_result )
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@ -89,6 +89,7 @@ module riscv_id_stage
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output logic [31:0] alu_operand_c_ex_o,
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output logic [ 4:0] imm_bmask_a_ex_o,
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output logic [ 4:0] imm_bmask_b_ex_o,
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output logic [ 1:0] imm_vec_ext_ex_o,
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output logic [ 1:0] alu_vec_mode_ex_o,
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output logic [4:0] regfile_waddr_ex_o,
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@ -306,6 +307,7 @@ module riscv_id_stage
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// Immediates for ID
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logic [ 4:0] imm_bmask_a_id;
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logic [ 4:0] imm_bmask_b_id;
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logic [ 1:0] imm_vec_ext_id;
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logic [ 1:0] alu_vec_mode;
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logic scalar_replication;
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@ -594,6 +596,7 @@ module riscv_id_stage
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assign imm_bmask_b_id = ((alu_operator == `ALU_BCLR) || (alu_operator == `ALU_BSET) || (alu_operator == `ALU_BINS)) ?
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imm_s2_type[4:0] : 0;
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assign imm_vec_ext_id = imm_vu_type[1:0];
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/////////////////////////////////////////////////////////
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// ____ _____ ____ ___ ____ _____ _____ ____ ____ //
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@ -936,6 +939,7 @@ module riscv_id_stage
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alu_operand_c_ex_o <= '0;
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imm_bmask_a_ex_o <= '0;
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imm_bmask_b_ex_o <= '0;
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imm_vec_ext_ex_o <= '0;
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alu_vec_mode_ex_o <= '0;
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mult_operand_a_ex_o <= '0;
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@ -1001,6 +1005,7 @@ module riscv_id_stage
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alu_operand_c_ex_o <= alu_operand_c;
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imm_bmask_a_ex_o <= imm_bmask_a_id;
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imm_bmask_b_ex_o <= imm_bmask_b_id;
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imm_vec_ext_ex_o <= imm_vec_ext_id;
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alu_vec_mode_ex_o <= alu_vec_mode;
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end
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@ -145,11 +145,15 @@
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// Absolute value
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`define ALU_ABS 6'b010100
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// Insert/extract
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`define ALU_INS 6'b101101
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// min/max
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`define ALU_MIN 6'b010000
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`define ALU_MINU 6'b010001
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`define ALU_MAX 6'b010010
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`define ALU_MAXU 6'b010011
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`define ALU_MAXU 6'b010011
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// vector modes
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@ -129,6 +129,7 @@ module riscv_core
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logic [31:0] alu_operand_c_ex;
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logic [ 4:0] imm_bmask_a_ex;
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logic [ 4:0] imm_bmask_b_ex;
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logic [ 1:0] imm_vec_ext_ex;
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logic [ 1:0] alu_vec_mode_ex;
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// Multiplier Control
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@ -383,6 +384,7 @@ module riscv_core
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.alu_operand_c_ex_o ( alu_operand_c_ex ),
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.imm_bmask_a_ex_o ( imm_bmask_a_ex ),
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.imm_bmask_b_ex_o ( imm_bmask_b_ex ),
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.imm_vec_ext_ex_o ( imm_vec_ext_ex ),
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.alu_vec_mode_ex_o ( alu_vec_mode_ex ),
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.regfile_waddr_ex_o ( regfile_waddr_ex ),
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@ -486,6 +488,7 @@ module riscv_core
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.alu_operand_c_i ( alu_operand_c_ex ), // from ID/EX pipe registers
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.imm_bmask_a_i ( imm_bmask_a_ex ), // from ID/EX pipe registers
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.imm_bmask_b_i ( imm_bmask_b_ex ), // from ID/EX pipe registers
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.imm_vec_ext_i ( imm_vec_ext_ex ), // from ID/EX pipe registers
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.alu_vec_mode_i ( alu_vec_mode_ex ), // from ID/EX pipe registers
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// Multipler
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