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[rtl] Use gated clock for wb_stage and rf
Corrects a typo, ibex_wb_stage and ibex_register_file were being supplied with the ungated clk.
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1 changed files with 2 additions and 2 deletions
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@ -705,7 +705,7 @@ module ibex_core #(
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ibex_wb_stage #(
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ibex_wb_stage #(
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.WritebackStage ( WritebackStage )
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.WritebackStage ( WritebackStage )
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) wb_stage_i (
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) wb_stage_i (
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.clk_i ( clk_i ),
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.clk_i ( clk ),
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.rst_ni ( rst_ni ),
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.rst_ni ( rst_ni ),
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.en_wb_i ( en_wb ),
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.en_wb_i ( en_wb ),
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.instr_type_wb_i ( instr_type_wb ),
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.instr_type_wb_i ( instr_type_wb ),
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@ -740,7 +740,7 @@ module ibex_core #(
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.DataWidth (32),
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.DataWidth (32),
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.DummyInstructions (DummyInstructions)
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.DummyInstructions (DummyInstructions)
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) register_file_i (
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) register_file_i (
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.clk_i ( clk_i ),
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.clk_i ( clk ),
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.rst_ni ( rst_ni ),
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.rst_ni ( rst_ni ),
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.test_en_i ( test_en_i ),
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.test_en_i ( test_en_i ),
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