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[rtl] Use gated clock for wb_stage and rf

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Corrects a typo, ibex_wb_stage and ibex_register_file were being
supplied with the ungated clk.
This commit is contained in:
Greg Chadwick 2020-06-12 10:33:05 +01:00
parent 207cac3ced
commit 3c55a72d08
1 changed files with 2 additions and 2 deletions
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4
rtl/ibex_core.sv
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@ -705,7 +705,7 @@ module ibex_core #(
ibex_wb_stage #(
.WritebackStage ( WritebackStage )
) wb_stage_i (
.clk_i ( clk_i ),
.clk_i ( clk ),
.rst_ni ( rst_ni ),
.en_wb_i ( en_wb ),
.instr_type_wb_i ( instr_type_wb ),
@ -740,7 +740,7 @@ module ibex_core #(
.DataWidth (32),
.DummyInstructions (DummyInstructions)
) register_file_i (
.clk_i ( clk_i ),
.clk_i ( clk ),
.rst_ni ( rst_ni ),
.test_en_i ( test_en_i ),