github-mirrors/ibex
1
0
Fork 0
mirror of https://github.com/lowRISC/ibex.git synced 2025-04-22 21:07:34 -04:00
Code Issues Projects Releases Packages Wiki Activity Actions

Prevent illegal instructions from propagating out of decoder

Browse source 
This commit makes sure that if any instruction is detected as being
illegal inside the decoder, the decoder does not set the control
signals to let the illegal instruction affect the register file,
LSU, EX, WB, CSRs. Previously, this was only the case for some but
but not all instructions.

Note that this is not sufficient to prevent instructions detected
as illegal elsewhere from affecting the processor state. For example,
when using RV32E, an instruction can be detected to use unavailable
registers outside the decoder in the ID stage. But it is cleaner to
handle all illegal instructions detected in the decoder similarly.
This commit is contained in:
Pirmin Vogel 2019-07-01 17:40:32 +01:00
parent d973618ce8
commit 3eb147dbc2
1 changed files with 17 additions and 7 deletions
Download patch file Download diff file Expand all files Collapse all files

24
rtl/ibex_decoder.sv
View file

@ -171,8 +171,6 @@ module ibex_decoder #(
regfile_we_o = 1'b1;
end
if (instr_rdata_i[14:12] != 3'b0) begin
jump_in_dec_o = 1'b0;
regfile_we_o = 1'b0;
illegal_insn_o = 1'b1;
end
end
@ -214,8 +212,6 @@ module ibex_decoder #(
alu_op_b_mux_sel_o = OP_B_IMM;
end else begin
// Register offset is illegal since no register c available
data_req_o = 1'b0;
data_we_o = 1'b0;
illegal_insn_o = 1'b1;
end
@ -225,8 +221,6 @@ module ibex_decoder #(
2'b01: data_type_o = 2'b01; // SH
2'b10: data_type_o = 2'b00; // SW
default: begin
data_req_o = 1'b0;
data_we_o = 1'b0;
illegal_insn_o = 1'b1;
end
endcase
@ -506,10 +500,26 @@ module ibex_decoder #(
end
endcase
// make sure invalid compressed instruction causes an exception
// make sure illegal compressed instructions cause illegal instruction exceptions
if (illegal_c_insn_i) begin
illegal_insn_o = 1'b1;
end
// make sure illegal instructions detected in the decoder do not propagate from decoder
// into register file, LSU, EX, WB, CSRs
// NOTE: instructions can also be detected to be illegal inside the CSRs (upon accesses with
// insufficient privileges), in ID stage (when accessing Reg 16 or higher in RV32E config),
// these cases are not handled here
if (illegal_insn_o) begin
regfile_we_o = 1'b0;
data_req_o = 1'b0;
data_we_o = 1'b0;
mult_en_o = 1'b0;
div_en_o = 1'b0;
jump_in_dec_o = 1'b0;
branch_in_dec_o = 1'b0;
csr_access_o = 1'b0;
end
end
endmodule // controller