[rtl] Comment and naming tweaks

doc/pipeline_details.rst

@@ -77,7 +77,7 @@ Read the description for more information.
 |                       |                       | ``BranchTargetALU`` set to ``1`` a seperate ALU calculates  |
 |                       |                       | the branch target simultaneously to calculating the branch  |
 |                       |                       | condition with the main ALU so 1 less stall cycle is        |
-|                       |                       | required                                                    |
+|                       |                       | required.                                                   |
 +-----------------------+-----------------------+-------------------------------------------------------------+
 | Instruction Fence     | 1 - N                 | The FENCE.I instruction as defined in 'Zifencei' of the     |
 |                       |                       | RISC-V specification. Internally it is implemented as a     |

rtl/ibex_decoder.sv

@@ -567,7 +567,7 @@ module ibex_decoder #(
       ///////////
 
       OPCODE_JAL: begin // Jump and Link
-        if(BranchTargetALU) begin
+        if (BranchTargetALU) begin
           jt_mux_sel_o = JT_ALU;
         end
 
@@ -587,7 +587,7 @@ module ibex_decoder #(
       end
 
       OPCODE_JALR: begin // Jump and Link Register
-        if(BranchTargetALU) begin
+        if (BranchTargetALU) begin
           jt_mux_sel_o = JT_ALU;
         end
 
@@ -619,15 +619,16 @@ module ibex_decoder #(
         endcase
 
         if (BranchTargetALU) begin
-          // With branch target ALU main ALU evaluates branch condition and branch target ALU
-          // calculates target (which is controlled in a seperate block below)
+          // With branch target ALU the main ALU evaluates the branch condition and the branch
+          // target ALU calculates the target (which is controlled in a seperate block below)
           alu_op_a_mux_sel_o  = OP_A_REG_A;
           alu_op_b_mux_sel_o  = OP_B_REG_B;
           jt_mux_sel_o        = JT_BT_ALU;
         end else begin
-          // Without branch target ALU branch is 2 stage operation using the Main ALU in both stages
+          // Without branch target ALU, a branch is a two-stage operation using the Main ALU in both
+          // stages
           if (instr_new_i) begin
-            // First evaluates branch condition
+            // First evaluate the branch condition
             alu_op_a_mux_sel_o  = OP_A_REG_A;
             alu_op_b_mux_sel_o  = OP_B_REG_B;
           end else begin

rtl/ibex_ex_block.sv

@@ -79,13 +79,13 @@ module ibex_ex_block #(
     assign jump_target_o = (jt_mux_sel_i == JT_ALU) ? alu_adder_result_ex_o : bt_alu_result[31:0];
   end else begin : g_no_branch_target_alu
     // Unused jt_mux_sel_i/bt_operand_imm_i/pc_id_i signals causes lint errors, this avoids them
-    ibex_pkg::jt_mux_sel_e jt_mux_sel_unused;
-    logic [11:0]           bt_operand_imm_unused;
-    logic [31:0]           pc_id_unused;
+    ibex_pkg::jt_mux_sel_e unused_jt_mux_sel;
+    logic [11:0]           unused_bt_operand_imm;
+    logic [31:0]           unused_pc_id;
 
-    assign jt_mux_sel_unused     = jt_mux_sel_i;
-    assign bt_operand_imm_unused = bt_operand_imm_i;
-    assign pc_id_unused          = pc_id_i;
+    assign unused_jt_mux_sel     = jt_mux_sel_i;
+    assign unused_bt_operand_imm = bt_operand_imm_i;
+    assign unused_pc_id          = pc_id_i;
 
     assign jump_target_o = alu_adder_result_ex_o;
   end

rtl/ibex_id_stage.sv

@@ -156,7 +156,7 @@ module ibex_id_stage #(
   logic        wfi_insn_dec;
 
   logic        branch_in_dec;
-  logic        branch_set, branch_set_n;
+  logic        branch_set, branch_set_d;
   logic        jump_in_dec;
   logic        jump_set;
 
@@ -545,7 +545,7 @@ module ibex_id_stage #(
   if (BranchTargetALU) begin : g_branch_set_direct
     // Branch set fed straight to controller with branch target ALU
     // (condition pass/fail used same cycle as generated instruction request)
-    assign branch_set = branch_set_n;
+    assign branch_set = branch_set_d;
   end else begin : g_branch_set_flopped
     // Branch set flopped without branch target ALU
     // (condition pass/fail used next cycle where branch target is calculated)
@@ -555,7 +555,7 @@ module ibex_id_stage #(
       if (!rst_ni) begin
         branch_set_q <= 1'b0;
       end else begin
-        branch_set_q <= branch_set_n;
+        branch_set_q <= branch_set_d;
       end
     end
 
@@ -584,7 +584,7 @@ module ibex_id_stage #(
     stall_multdiv           = 1'b0;
     stall_jump              = 1'b0;
     stall_branch            = 1'b0;
-    branch_set_n            = 1'b0;
+    branch_set_d            = 1'b0;
     perf_branch_o           = 1'b0;
     instr_ret_o             = 1'b0;
 
@@ -612,7 +612,7 @@ module ibex_id_stage #(
               id_wb_fsm_ns            =  branch_decision_i ? WAIT_MULTICYCLE : IDLE;
               stall_branch            =  branch_decision_i;
               instr_multicycle_done_n = ~branch_decision_i;
-              branch_set_n            =  branch_decision_i;
+              branch_set_d            =  branch_decision_i;
               perf_branch_o           =  1'b1;
               instr_ret_o             = ~branch_decision_i;
             end