Rename ibex_[tracer_]define to ibex_[tracer_]pkg

This file doesn't contain defines any more, but a normal SV package.

The diff is best viewed without whitespace changes, as the reindents
cause a lof of diff noise.

Fixes lowrisc/ibex#173

ibex_core.core

@@ -7,7 +7,7 @@ description: "CPU core with 2 stage pipeline implementing the RV32IMC_Zicsr ISA"
 filesets:
   files_rtl:
     files:
-      - rtl/ibex_defines.sv
+      - rtl/ibex_pkg.sv
       - rtl/ibex_alu.sv
       - rtl/ibex_compressed_decoder.sv
       - rtl/ibex_controller.sv

ibex_tracer.core

@@ -9,7 +9,7 @@ filesets:
     depend:
       - lowrisc:ibex:ibex
     files:
-      - rtl/ibex_tracer_defines.sv
+      - rtl/ibex_tracer_pkg.sv
       - rtl/ibex_tracer.sv
       - rtl/ibex_core_tracer.sv
     file_type: systemVerilogSource

rtl/ibex_alu.sv

@@ -22,7 +22,7 @@
  * Arithmetic logic unit
  */
 module ibex_alu (
-    input  ibex_defines::alu_op_e operator_i,
+    input  ibex_pkg::alu_op_e operator_i,
     input  logic [31:0]       operand_a_i,
     input  logic [31:0]       operand_b_i,
 
@@ -38,7 +38,7 @@ module ibex_alu (
     output logic              comparison_result_o,
     output logic              is_equal_result_o
 );
-  import ibex_defines::*;
+  import ibex_pkg::*;
 
   logic [31:0] operand_a_rev;
   logic [32:0] operand_b_neg;

rtl/ibex_compressed_decoder.sv

@@ -28,7 +28,7 @@ module ibex_compressed_decoder (
     output logic        is_compressed_o,
     output logic        illegal_instr_o
 );
-  import ibex_defines::*;
+  import ibex_pkg::*;
 
   ////////////////////////
   // Compressed decoder //

rtl/ibex_controller.sv

@@ -53,9 +53,9 @@ module ibex_controller (
     // to prefetcher
     output logic                  instr_req_o,           // start fetching instructions
     output logic                  pc_set_o,              // jump to address set by pc_mux
-    output ibex_defines::pc_sel_e     pc_mux_o,              // IF stage fetch address selector
+    output ibex_pkg::pc_sel_e     pc_mux_o,              // IF stage fetch address selector
                                                          // (boot, normal, exception...)
-    output ibex_defines::exc_pc_sel_e exc_pc_mux_o,          // IF stage selector for exception PC
+    output ibex_pkg::exc_pc_sel_e exc_pc_mux_o,          // IF stage selector for exception PC
 
     // LSU
     input  logic [31:0]           lsu_addr_last_i,       // for mtval
@@ -77,13 +77,13 @@ module ibex_controller (
     output logic                  irq_ack_o,
     output logic [4:0]            irq_id_o,
 
-    output ibex_defines::exc_cause_e  exc_cause_o,
+    output ibex_pkg::exc_cause_e  exc_cause_o,
     output logic                  exc_ack_o,
     output logic                  exc_kill_o,
 
     // debug signals
     input  logic                  debug_req_i,
-    output ibex_defines::dbg_cause_e  debug_cause_o,
+    output ibex_pkg::dbg_cause_e  debug_cause_o,
     output logic                  debug_csr_save_o,
     input  logic                  debug_single_step_i,
     input  logic                  debug_ebreakm_i,
@@ -107,7 +107,7 @@ module ibex_controller (
     output logic                  perf_tbranch_o         // we are executing a taken branch
                                                          // instruction
 );
-  import ibex_defines::*;
+  import ibex_pkg::*;
 
   // FSM state encoding
   typedef enum logic [3:0] {

rtl/ibex_core.f

@@ -1,4 +1,4 @@
-ibex_defines.sv
+ibex_pkg.sv
 ibex_alu.sv
 ibex_compressed_decoder.sv
 ibex_controller.sv

rtl/ibex_core.sv

@@ -106,7 +106,7 @@ module ibex_core #(
 
 );
 
-  import ibex_defines::*;
+  import ibex_pkg::*;
 
   // IF/ID signals
   logic        instr_valid_id;

rtl/ibex_core_tracer.sv

@@ -87,7 +87,7 @@ module ibex_core_tracer #(
 
 );
 
-  import ibex_defines::*;
+  import ibex_pkg::*;
 
   ibex_core #(
     .MHPMCounterNum(MHPMCounterNum),

rtl/ibex_cs_registers.sv

@@ -41,9 +41,9 @@ module ibex_cs_registers #(
 
     // Interface to registers (SRAM like)
     input  logic                 csr_access_i,
-    input  ibex_defines::csr_num_e   csr_addr_i,
+    input  ibex_pkg::csr_num_e   csr_addr_i,
     input  logic [31:0]          csr_wdata_i,
-    input  ibex_defines::csr_op_e    csr_op_i,
+    input  ibex_pkg::csr_op_e    csr_op_i,
     output logic [31:0]          csr_rdata_o,
 
     // Interrupts
@@ -51,7 +51,7 @@ module ibex_cs_registers #(
     output logic [31:0]          csr_mepc_o,
 
     // debug
-    input  ibex_defines::dbg_cause_e debug_cause_i,
+    input  ibex_pkg::dbg_cause_e debug_cause_i,
     input  logic                 debug_csr_save_i,
     output logic [31:0]          csr_depc_o,
     output logic                 debug_single_step_o,
@@ -66,7 +66,7 @@ module ibex_cs_registers #(
     input  logic                 csr_restore_dret_i,
     input  logic                 csr_save_cause_i,
     input  logic [31:0]          csr_mtvec_i,
-    input  ibex_defines::exc_cause_e csr_mcause_i,
+    input  ibex_pkg::exc_cause_e csr_mcause_i,
     input  logic [31:0]          csr_mtval_i,
     output logic                 illegal_csr_insn_o,     // access to non-existent CSR,
                                                          // with wrong priviledge level, or
@@ -86,7 +86,7 @@ module ibex_cs_registers #(
     input  logic                 lsu_busy_i
 );
 
-  import ibex_defines::*;
+  import ibex_pkg::*;
 
   // misa
   localparam logic [1:0] MXL = 2'd1; // M-XLEN: XLEN in M-Mode for RV32

rtl/ibex_decoder.sv

@@ -49,8 +49,8 @@ module ibex_decoder #(
     input  logic                 illegal_c_insn_i,      // compressed instruction decode failed
 
     // immediates
-    output ibex_defines::imm_a_sel_e imm_a_mux_sel_o,       // immediate selection for operand a
-    output ibex_defines::imm_b_sel_e imm_b_mux_sel_o,       // immediate selection for operand b
+    output ibex_pkg::imm_a_sel_e imm_a_mux_sel_o,       // immediate selection for operand a
+    output ibex_pkg::imm_b_sel_e imm_b_mux_sel_o,       // immediate selection for operand b
     output logic [31:0]          imm_i_type_o,
     output logic [31:0]          imm_s_type_o,
     output logic [31:0]          imm_b_type_o,
@@ -59,29 +59,29 @@ module ibex_decoder #(
     output logic [31:0]          zimm_rs1_type_o,
 
     // register file
-    output ibex_defines::rf_wd_sel_e regfile_wdata_sel_o,   // RF write data selection
+    output ibex_pkg::rf_wd_sel_e regfile_wdata_sel_o,   // RF write data selection
     output logic                 regfile_we_o,          // write enable for regfile
     output logic [4:0]           regfile_raddr_a_o,
     output logic [4:0]           regfile_raddr_b_o,
     output logic [4:0]           regfile_waddr_o,
 
     // ALU
-    output ibex_defines::alu_op_e    alu_operator_o,        // ALU operation selection
-    output ibex_defines::op_a_sel_e  alu_op_a_mux_sel_o,    // operand a selection: reg value, PC,
+    output ibex_pkg::alu_op_e    alu_operator_o,        // ALU operation selection
+    output ibex_pkg::op_a_sel_e  alu_op_a_mux_sel_o,    // operand a selection: reg value, PC,
                                                         // immediate or zero
-    output ibex_defines::op_b_sel_e  alu_op_b_mux_sel_o,    // operand b selection: reg value or
+    output ibex_pkg::op_b_sel_e  alu_op_b_mux_sel_o,    // operand b selection: reg value or
                                                         // immediate
 
     // MULT & DIV
     output logic                 mult_en_o,             // perform integer multiplication
     output logic                 div_en_o,              // perform integer division or
                                                         // remainder
-    output ibex_defines::md_op_e     multdiv_operator_o,
+    output ibex_pkg::md_op_e     multdiv_operator_o,
     output logic [1:0]           multdiv_signed_mode_o,
 
     // CSRs
     output logic                 csr_access_o,          // access to CSR
-    output ibex_defines::csr_op_e    csr_op_o,              // operation to perform on CSR
+    output ibex_pkg::csr_op_e    csr_op_o,              // operation to perform on CSR
     output logic                 csr_status_o,          // access to xstatus CSR
 
     // LSU
@@ -98,7 +98,7 @@ module ibex_decoder #(
     output logic                 branch_in_dec_o
 );
 
-  import ibex_defines::*;
+  import ibex_pkg::*;
 
   logic        illegal_insn;
   logic        illegal_reg_rv32e;

rtl/ibex_ex_block.sv

@@ -33,12 +33,12 @@ module ibex_ex_block #(
     input  logic              rst_ni,
 
     // ALU
-    input  ibex_defines::alu_op_e alu_operator_i,
+    input  ibex_pkg::alu_op_e alu_operator_i,
     input  logic [31:0]       alu_operand_a_i,
     input  logic [31:0]       alu_operand_b_i,
 
     // Multiplier/Divider
-    input  ibex_defines::md_op_e  multdiv_operator_i,
+    input  ibex_pkg::md_op_e  multdiv_operator_i,
     input  logic              mult_en_i,
     input  logic              div_en_i,
     input  logic  [1:0]       multdiv_signed_mode_i,
@@ -54,7 +54,7 @@ module ibex_ex_block #(
     output logic              ex_valid_o             // EX has valid output
 );
 
-  import ibex_defines::*;
+  import ibex_pkg::*;
 
   localparam bit MULT_TYPE = 1; // 0 -> SLOW, 1 -> FAST
 

rtl/ibex_id_stage.sv

@@ -60,8 +60,8 @@ module ibex_id_stage #(
 
     // IF and ID stage signals
     output logic                  pc_set_o,
-    output ibex_defines::pc_sel_e     pc_mux_o,
-    output ibex_defines::exc_pc_sel_e exc_pc_mux_o,
+    output ibex_pkg::pc_sel_e     pc_mux_o,
+    output ibex_pkg::exc_pc_sel_e exc_pc_mux_o,
 
     input  logic                  illegal_c_insn_i,
 
@@ -71,21 +71,21 @@ module ibex_id_stage #(
     input  logic                  ex_valid_i,     // EX stage has valid output
     input  logic                  lsu_valid_i,    // LSU has valid output, or is done
     // ALU
-    output ibex_defines::alu_op_e     alu_operator_ex_o,
+    output ibex_pkg::alu_op_e     alu_operator_ex_o,
     output logic [31:0]           alu_operand_a_ex_o,
     output logic [31:0]           alu_operand_b_ex_o,
 
     // MUL, DIV
     output logic                  mult_en_ex_o,
     output logic                  div_en_ex_o,
-    output ibex_defines::md_op_e      multdiv_operator_ex_o,
+    output ibex_pkg::md_op_e      multdiv_operator_ex_o,
     output logic  [1:0]           multdiv_signed_mode_ex_o,
     output logic [31:0]           multdiv_operand_a_ex_o,
     output logic [31:0]           multdiv_operand_b_ex_o,
 
     // CSR
     output logic                  csr_access_o,
-    output ibex_defines::csr_op_e     csr_op_o,
+    output ibex_pkg::csr_op_e     csr_op_o,
     output logic                  csr_save_if_o,
     output logic                  csr_save_id_o,
     output logic                  csr_restore_mret_id_o,
@@ -111,13 +111,13 @@ module ibex_id_stage #(
     input  logic                  m_irq_enable_i,
     output logic                  irq_ack_o,
     output logic [4:0]            irq_id_o,
-    output ibex_defines::exc_cause_e  exc_cause_o,
+    output ibex_pkg::exc_cause_e  exc_cause_o,
 
     input  logic                  lsu_load_err_i,
     input  logic                  lsu_store_err_i,
 
     // Debug Signal
-    output ibex_defines::dbg_cause_e  debug_cause_o,
+    output ibex_pkg::dbg_cause_e  debug_cause_o,
     output logic                  debug_csr_save_o,
     input  logic                  debug_req_i,
     input  logic                  debug_single_step_i,
@@ -146,7 +146,7 @@ module ibex_id_stage #(
     output logic                  instr_ret_compressed_o
 );
 
-  import ibex_defines::*;
+  import ibex_pkg::*;
 
   // Decoder/Controller, ID stage internal signals
   logic        illegal_insn_dec;

rtl/ibex_if_stage.sv

@@ -64,9 +64,9 @@ module ibex_if_stage #(
                                                             // the interrupt/exception
     input  logic [31:0]           csr_depc_i,               // PC to restore after handling
                                                             // the debug request
-    input  ibex_defines::pc_sel_e     pc_mux_i,                 // selector for PC multiplexer
-    input  ibex_defines::exc_pc_sel_e exc_pc_mux_i,             // selects ISR address
-    input  ibex_defines::exc_cause_e  exc_cause,                // selects ISR address for
+    input  ibex_pkg::pc_sel_e     pc_mux_i,                 // selector for PC multiplexer
+    input  ibex_pkg::exc_pc_sel_e exc_pc_mux_i,             // selects ISR address
+    input  ibex_pkg::exc_cause_e  exc_cause,                // selects ISR address for
                                                                 // vectorized interrupt lines
 
     // jump and branch target and decision
@@ -83,7 +83,7 @@ module ibex_if_stage #(
     output logic                  perf_imiss_o              // instr fetch miss
 );
 
-  import ibex_defines::*;
+  import ibex_pkg::*;
 
   logic              offset_in_init_d, offset_in_init_q;
   logic              have_instr;

rtl/ibex_int_controller.sv

@@ -38,7 +38,7 @@ module ibex_int_controller (
     input  logic        m_IE_i          // interrupt enable bit from CSR (M mode)
 );
 
-  import ibex_defines::*;
+  import ibex_pkg::*;
 
   typedef enum logic [1:0] { IDLE, IRQ_PENDING, IRQ_DONE} exc_ctrl_e;
   exc_ctrl_e exc_ctrl_ns, exc_ctrl_cs;

rtl/ibex_multdiv_fast.sv

@@ -28,7 +28,7 @@ module ibex_multdiv_fast (
     input  logic             rst_ni,
     input  logic             mult_en_i,
     input  logic             div_en_i,
-    input  ibex_defines::md_op_e operator_i,
+    input  ibex_pkg::md_op_e operator_i,
     input  logic  [1:0]      signed_mode_i,
     input  logic [31:0]      op_a_i,
     input  logic [31:0]      op_b_i,
@@ -43,7 +43,7 @@ module ibex_multdiv_fast (
     output logic             valid_o
 );
 
-  import ibex_defines::*;
+  import ibex_pkg::*;
 
   logic [ 4:0] div_counter_q, div_counter_n;
   typedef enum logic [1:0] {

rtl/ibex_multdiv_slow.sv

@@ -25,7 +25,7 @@ module ibex_multdiv_slow (
     input  logic             rst_ni,
     input  logic             mult_en_i,
     input  logic             div_en_i,
-    input  ibex_defines::md_op_e operator_i,
+    input  ibex_pkg::md_op_e operator_i,
     input  logic  [1:0]      signed_mode_i,
     input  logic [31:0]      op_a_i,
     input  logic [31:0]      op_b_i,
@@ -40,7 +40,7 @@ module ibex_multdiv_slow (
     output logic             valid_o
 );
 
-  import ibex_defines::*;
+  import ibex_pkg::*;
 
   logic [ 4:0] multdiv_state_q, multdiv_state_d, multdiv_state_m1;
   typedef enum logic [2:0] {

rtl/ibex_pkg.sv

@@ -19,9 +19,9 @@
 ////////////////////////////////////////////////////////////////////////////////
 
 /**
- * Defines for various constants used by the processor core
+ * Package with constants used by Ibex
  */
-package ibex_defines;
+package ibex_pkg;
 
 
 /////////////

rtl/ibex_tracer.sv

@@ -19,8 +19,8 @@
 
 `ifndef VERILATOR
 
-import ibex_defines::*;
-import ibex_tracer_defines::*;
+import ibex_pkg::*;
+import ibex_tracer_pkg::*;
 
 // Source/Destination register instruction index
 `define REG_S1 19:15

rtl/ibex_tracer_pkg.sv

@@ -3,8 +3,8 @@
 // Licensed under the Apache License, Version 2.0, see LICENSE for details.
 // SPDX-License-Identifier: Apache-2.0
 
-package ibex_tracer_defines;
-import ibex_defines::*;
+package ibex_tracer_pkg;
+import ibex_pkg::*;
 
 // instruction masks (for tracer)
 parameter logic [31:0] INSTR_LUI     = { 25'b?,                           {OPCODE_LUI  } };

src_files.yml

@@ -2,7 +2,7 @@ ibex:
   incdirs: [
   ]
   files: [
-    ibex_defines.sv,
+    ibex_pkg.sv,
     ibex_alu.sv,
     ibex_compressed_decoder.sv,
     ibex_controller.sv,
@@ -27,8 +27,8 @@ ibex_vip_rtl:
   incdirs: [
   ]
   files: [
-    ibex_defines.sv,
-    ibex_tracer_defines.sv,
+    ibex_pkg.sv,
+    ibex_tracer_pkg.sv,
     ibex_tracer.sv,
   ]
 ibex_regfile_rtl: