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https://github.com/lowRISC/ibex.git
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[DV] Test debug requests during interrupt handler execution (#565)
Signed-off-by: Udi <udij@google.com>
This commit is contained in:
udinator
GitHub
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commit
43752a6c19
2 changed files with 73 additions and 37 deletions
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@ -298,10 +298,31 @@
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gen_opts: >
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+require_signature_addr=1
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+gen_debug_section=1
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+enable_interrupt=1
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+randomize_csr=1
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+no_csr_instr=1
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+no_fence=1
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rtl_test: core_ibex_debug_irq_test
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rtl_test: core_ibex_irq_in_debug_test
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sim_opts: >
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+require_signature_addr=1
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+enable_debug_seq=1
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+enable_irq_multiple_seq=1
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compare_opts:
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compare_final_value_only: 1
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- test: riscv_debug_in_irq_test
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description: >
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Send debug stimulus while core is in an interrupt handler
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iterations: 10
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gen_test: riscv_rand_instr_test
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gen_opts: >
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+require_signature_addr=1
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+gen_debug_section=1
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+enable_interrupt=1
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+randomize_csr=1
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no_csr_instr=1
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+no_fence=1
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rtl_test: core_ibex_debug_in_irq_test
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sim_opts: >
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+require_signature_addr=1
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+enable_debug_seq=1
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@ -188,7 +188,7 @@ class core_ibex_debug_intr_basic_test extends core_ibex_base_test;
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end
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begin
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if (cfg.enable_debug_seq) begin
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send_debug_stimulus();
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stress_debug();
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end
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end
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join_none
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@ -323,7 +323,7 @@ class core_ibex_debug_intr_basic_test extends core_ibex_base_test;
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// Basic debug stimulus check for Ibex for debug stimulus stress tests: check that Ibex enters
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// debug mode properly after stimulus is sent and then check that a dret is encountered signifying
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// the end of debug mode.
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virtual task send_debug_stimulus();
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virtual task stress_debug();
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fork
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begin
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vseq.start_debug_stress_seq();
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@ -398,7 +398,7 @@ class core_ibex_directed_test extends core_ibex_debug_intr_basic_test;
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end
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begin
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if (cfg.enable_debug_seq) begin
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send_debug_stimulus();
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stress_debug();
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end
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end
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join_none
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@ -433,6 +433,17 @@ class core_ibex_directed_test extends core_ibex_debug_intr_basic_test;
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// Checker functions/tasks that might be commonly used
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//------------------------------------------------------
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// Send a single debug request and perform all relevant checks
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virtual task send_debug_stimulus(priv_lvl_e mode, string debug_status_err_msg);
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vseq.start_debug_single_seq();
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check_next_core_status(IN_DEBUG_MODE, debug_status_err_msg, 1000);
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check_priv_mode(PRIV_LVL_M);
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wait_for_csr_write(CSR_DCSR, 500);
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check_dcsr_prv(mode);
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check_dcsr_cause(DBG_CAUSE_HALTREQ);
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wait_ret("dret", 5000);
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endtask
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// Illegal instruction checker
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virtual task check_illegal_insn(string exception_msg);
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check_next_core_status(HANDLING_EXCEPTION, "Core did not jump to vectored exception handler", 1000);
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@ -510,10 +521,10 @@ class core_ibex_irq_csr_test extends core_ibex_directed_test;
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endclass
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// Debug mode IRQ test
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class core_ibex_debug_irq_test extends core_ibex_directed_test;
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// Tests irqs asserted in debug mode
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class core_ibex_irq_in_debug_test extends core_ibex_directed_test;
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`uvm_component_utils(core_ibex_debug_irq_test)
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`uvm_component_utils(core_ibex_irq_in_debug_test)
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`uvm_component_new
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virtual task check_stimulus();
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@ -547,6 +558,37 @@ class core_ibex_debug_irq_test extends core_ibex_directed_test;
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endclass
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// Tests debug mode asserted during irq handler
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class core_ibex_debug_in_irq_test extends core_ibex_directed_test;
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`uvm_component_utils(core_ibex_debug_in_irq_test)
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`uvm_component_new
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virtual task check_stimulus();
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// send first part of irq/checking routine
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// then assert basic debug stimulus
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// check that core enters and exits debug mode correctly
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// then finish interrupt handling routine
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bit valid_irq;
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forever begin
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send_irq_stimulus_start(1'b0, valid_irq);
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if (valid_irq) begin
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fork
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begin
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send_debug_stimulus(operating_mode, "Core did not enter debug mode from interrupt handler");
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end
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begin
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wait(dut_vif.dret == 1'b1);
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send_irq_stimulus_end();
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end
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join
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end
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clk_vif.wait_clks($urandom_range(250, 500));
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end
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endtask
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endclass
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// Nested interrupt test class (with multiple interrupts)
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class core_ibex_nested_irq_test extends core_ibex_directed_test;
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@ -588,20 +630,7 @@ class core_ibex_debug_wfi_test extends core_ibex_directed_test;
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wait (dut_vif.wfi === 1'b1);
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wait (dut_vif.core_sleep === 1'b1);
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clk_vif.wait_clks($urandom_range(100));
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vseq.start_debug_single_seq();
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// After assserting this signal, core should wake up and jump into debug mode from WFI state
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// - next handshake should be a notification that the core is now in debug mode
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check_next_core_status(IN_DEBUG_MODE, "Core did not jump into debug mode from WFI state",
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1000);
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check_priv_mode(PRIV_LVL_M);
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// We don't want to trigger debug stimulus for any WFI instructions encountered inside the
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// debug rom - those should act as NOP instructions - so we wait until hitting the end of the
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// debug rom.
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// We also want to check that dcsr.cause has been set correctly
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wait_for_csr_write(CSR_DCSR, 500);
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check_dcsr_prv(init_operating_mode);
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check_dcsr_cause(DBG_CAUSE_HALTREQ);
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wait_ret("dret", 5000);
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send_debug_stimulus(init_operating_mode, "Core did not jump into debug mode from WFI state");
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end
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endtask
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@ -618,25 +647,11 @@ class core_ibex_debug_csr_test extends core_ibex_directed_test;
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// wait for a dummy write to mstatus in init code
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wait(csr_vif.csr_access === 1'b1 && csr_vif.csr_addr === CSR_MSTATUS &&
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csr_vif.csr_op != CSR_OP_READ);
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vseq.start_debug_single_seq();
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check_next_core_status(IN_DEBUG_MODE, "Core did not jump into debug mode from WFI state",
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1000);
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check_priv_mode(PRIV_LVL_M);
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wait_for_csr_write(CSR_DCSR, 500);
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check_dcsr_prv(init_operating_mode);
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check_dcsr_cause(DBG_CAUSE_HALTREQ);
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wait_ret("dret", 5000);
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send_debug_stimulus(init_operating_mode, "Core did not trap to debug mode upon debug stimulus");
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// wait for a dummy write to mie in the init code
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wait(csr_vif.csr_access === 1'b1 && csr_vif.csr_addr === CSR_MIE &&
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csr_vif.csr_op != CSR_OP_READ);
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vseq.start_debug_single_seq();
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check_next_core_status(IN_DEBUG_MODE, "Core did not jump into debug mode from WFI state",
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1000);
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check_priv_mode(PRIV_LVL_M);
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wait_for_csr_write(CSR_DCSR, 500);
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check_dcsr_prv(init_operating_mode);
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check_dcsr_cause(DBG_CAUSE_HALTREQ);
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wait_ret("dret", 5000);
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send_debug_stimulus(init_operating_mode, "Core did not trap to debug mode upon debug stimulus");
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endtask
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endclass
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