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Avoid explicit module names references to signals

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This allows changing the module names without breaking the sim flow.
This commit is contained in:
Flavien Solt 2023-03-06 21:36:39 +01:00 • committed by Greg Chadwick
parent 94f9f16c07
commit 43aeda171d
1 changed files with 2 additions and 2 deletions
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4
rtl/ibex_controller.sv
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@ -174,8 +174,8 @@ module ibex_controller #(
always_ff @(negedge clk_i) begin
// print warning in case of decoding errors
if ((ctrl_fsm_cs == DECODE) && instr_valid_i && !instr_fetch_err_i && illegal_insn_d) begin
$display("%t: Illegal instruction (hart %0x) at PC 0x%h: 0x%h", $time, ibex_core.hart_id_i,
ibex_id_stage.pc_id_i, ibex_id_stage.instr_rdata_i);
$display("%t: Illegal instruction (hart %0x) at PC 0x%h: 0x%h", $time, u_ibex_core.hart_id_i,
pc_id_i, id_stage_i.instr_rdata_i);
end
end
// synopsys translate_on