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Make instr_addr_o in prefetcher independent of instr_rvalid_i
This commit is contained in:
Andreas Traber
parent
efb607a792
commit
4571bc30ae
1 changed files with 55 additions and 46 deletions
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@ -73,7 +73,7 @@ module prefetch_L0_buffer
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always_ff @(posedge clk or negedge rst_n)
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begin
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if(~rst_n)
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if (~rst_n)
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begin
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CS <= EMPTY;
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current_address <= '0;
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@ -85,7 +85,7 @@ module prefetch_L0_buffer
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begin
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CS <= NS;
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if(branch_i)
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if (branch_i)
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begin
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current_address <= {addr_i[31:4],4'b0000};
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pointer_cs <= addr_i[3:2];
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@ -93,7 +93,7 @@ module prefetch_L0_buffer
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end
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else
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begin
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if(update_current_address) begin
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if (update_current_address) begin
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last_address <= current_address;
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current_address <= current_address + 5'h10; // jump to the next cache line
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end
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@ -127,10 +127,11 @@ module prefetch_L0_buffer
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EMPTY:
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begin
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instr_req_o = branch_i;
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if(branch_i) // make the request to icache
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if (branch_i) // make the request to icache
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begin
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if(instr_gnt_i)
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if (instr_gnt_i)
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NS = WAIT_RVALID;
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else
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NS = WAIT_GNT;
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@ -143,14 +144,15 @@ module prefetch_L0_buffer
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WAIT_RVALID:
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begin
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if(branch_i) // there is a pending branch
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if (branch_i) // there is a pending branch
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begin
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if(instr_rvalid_i)
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instr_addr_o = {addr_i[31:4],4'b0000};
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if (instr_rvalid_i)
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begin
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instr_req_o = 1'b1;
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instr_addr_o = {addr_i[31:4],4'b0000};
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if(instr_gnt_i)
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if (instr_gnt_i)
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NS = WAIT_RVALID;
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else
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NS = WAIT_GNT;
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@ -165,19 +167,22 @@ module prefetch_L0_buffer
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begin
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valid_o = instr_rvalid_i;
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if(instr_rvalid_i)
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// prepare address even if we don't need it
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// this removes the dependency for instr_addr_o on instr_rvalid_i
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instr_addr_o = current_address + 5'h10;
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if (instr_rvalid_i)
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begin
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if(&pointer_cs) // we are receiving the last packet, then prefetch the next one
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if (&pointer_cs) // we are receiving the last packet, then prefetch the next one
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begin
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is_prefetch_n = 1'b1;
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instr_req_o = 1'b1; //if the cpu is ready to sample the instruction, then ask for a new instruction
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instr_addr_o = current_address + 5'h10;
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pointer_ns = '0;
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instr_req_o = 1'b1;
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pointer_ns = '0;
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update_current_address = 1'b1;
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if(instr_gnt_i)
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if (instr_gnt_i)
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NS = WAIT_RVALID;
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else
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NS = WAIT_GNT;
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@ -185,7 +190,8 @@ module prefetch_L0_buffer
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else // not the last chunk
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begin
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NS = VALID_L0;
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if(ready_L0)
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if (ready_L0)
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pointer_ns = pointer_cs + 1'b1;
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else
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pointer_ns = pointer_cs;
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@ -203,19 +209,19 @@ module prefetch_L0_buffer
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valid_o = 1'b1;
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valid_L0 = 1'b1;
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if(branch_i)
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if (branch_i)
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begin
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instr_req_o = 1'b1;
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instr_addr_o = {addr_i[31:4],4'b0000};
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if(instr_gnt_i)
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if (instr_gnt_i)
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NS = WAIT_RVALID;
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else
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NS = WAIT_GNT;
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end
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else
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begin
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if( &pointer_cs ) // we are dispathing the last packet, therefore prefetch the next cache line
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if ( &pointer_cs ) // we are dispathing the last packet, therefore prefetch the next cache line
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begin
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is_prefetch_n = 1'b1;
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instr_req_o = 1'b1;
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@ -223,16 +229,16 @@ module prefetch_L0_buffer
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pointer_ns = '0;
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update_current_address = 1'b1;
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if(instr_gnt_i)
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if (instr_gnt_i)
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NS = WAIT_RVALID;
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else
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NS = WAIT_GNT;
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end
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else
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begin
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if(ready_L0)
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if (ready_L0)
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begin
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pointer_ns = pointer_cs + 1'b1;
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pointer_ns = pointer_cs + 1'b1;
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end
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NS = VALID_L0;
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@ -242,12 +248,12 @@ module prefetch_L0_buffer
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WAIT_GNT:
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begin
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if(branch_i)
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if (branch_i)
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begin
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instr_req_o = 1'b1;
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instr_addr_o = {addr_i[31:4],4'b0000};
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if(instr_gnt_i)
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if (instr_gnt_i)
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NS = WAIT_RVALID;
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else
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NS = WAIT_GNT;
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@ -257,7 +263,7 @@ module prefetch_L0_buffer
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instr_req_o = 1'b1;
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instr_addr_o = current_address; // has been previously updated
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if(instr_gnt_i)
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if (instr_gnt_i)
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NS = WAIT_RVALID;
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else
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NS = WAIT_GNT;
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@ -266,22 +272,25 @@ module prefetch_L0_buffer
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WAIT_ABORTED:
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begin
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clear_buffer = 1'b1;
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clear_buffer = 1'b1;
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if(instr_rvalid_i)
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begin
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instr_req_o = 1'b1;
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instr_addr_o = current_address;
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// prepare address even if we don't need it
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// this removes the dependency for instr_addr_o on instr_rvalid_i
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instr_addr_o = current_address;
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if(instr_gnt_i)
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NS = WAIT_RVALID;
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else
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NS = WAIT_GNT;
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end
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else
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begin
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NS = WAIT_ABORTED;
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end
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if (instr_rvalid_i)
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begin
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instr_req_o = 1'b1;
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if (instr_gnt_i)
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NS = WAIT_RVALID;
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else
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NS = WAIT_GNT;
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end
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else
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begin
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NS = WAIT_ABORTED;
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end
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end //~WAIT_ABORTED
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default:
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@ -323,9 +332,9 @@ module prefetch_L0_buffer
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begin
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if (valid_L0) begin
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case(addr_o[3:2])
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2'b00: begin unaligned_rdata_o[31:16] = L0_buffer[1][15:0]; unaligned_valid_o = 1'b1; end
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2'b01: begin unaligned_rdata_o[31:16] = L0_buffer[2][15:0]; unaligned_valid_o = 1'b1; end
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2'b10: begin unaligned_rdata_o[31:16] = L0_buffer[3][15:0]; unaligned_valid_o = 1'b1; end
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2'b00: begin unaligned_rdata_o[31:16] = L0_buffer[1][15:0]; unaligned_valid_o = 1'b1; end
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2'b01: begin unaligned_rdata_o[31:16] = L0_buffer[2][15:0]; unaligned_valid_o = 1'b1; end
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2'b10: begin unaligned_rdata_o[31:16] = L0_buffer[3][15:0]; unaligned_valid_o = 1'b1; end
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// this state is only interesting if we have already done a prefetch
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2'b11: begin
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unaligned_rdata_o[31:16] = L0_buffer[0][15:0];
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@ -342,9 +351,9 @@ module prefetch_L0_buffer
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// icache
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case(addr_o[3:2])
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2'b00: begin unaligned_rdata_o[31:16] = instr_rdata_i[1][15:0]; unaligned_valid_o = instr_rvalid_i; end
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2'b01: begin unaligned_rdata_o[31:16] = instr_rdata_i[2][15:0]; unaligned_valid_o = instr_rvalid_i; end
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2'b10: begin unaligned_rdata_o[31:16] = instr_rdata_i[3][15:0]; unaligned_valid_o = instr_rvalid_i; end
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2'b00: begin unaligned_rdata_o[31:16] = instr_rdata_i[1][15:0]; unaligned_valid_o = instr_rvalid_i; end
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2'b01: begin unaligned_rdata_o[31:16] = instr_rdata_i[2][15:0]; unaligned_valid_o = instr_rvalid_i; end
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2'b10: begin unaligned_rdata_o[31:16] = instr_rdata_i[3][15:0]; unaligned_valid_o = instr_rvalid_i; end
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2'b11:
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begin
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@ -364,7 +373,7 @@ module prefetch_L0_buffer
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always_ff @(posedge clk or negedge rst_n)
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begin
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if(~rst_n)
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if (~rst_n)
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begin
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L0_buffer <= '0;
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previous_chunk <= '0;
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