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[doc] Drop EXPERIMENTAL for verified features

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Many things were marked as 'EXPERIMENTAL' where that is no longer the
case. This brings things up to date.
This commit is contained in:
Greg Chadwick 2023-02-10 15:19:32 +00:00 • committed by Greg Chadwick
parent 4c903d1033
commit 45b7272ee5
3 changed files with 11 additions and 17 deletions
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23
doc/02_user/integration.rst
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@ -198,26 +198,23 @@ Parameters
| | | | "ibex_pkg::RegFileFPGA": Register file for FPGA targets |
| | | | "ibex_pkg::RegFileLatch": Latch-based register file for ASIC targets |
+------------------------------+---------------------+------------+-----------------------------------------------------------------------+
| ``BranchTargetALU`` | bit | 0 | *EXPERIMENTAL* - Enables branch target ALU removing a stall |
| | | | cycle from taken branches |
| ``BranchTargetALU`` | bit | 0 | Enables branch target ALU removing a stall cycle from taken branches |
+------------------------------+---------------------+------------+-----------------------------------------------------------------------+
| ``WritebackStage`` | bit | 0 | *EXPERIMENTAL* - Enables third pipeline stage (writeback) |
| | | | improving performance of loads and stores |
| ``WritebackStage`` | bit | 0 | Enables third pipeline stage (writeback) improving performance of |
| | | | loads and stores |
+------------------------------+---------------------+------------+-----------------------------------------------------------------------+
| ``ICache`` | bit | 0 | *EXPERIMENTAL* Enable instruction cache instead of prefetch |
| | | | buffer |
| ``ICache`` | bit | 0 | Enable instruction cache instead of prefetch buffer |
+------------------------------+---------------------+------------+-----------------------------------------------------------------------+
| ``ICacheECC`` | bit | 0 | *EXPERIMENTAL* Enable SECDED ECC protection in ICache (if |
| | | | ICache == 1) |
| ``ICacheECC`` | bit | 0 | Enable SECDED ECC protection in ICache (if ICache == 1) |
+------------------------------+---------------------+------------+-----------------------------------------------------------------------+
| ``ICacheScramble`` | bit | 0 | *EXPERIMENTAL* Enabling this parameter replaces tag and data RAMs of |
| | | | ICache with scrambling RAM primitives. |
| ``ICacheScramble`` | bit | 0 | Enabling this parameter replaces tag and data RAMs of ICache with |
| | | | scrambling RAM primitives. |
+------------------------------+---------------------+------------+-----------------------------------------------------------------------+
| ``BranchPrediction`` | bit | 0 | *EXPERIMENTAL* Enable Static branch prediction |
+------------------------------+---------------------+------------+-----------------------------------------------------------------------+
| ``SecureIbex`` | bit | 0 | *EXPERIMENTAL* Enable various additional features targeting |
| | | | secure code execution. Note: SecureIbex == 1'b1 and |
| | | | RV32M == ibex_pkg::RV32MNone is an illegal combination. |
| ``SecureIbex`` | bit | 0 | Enable various additional features targeting secure code execution. |
| | | | Note: SecureIbex == 1'b1 and RV32M == ibex_pkg::RV32MNone is an |
| | | | illegal combination. |
+------------------------------+---------------------+------------+-----------------------------------------------------------------------+
| ``RndCnstLfsrSeed`` | lfsr_seed_t | see above | Set the starting seed of the LFSR used to generate dummy instructions |
| | | | (only relevant when SecureIbex == 1'b1) |

3
doc/03_reference/cosim.rst
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@ -19,9 +19,6 @@ The RISC-V Formal Interface (RVFI) is used to provide information about retired
The RVFI has been extended to provide interrupt and debug information and the value of the ``mcycle`` CSR.
These extended signals have the prefix ``rvfi_ext``
The co-simulation system is EXPERIMENTAL.
It is disabled by default in the UVM DV environment currently, however it is intended to become the primary checking method for the UVM testbench.
Setup and Usage
---------------

2
doc/03_reference/pipeline_details.rst
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@ -26,7 +26,7 @@ See Multi- and Single-Cycle Instructions below for the details.
Third Pipeline Stage
--------------------
Ibex can be configured to have a third pipeline stage (Writeback) which has major effects on performance and instruction behaviour.
This feature is *EXPERIMENTAL* and the details of its impact are not yet documented here.
The details of its impact are not yet documented here.
All of the information presented below applies only to the two stage pipeline provided in the default configurations.
Multi- and Single-Cycle Instructions