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Add vector instructions to simulation tracer
This commit is contained in:
Andreas Traber
parent
96e6eb82d9
commit
47b713fd0d
3 changed files with 99 additions and 2 deletions
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@ -27,6 +27,7 @@
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`define INSTR_BGE { 17'b?, 3'b101, 5'b?, `OPCODE_BRANCH }
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`define INSTR_BLTU { 17'b?, 3'b110, 5'b?, `OPCODE_BRANCH }
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`define INSTR_BGEU { 17'b?, 3'b111, 5'b?, `OPCODE_BRANCH }
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`define INSTR_BALL { 17'b?, 3'b010, 5'b?, `OPCODE_BRANCH }
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// OPIMM
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`define INSTR_ADDI { 17'b?, 3'b000, 5'b?, `OPCODE_OPIMM }
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`define INSTR_SLTI { 17'b?, 3'b010, 5'b?, `OPCODE_OPIMM }
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@ -756,6 +756,7 @@ module riscv_core
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.rs1_value ( id_stage_i.operand_a_fw_id ),
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.rs2_value ( id_stage_i.operand_b_fw_id ),
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.rs3_value ( id_stage_i.alu_operand_c ),
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.rs2_value_vec ( id_stage_i.alu_operand_b ),
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.ex_valid ( ex_valid ),
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.ex_reg_addr ( regfile_alu_waddr_fw ),
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@ -783,7 +784,9 @@ module riscv_core
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.imm_s_type ( id_stage_i.imm_s_type ),
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.imm_sb_type ( id_stage_i.imm_sb_type ),
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.imm_s2_type ( id_stage_i.imm_s2_type ),
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.imm_s3_type ( id_stage_i.imm_s3_type )
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.imm_s3_type ( id_stage_i.imm_s3_type ),
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.imm_vs_type ( id_stage_i.imm_vs_type ),
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.imm_vu_type ( id_stage_i.imm_vu_type )
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);
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`endif
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@ -44,6 +44,7 @@ module riscv_tracer
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input logic [31:0] rs1_value,
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input logic [31:0] rs2_value,
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input logic [31:0] rs3_value,
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input logic [31:0] rs2_value_vec,
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input logic ex_valid,
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input logic [ 4:0] ex_reg_addr,
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@ -71,7 +72,9 @@ module riscv_tracer
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input logic [31:0] imm_s_type,
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input logic [31:0] imm_sb_type,
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input logic [31:0] imm_s2_type,
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input logic [31:0] imm_s3_type
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input logic [31:0] imm_s3_type,
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input logic [31:0] imm_vs_type,
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input logic [31:0] imm_vu_type
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);
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integer f;
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@ -210,6 +213,13 @@ module riscv_tracer
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end
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endfunction // printSBInstr
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function void printSBallInstr(input string mnemonic);
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begin
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regs_read.push_back({>> {rs1, rs1_value}});
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str = $sformatf("%-16s x%0d, %0d", mnemonic, rs1, $signed(imm_sb_type));
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end
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endfunction // printSBInstr
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function void printCSRInstr(input string mnemonic);
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logic [11:0] csr;
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begin
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@ -379,6 +389,87 @@ module riscv_tracer
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endcase
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end
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endfunction
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function void printVecInstr();
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string mnemonic;
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string str_asm;
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string str_args;
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string str_hb;
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string str_sci;
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string str_imm;
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begin
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// set mnemonic
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case (instr[31:26])
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6'b000000: begin mnemonic = "pv.add"; str_imm = $sformatf("0x%0d", imm_vs_type); end
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6'b000010: begin mnemonic = "pv.sub"; str_imm = $sformatf("0x%0d", imm_vs_type); end
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6'b000100: begin mnemonic = "pv.avg"; str_imm = $sformatf("0x%0d", imm_vs_type); end
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6'b000110: begin mnemonic = "pv.avgu"; str_imm = $sformatf("0x%0d", imm_vu_type); end
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6'b001000: begin mnemonic = "pv.min"; str_imm = $sformatf("0x%0d", imm_vs_type); end
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6'b001010: begin mnemonic = "pv.minu"; str_imm = $sformatf("0x%0d", imm_vu_type); end
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6'b001100: begin mnemonic = "pv.max"; str_imm = $sformatf("0x%0d", imm_vs_type); end
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6'b001110: begin mnemonic = "pv.maxu"; str_imm = $sformatf("0x%0d", imm_vu_type); end
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6'b010000: begin mnemonic = "pv.srl"; str_imm = $sformatf("0x%0d", imm_vs_type); end
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6'b010010: begin mnemonic = "pv.sra"; str_imm = $sformatf("0x%0d", imm_vs_type); end
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6'b010100: begin mnemonic = "pv.sll"; str_imm = $sformatf("0x%0d", imm_vs_type); end
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6'b010110: begin mnemonic = "pv.or"; str_imm = $sformatf("0x%0d", imm_vs_type); end
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6'b011000: begin mnemonic = "pv.xor"; str_imm = $sformatf("0x%0d", imm_vs_type); end
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6'b011010: begin mnemonic = "pv.and"; str_imm = $sformatf("0x%0d", imm_vs_type); end
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6'b011100: begin mnemonic = "pv.abs"; str_imm = $sformatf("0x%0d", imm_vs_type); end
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6'b011110: begin mnemonic = "pv.extract"; str_imm = $sformatf("0x%0d", imm_vs_type); end
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6'b100000: begin mnemonic = "pv.extractu"; str_imm = $sformatf("0x%0d", imm_vu_type); end
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6'b100010: begin mnemonic = "pv.insert"; str_imm = $sformatf("0x%0d", imm_vs_type); end
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// comparisons
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6'b000001: begin mnemonic = "pv.cmpeq"; str_imm = $sformatf("0x%0d", imm_vs_type); end
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6'b000011: begin mnemonic = "pv.cmpne"; str_imm = $sformatf("0x%0d", imm_vs_type); end
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6'b000101: begin mnemonic = "pv.cmpgt"; str_imm = $sformatf("0x%0d", imm_vs_type); end
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6'b000111: begin mnemonic = "pv.cmpge"; str_imm = $sformatf("0x%0d", imm_vs_type); end
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6'b001001: begin mnemonic = "pv.cmplt"; str_imm = $sformatf("0x%0d", imm_vs_type); end
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6'b001011: begin mnemonic = "pv.cmple"; str_imm = $sformatf("0x%0d", imm_vs_type); end
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6'b001101: begin mnemonic = "pv.cmpgtu"; str_imm = $sformatf("0x%0d", imm_vu_type); end
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6'b001111: begin mnemonic = "pv.cmpgeu"; str_imm = $sformatf("0x%0d", imm_vu_type); end
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6'b010001: begin mnemonic = "pv.cmpltu"; str_imm = $sformatf("0x%0d", imm_vu_type); end
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6'b010011: begin mnemonic = "pv.cmpleu"; str_imm = $sformatf("0x%0d", imm_vu_type); end
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default: begin
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printMnemonic("INVALID");
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return;
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end
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endcase
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// always read rs1 and write rd
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regs_read.push_back({>> {rs1, rs1_value}});
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regs_write.push_back({>> {rd, 'x}});
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case (instr[14:13])
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2'b00: begin
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str_sci = "";
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str_args = $sformatf("x%0d, x%0d, x%0d", rd, rs1, rs2);
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regs_read.push_back({>> {rs2, rs2_value}});
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end
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2'b10: begin
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str_sci = ".sc";
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str_args = $sformatf("x%0d, x%0d, x%0d", rd, rs1, rs2);
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regs_read.push_back({>> {rs2, rs2_value_vec}});
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end
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2'b11: begin
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str_sci = ".sci";
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str_args = $sformatf("x%0d, x%0d, %s", rd, rs1, str_imm);
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end
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endcase
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if (instr[12])
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str_hb = ".b";
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else
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str_hb = ".h";
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str_asm = $sformatf("%s%s%s", mnemonic, str_sci, str_hb);
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str = $sformatf("%-16s %s", str_asm, str_args);
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end
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endfunction
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endclass
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mailbox instr_ex = new (2);
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@ -507,6 +598,7 @@ module riscv_tracer
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`INSTR_BGE: trace.printSBInstr("bge");
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`INSTR_BLTU: trace.printSBInstr("bltu");
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`INSTR_BGEU: trace.printSBInstr("bgeu");
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`INSTR_BALL: trace.printSBallInstr("pv.ball");
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// OPIMM
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`INSTR_ADDI: trace.printIInstr("addi");
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`INSTR_SLTI: trace.printIInstr("slti");
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@ -569,6 +661,7 @@ module riscv_tracer
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{25'b?, `OPCODE_STORE}: trace.printStoreInstr();
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{25'b?, `OPCODE_STORE_POST}: trace.printStoreInstr();
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{25'b?, `OPCODE_HWLOOP}: trace.printHwloopInstr();
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{25'b?, `OPCODE_VECOP}: trace.printVecInstr();
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default: trace.printMnemonic("INVALID");
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endcase // unique case (instr)
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