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Use exc_cause in IF stage directly, add missing casts to enum type

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In case of interrupts, `exc_cause` carries the interrupt ID in the lower
bits and its MSB is 0 anyway. There is no need to forward only the lower
bits to the IF stage.
This commit is contained in:
Pirmin Vogel 2019-05-08 15:07:52 +01:00 • committed by Philipp Wagner
parent 53f2fb9350
commit 49fa87ba44
3 changed files with 6 additions and 6 deletions
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4
rtl/ibex_controller.sv
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@ -312,10 +312,10 @@ module ibex_controller (
pc_set_o = 1'b1; pc_set_o = 1'b1;
exc_pc_mux_o = EXC_PC_IRQ; exc_pc_mux_o = EXC_PC_IRQ;
exc_cause_o = {1'b0,irq_id_ctrl_i}; exc_cause_o = exc_cause_e'({1'b0, irq_id_ctrl_i});
csr_save_cause_o = 1'b1; csr_save_cause_o = 1'b1;
csr_cause_o = {1'b1,irq_id_ctrl_i}; csr_cause_o = exc_cause_e'({1'b1, irq_id_ctrl_i});
csr_save_if_o = 1'b1; csr_save_if_o = 1'b1;

4
rtl/ibex_core.sv
View file

@ -89,7 +89,7 @@ module ibex_core #(
logic pc_set; logic pc_set;
pc_sel_e pc_mux_id; // Mux selector for next PC pc_sel_e pc_mux_id; // Mux selector for next PC
exc_pc_sel_e exc_pc_mux_id; // Mux selector for exception PC exc_pc_sel_e exc_pc_mux_id; // Mux selector for exception PC
exc_cause_e exc_cause; exc_cause_e exc_cause; // Exception cause + IRQ ID for vectorized interrupt lines
logic lsu_load_err; logic lsu_load_err;
logic lsu_store_err; logic lsu_store_err;
@ -256,7 +256,7 @@ module ibex_core #(
.depc_i ( depc ), // debug return address .depc_i ( depc ), // debug return address
.pc_mux_i ( pc_mux_id ), // sel for pc multiplexer .pc_mux_i ( pc_mux_id ), // sel for pc multiplexer
.exc_pc_mux_i ( exc_pc_mux_id ), .exc_pc_mux_i ( exc_pc_mux_id ),
.exc_vec_pc_mux_i ( exc_cause[4:0] ), .exc_vec_pc_mux_i ( exc_cause ),
// Jump targets // Jump targets
.jump_target_ex_i ( jump_target_ex ), .jump_target_ex_i ( jump_target_ex ),

4
rtl/ibex_if_stage.sv
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@ -60,7 +60,7 @@ module ibex_if_stage #(
input logic [31:0] depc_i, // address used to restore PC when the debug is served input logic [31:0] depc_i, // address used to restore PC when the debug is served
input ibex_defines::pc_sel_e pc_mux_i, // sel for pc multiplexer input ibex_defines::pc_sel_e pc_mux_i, // sel for pc multiplexer
input ibex_defines::exc_pc_sel_e exc_pc_mux_i, // selects ISR address input ibex_defines::exc_pc_sel_e exc_pc_mux_i, // selects ISR address
input logic [4:0] exc_vec_pc_mux_i, // selects ISR address for vectorized input ibex_defines::exc_cause_e exc_vec_pc_mux_i, // selects ISR address for vectorized
// interrupt lines // interrupt lines
// jump and branch target and decision // jump and branch target and decision
@ -103,7 +103,7 @@ module ibex_if_stage #(
EXC_PC_ILLINSN: exc_pc = { boot_addr_i[31:8], {EXC_OFF_ILLINSN} }; EXC_PC_ILLINSN: exc_pc = { boot_addr_i[31:8], {EXC_OFF_ILLINSN} };
EXC_PC_ECALL: exc_pc = { boot_addr_i[31:8], {EXC_OFF_ECALL} }; EXC_PC_ECALL: exc_pc = { boot_addr_i[31:8], {EXC_OFF_ECALL} };
EXC_PC_BREAKPOINT: exc_pc = { boot_addr_i[31:8], {EXC_OFF_BREAKPOINT} }; EXC_PC_BREAKPOINT: exc_pc = { boot_addr_i[31:8], {EXC_OFF_BREAKPOINT} };
EXC_PC_IRQ: exc_pc = { boot_addr_i[31:8], 1'b0, exc_vec_pc_mux_i[4:0], 2'b0 }; EXC_PC_IRQ: exc_pc = { boot_addr_i[31:8], {exc_vec_pc_mux_i}, 2'b0 };
EXC_PC_DBD: exc_pc = { DM_HALT_ADDRESS }; EXC_PC_DBD: exc_pc = { DM_HALT_ADDRESS };
EXC_PC_DBGEXC: exc_pc = { DM_EXCEPTION_ADDRESS }; EXC_PC_DBGEXC: exc_pc = { DM_EXCEPTION_ADDRESS };
// TODO: Add case for EXC_PC_STORE and EXC_PC_LOAD as soon as they are supported // TODO: Add case for EXC_PC_STORE and EXC_PC_LOAD as soon as they are supported