github-mirrors/ibex
1
0
Fork 0
mirror of https://github.com/lowRISC/ibex.git synced 2025-04-23 05:17:12 -04:00
Code Issues Projects Releases Packages Wiki Activity Actions

[dv] Set rdata on write response in sequence not driver

Browse source 
This enables the sequence to corrupt the integrity on write responses
should it choose to.  Previously the driver would always produce correct
integrity.
This commit is contained in:
Greg Chadwick 2022-11-02 11:26:12 +00:00 • committed by Greg Chadwick
parent 2d03fc8b73
commit 4b88ee9571
2 changed files with 9 additions and 5 deletions
Download patch file Download diff file Expand all files Collapse all files

9
dv/uvm/core_ibex/common/ibex_mem_intf_agent/ibex_mem_intf_response_driver.sv
View file

@ -129,11 +129,10 @@ class ibex_mem_intf_response_driver extends uvm_driver #(ibex_mem_intf_seq_item)
end else begin
// rdata and intg fields aren't relevant to write responses
if (cfg.fixed_data_write_response) begin
// when fixed_data_write_response is set, set rdata to fixed value with correct matching
// rintg field.
cfg.vif.response_driver_cb.rdata <= 32'hffffffff;
cfg.vif.response_driver_cb.rintg <=
prim_secded_pkg::prim_secded_inv_39_32_enc(32'hffffffff)[38:32];
// when fixed_data_write_response is set, sequence item is responsible for producing
// fixed values so just copy them across here.
cfg.vif.response_driver_cb.rdata <= tr.data;
cfg.vif.response_driver_cb.rintg <= tr.intg;
end else begin
// when fixed_data_write_response is not set, drive the irrelevant fields to x.
cfg.vif.response_driver_cb.rdata <= 'x;

5
dv/uvm/core_ibex/common/ibex_mem_intf_agent/ibex_mem_intf_response_seq_lib.sv
View file

@ -76,6 +76,11 @@ class ibex_mem_intf_response_seq extends uvm_sequence #(ibex_mem_intf_seq_item);
end else if(item.read_write == WRITE) begin
// Update memory_model
write(aligned_addr, item.data);
if (p_sequencer.cfg.fixed_data_write_response) begin
// When fixed_data_write_response is set drive data in store response to fixed
// 32'hffffffff value. Integrity is calculated below.
req.data = 32'hffffffff;
end
end
// Add integrity bits
{req.intg, req.data} = prim_secded_pkg::prim_secded_inv_39_32_enc(req.data);