Update lowrisc_ip to lowRISC/opentitan@0747afbdd

Update code from upstream repository
https://github.com/lowRISC/opentitan to revision
0747afbddec0ad176980429fe3100b32edb71d4a

* [dv] Enable C/C++ code sourcing with VCS in .core (Canberk Topal)
* [dv/dv_base_reg] Remove duplicated `get_map_by_name` method (Cindy
  Chen)
* [prim] Pulse Sync assertion to check input/output (Eunchan Kim)
* [sparse_fsm_flop] Create flop macro to increase DV coverage (Michael
  Schaffner)
* [dvsim] Make build-randomization opt-in (Srikrishna Iyer)
* [xcelium] Fix compile error (Srikrishna Iyer)
* [dv/cov] fpv_csr_assert only collect assertion coverage (Cindy Chen)
* [dv/jtag] Fix chip_level jtag csr rw failure (Cindy Chen)
* [rtl] Convert some non-ANSI parameters to localparams (Rupert
  Swarbrick)
* [prim] Waive unused parameters for Verilator in prim_generic_otp
  (Rupert Swarbrick)
* [prim] Make a variable widening explicit in prim_present.sv (Rupert
  Swarbrick)
* [prim] Waive some ALWCOMBORDER Verilator warnings in prim_arbiter_*
  (Rupert Swarbrick)
* [prim] Fix Verilator lint warnings in prim_gf_mult.sv (Rupert
  Swarbrick)
* [prim] Make some widening comparisons explicit in prim_clock_*.sv
  (Rupert Swarbrick)
* [prim] Waive unused EnableAlertTriggerSVA for verilator lint (Rupert
  Swarbrick)
* [bazel,dvsim] Add build rules for dvsim.py (Timothy Trippel)
* [prim] Fix a bunch of Verilator lint errors in prim_packer.sv
  (Rupert Swarbrick)
* [prim_sparse_fsm_flop/lint] Move waiver to correct file (Michael
  Schaffner)
* [rv_dm dv] Test drive compile-time seed (Srikrishna Iyer)
* [dvsim] Introduce Verilog compile-time seeds (Srikrishna Iyer)
* [dvsim] Treat `tests: ["N/A"]` as an ignored testpoint (Srikrishna
  Iyer)
* [hw/dv] Removed colon from Questa build and run fail patterns.
  (David Pudner)
* [hw/dv] Code review changes for running questa simulations. (David
  Pudner)
* [hw/dv] Added apache license header to questa_initial_setup.sh.
  (David Pudner)
* [doc/ug] Updated opentitan documentation to include information
  about Questa use. (David Pudner)
* [hw/dv] Added Questa dvsim files (David Pudner)
* [dv/unr] Blackbox common security modules from UNR flow (Cindy Chen)
* [dv] Minor fix to error message in mem_model.sv (Rupert Swarbrick)
* [keymgr] Update keymgr to use prim_edn_req (Timothy Chen)
* [doc] Fix rendering of special characters in testplan table (Rupert
  Swarbrick)
* [dv] enable tlul_assert for csr part2 (Rasmus Madsen)
* [dv] Enable tlul_assert for CSR tests (Weicai Yang)
* [dv] Add valid/ready req/ack coverage for push_pull agent (Weicai
  Yang)
* [dv,verilator] Make multiple sim_ctrl extensions play nicely (Rupert
  Swarbrick)
* [chip dv] Add AST initialization routine (Srikrishna Iyer)
* [top] auto generate (Timothy Chen)
* [reggen] Make field 'qe' behavior consistent (Timothy Chen)
* [prim] IFDEF_CODE waiver in sparsefsm flop (Eunchan Kim)
* [dv] Update checklist for all blocks (Weicai Yang)
* [dv/entropy_src] Temp remove stress_all_with_rand_reset test (Cindy
  Chen)

Signed-off-by: Canberk Topal <ctopal@lowrisc.org>

vendor/lowrisc_ip/dv/sv/dv_base_reg/dv_base_reg_block.sv

@@ -365,11 +365,17 @@ class dv_base_reg_block extends uvm_reg_block;
                                 .map(map));
   endfunction
 
-  // Set default map for this block and all its sub-blocks.
-  function void set_default_map_w_subblks(uvm_reg_map map);
+  // Set default map for this block and all its sub-blocks by name.
+  // This function only works if user is setting default map for all blocks under the hierarchy
+  // with the same map name.
+  function void set_default_map_w_subblks_by_name(string map_name);
     dv_base_reg_block subblks[$];
-    set_default_map(map);
+    uvm_reg_map map = this.get_map_by_name(map_name);
+    `DV_CHECK(map != null)
+    this.set_default_map(map);
+
     get_dv_base_reg_blocks(subblks);
-    foreach (subblks[i]) subblks[i].set_default_map_w_subblks(map);
+    foreach (subblks[i]) subblks[i].set_default_map_w_subblks_by_name(map_name);
   endfunction
+
 endclass

vendor/lowrisc_ip/dv/sv/dv_utils/dv_macros.svh

@@ -534,3 +534,10 @@
     100     :/ 1  \
   };
 `endif
+
+// Enables build-time randomization of fixed design constants.
+//
+// This is meant to be overridden externally by passing `+define+BUILD_SEED=<value>`.
+`ifndef BUILD_SEED
+  `define BUILD_SEED 1
+`endif

vendor/lowrisc_ip/dv/sv/mem_bkdr_util/mem_bkdr_util.sv

@@ -483,11 +483,14 @@ class mem_bkdr_util extends uvm_object;
   endfunction
 
   // load mem from file
-  virtual function void load_mem_from_file(string file);
+  virtual task load_mem_from_file(string file);
     check_file(file, "r");
     this.file = file;
     ->readmemh_event;
-  endfunction
+    // The delay below avoids a race condition between this mem backdoor load and a subsequent
+    // backdoor write to a particular location.
+    #0;
+  endtask
 
   // save mem contents to file
   virtual function void write_mem_to_file(string file);

vendor/lowrisc_ip/dv/sv/mem_model/mem_model.sv

@@ -32,7 +32,7 @@ class mem_model #(int AddrWidth = bus_params_pkg::BUS_AW,
       `uvm_info(`gfn, $sformatf("Read Mem  : Addr[0x%0h], Data[0x%0h]", addr, data), UVM_HIGH)
     end else begin
       `DV_CHECK_STD_RANDOMIZE_FATAL(data)
-      `uvm_error(`gfn, $sformatf("read to uninitialzed addr 0x%0h", addr))
+      `uvm_error(`gfn, $sformatf("read from uninitialized addr 0x%0h", addr))
     end
     return data;
   endfunction

vendor/lowrisc_ip/dv/sv/push_pull_agent/push_pull_agent_cov.sv

@@ -2,6 +2,27 @@
 // Licensed under the Apache License, Version 2.0, see LICENSE for details.
 // SPDX-License-Identifier: Apache-2.0
 
+// coverage for sampling all the combination of valid and ready
+covergroup valid_ready_cg(string name, string path) with function sample(bit valid, bit ready);
+  option.per_instance = 1;
+  option.name         = {path, "::", name};
+
+  cp_valid_ready: coverpoint {valid, ready};
+endgroup : valid_ready_cg
+
+// coverage for sampling all the combination of valid and ready
+covergroup req_ack_cg(string name, string path) with function sample(bit req, bit ack);
+  option.per_instance = 1;
+  option.name         = {path, "::", name};
+
+  // Not a possible combination if this is non-4-phases mode.
+  // But this will happen in the 4 phases req-ack handshake.
+  // In that case, this value has to happen after 2'b11, so no need to sample it
+  cp_req_ack: coverpoint {req, ack} {
+    ignore_bins ack_wo_req = {2'b01};
+  }
+endgroup : req_ack_cg
+
 class push_pull_agent_cov #(parameter int HostDataWidth = 32,
                             parameter int DeviceDataWidth = HostDataWidth)
   extends dv_base_agent_cov #(
@@ -9,15 +30,16 @@ class push_pull_agent_cov #(parameter int HostDataWidth = 32,
 );
 
   `uvm_component_param_utils(push_pull_agent_cov#(HostDataWidth, DeviceDataWidth))
+  `uvm_component_new
 
-  // the base class provides the following handles for use:
-  // push_pull_agent_cfg: cfg
-
-  // covergroups
-
-  function new(string name, uvm_component parent);
-    super.new(name, parent);
-    // instantiate all covergroups here
-  endfunction : new
+  valid_ready_cg m_valid_ready_cg;
+  req_ack_cg m_req_ack_cg;
+  function void build_phase(uvm_phase phase);
+    if (cfg.agent_type == PushAgent) begin
+      m_valid_ready_cg = new("m_valid_ready_cg", `gfn);
+    end else begin
+      m_req_ack_cg = new("m_req_ack_cg", `gfn);
+    end
+  endfunction : build_phase
 
 endclass

vendor/lowrisc_ip/dv/sv/push_pull_agent/push_pull_monitor.sv

@@ -26,6 +26,7 @@ class push_pull_monitor #(parameter int HostDataWidth = 32,
       collect_trans(phase);
       // Collect partial pull reqs for the reactive pull device agent.
       collect_pull_req();
+      collect_cov();
     join_none
   endtask
 
@@ -108,6 +109,22 @@ class push_pull_monitor #(parameter int HostDataWidth = 32,
     end
   endtask
 
+  virtual protected task collect_cov();
+    if (cfg.en_cov) begin
+      if (cfg.agent_type == PushAgent) begin
+        forever @(cfg.vif.mon_cb.ready or cfg.vif.mon_cb.valid) begin
+          `WAIT_FOR_RESET
+          cov.m_valid_ready_cg.sample(cfg.vif.mon_cb.ready, cfg.vif.mon_cb.valid);
+        end // forever
+      end else begin // PullAgent
+        forever @(cfg.vif.mon_cb.req or cfg.vif.mon_cb.ack) begin
+          `WAIT_FOR_RESET
+          cov.m_req_ack_cg.sample(cfg.vif.mon_cb.req, cfg.vif.mon_cb.ack);
+        end // forever
+      end // PushAgent or PullAgent
+    end // cfg.en_cov
+  endtask
+
   `undef WAIT_FOR_RESET
 
   // Creates and writes the item to the analysis_port.

vendor/lowrisc_ip/dv/tools/dvsim/common_modes.hjson

@@ -45,6 +45,27 @@
       is_sim_mode: 1
       en_build_modes: ["{tool}_loopdetect"]
     }
+    // Enables randomization of testbench / RTL build.
+    //
+    // Build randomization is achieved by passing `--build-seed <optional-seed>` on the dvsim
+    // command-line. If not passed, the build is not randomized. Build randomization is achieved
+    // in two ways. One of them is setting the pre-processor macro `BUILD_SEED` to the seed value,
+    // which is done below. The SystemVerilog testbench sources can use the `BUILD_SEED` macro
+    // value to set some design constants (such as parameters) upon instantiation. The `BUILD_SEED`,
+    // if not set externally (by passing the --build-seed switch) is set to 1 in 
+    // `hw/dv/sv/dv_utils/dv_macros.svh`. The other way is by passing the {seed} value to utility 
+    // scripts that generate packages that contain randomized constants. These utility scripts can 
+    // be invoked as a `pre_build_cmd`, wrapped within the `build_seed` sim mode in the DUT 
+    // simulation configuration Hjson file. All forms of build randomization must be wrapped within
+    // this `build_seed` sim mode. They will all use the same {seed} value, which allows us to 
+    // deterministically reproduce failures. The `--build-seed` switch is expected to be passed 
+    // when running the nightly regressions. The `seed` value set by dvsim is a 32-bit unsigned 
+    // integer (unless specified on the command-line).
+    {
+      name: build_seed
+      is_sim_mode: 1
+      build_opts: ["+define+BUILD_SEED={seed}"]
+    }
   ]
 
   run_modes: [

vendor/lowrisc_ip/dv/tools/dvsim/questa.hjson

@@ -0,0 +1,115 @@
+// Copyright lowRISC contributors.
+// Licensed under the Apache License, Version 2.0, see LICENSE for details.
+// SPDX-License-Identifier: Apache-2.0
+{
+  build_cmd:  "{job_prefix} {QUESTA_HOME}/questasim/linux_x86_64/qrun -optimize"
+  run_cmd:    "{job_prefix} {QUESTA_HOME}/questasim/linux_x86_64/qrun -simulate"
+
+
+  build_opts: [ "-timescale 1ns/1ps",
+                "-outdir {build_dir}/qrun.out",
+                "-uvm -uvmhome {QUESTA_HOME}/questasim/verilog_src/uvm-1.2",
+                "-mfcu",
+                "-f {sv_flist}",
+                // List multiple tops for the simulation. Prepend each top level with `-top`.
+                "{eval_cmd} echo {sim_tops} | sed -E 's/(\\S+)/-top \\1/g'",
+                "-voptargs=\"+acc=nr\""
+              ]
+
+  run_opts:   [ "-outdir {build_dir}/qrun.out",
+                "-sv_seed {seed}",
+                // dv_macros.svh has a macro printing null using %0d
+                // format specifier, Questa throws an error on this
+                // we demote this error in Questa
+                "-suppress vsim-8323",
+                // Questa forces all declared virtual interfaces to be allocated,
+                // even in classes that are not even created at runtime. The switch
+                // below demotes the associated error thrown.
+                "-permit_unmatched_virtual_intf",
+                "+UVM_TESTNAME={uvm_test}",
+                "+UVM_TEST_SEQ={uvm_test_seq}",
+                "-do {run_script}"
+              ]
+
+  // Supported wave dumping formats (in order of preference).
+  supported_wave_formats: []
+
+  // Default tcl script used when running the sim. Override if needed.
+  run_script: "{dv_root}/tools/questa/sim.tcl"
+
+  // Coverage related.
+  cov_db_dir: "{scratch_path}/coverage/{build_mode}.ucdb"
+
+  // Individual test specific coverage data - this will be deleted if the test fails
+  // so that coverage from failiing tests is not included in the final report.
+  cov_db_test_dir_name: "{run_dir_name}.{seed}"
+  cov_db_test_dir: "{cov_db_dir}/snps/coverage/db/testdata/{cov_db_test_dir_name}"
+
+  // Merging coverage.
+  // "cov_db_dirs" is a special variable that appends all build directories in use.
+  // It is constructed by the tool itself.
+  cov_merge_dir:    "{scratch_path}/cov_report"
+  cov_merge_db_dir: ""
+  cov_merge_cmd:    ""
+  cov_merge_opts:   []
+
+  // Generate covreage reports in text as well as html.
+  cov_report_dir:       "{scratch_path}/cov_report"
+  cov_report_cmd:       ""
+  cov_report_opts:      []
+  cov_report_txt:   "{cov_report_dir}/dashboard.txt"
+
+  // Analyzing coverage - this is done by invoking --cov-analyze switch. It opens up the
+  // GUI for visual analysis.
+  cov_analyze_dir:  "{scratch_path}/cov_analyze"
+  cov_analyze_cmd:  ""
+  cov_analyze_opts: []
+
+  // By default, collect all coverage metrics.
+  cov_metrics: "bcestf"
+
+  // pass and fail patterns
+  build_fail_patterns: ["^## \\*\\* Error.*$"
+                        "^\\*\\* Error.*$"]
+  run_fail_patterns:   ["^\\*\\* Error.*$"]
+
+  build_modes: [
+   {
+      name: questa_gui
+      is_sim_mode: 1
+      build_opts: []
+      run_opts: ["-gui"]
+    }
+    {
+      name: questa_waves
+      is_sim_mode: 1
+    }
+    // TODO Questa coverage only currently supported in the GUI with no merging
+    {
+      name: questa_cov
+      is_sim_mode: 1
+      build_opts: ["+cover={cov_metrics}"]
+      run_opts:   ["-coverage", "-gui"]
+    }
+    // TODO support profiling for questa
+    {
+      name: questa_profile
+      is_sim_mode: 1
+      build_opts: []
+      run_opts:   []
+    }
+    {
+      name: questa_xprop
+      is_sim_mode: 1
+      build_opts: []
+    }
+    {
+      // TODO: Add build and run options to enable zero delay loop detection.
+      name: questa_loopdetect
+      is_sim_mode: 1
+      build_opts: []
+      run_opts:   []
+    }
+
+  ]
+}

vendor/lowrisc_ip/dv/tools/dvsim/sim.mk

@@ -2,10 +2,11 @@
 # Licensed under the Apache License, Version 2.0, see LICENSE for details.
 # SPDX-License-Identifier: Apache-2.0
 
-export SHELL	:= /bin/bash
+export SHELL  := /bin/bash
 .DEFAULT_GOAL := all
 
-LOCK_SW_BUILD_DIR  ?= flock --timeout 3600 ${sw_build_dir} --command
+LOCK_ROOT_DIR     ?= flock --timeout 3600 ${proj_root} --command
+LOCK_SW_BUILD_DIR ?= flock --timeout 3600 ${sw_build_dir} --command
 
 all: build run
 
@@ -18,7 +19,11 @@ pre_build:
 	@echo "[make]: pre_build"
 	mkdir -p ${build_dir}
 ifneq (${pre_build_cmds},)
-	cd ${build_dir} && ${pre_build_cmds}
+	# pre_build_cmds are likely changing the in-tree sources. We hence use FLOCK
+        # utility to prevent multiple builds that may be running in parallel from
+        # stepping on each other. TODO: Enforce the list of pre_build_cmds is
+        # identical across all build modes.
+	${LOCK_ROOT_DIR} "cd ${build_dir} && ${pre_build_cmds}"
 endif
 
 gen_sv_flist: pre_build

vendor/lowrisc_ip/dv/tools/dvsim/tests/stress_all_test.hjson

@@ -0,0 +1,17 @@
+// Copyright lowRISC contributors.
+// Licensed under the Apache License, Version 2.0, see LICENSE for details.
+// SPDX-License-Identifier: Apache-2.0
+//
+// Different from `stress_tests.hjson`, this hjson only include `stress_all` test to serve as a
+// temporary import for IPs that are at V2 stage and does not support `stress_all_with_rand_reset`
+// sequence.
+{
+  tests: [
+    {
+      name: "{name}_stress_all"
+      uvm_test_seq: "{name}_stress_all_vseq"
+      // 10ms
+      run_opts: ["+test_timeout_ns=10000000000"]
+    }
+  ]
+}

vendor/lowrisc_ip/dv/tools/questa/sim.tcl

@@ -0,0 +1,18 @@
+# Copyright lowRISC contributors.
+# Licensed under the Apache License, Version 2.0, see LICENSE for details.
+# SPDX-License-Identifier: Apache-2.0
+
+
+# Remove leading "# " from the front of log file lines and run the test if not in gui mode.
+# This provides compatibility for log file error checking with other supported simulators within Opentitan.
+set gui 0
+if {[info exists ::env(GUI)]} {
+  set gui "$::env(GUI)"
+}
+
+if {$gui == 0} {
+  set PrefMain(LinePrefix) ""
+  run -all
+} else {
+  set PrefMain(LinePrefix) ""
+}

vendor/lowrisc_ip/dv/tools/vcs/cover.cfg

@@ -15,6 +15,9 @@
 -moduletree prim_esc_receiver
 -moduletree prim_prince // prim_prince is verified in a separate DV environment.
 -moduletree prim_lfsr // prim_lfsr is verified in FPV.
+// csr_assert_fpv is an auto-generated csr read assertion module. So only assertion coverage is
+// meaningful to collect.
+-moduletree *csr_assert_fpv
 
 begin tgl
   -tree tb
@@ -28,6 +31,8 @@ begin tgl
 end
 
 begin assert
+  +moduletree *csr_assert_fpv
+
   // These three assertions in prim_lc_sync and prim_mubi* check when `lc_ctrl_pkg::lc_tx_t` or
   // `mubi*_t` input are neither `On` or `Off`, it is interrupted to the correct `On` or `Off`
   // after one clock cycle. This behavior is implemented outside of IP level design thus these

vendor/lowrisc_ip/dv/tools/vcs/cover_reg_top.cfg

@@ -7,6 +7,7 @@
 
 +moduletree *_reg_top
 +node tb.dut tl_*
++assert tb.dut.tlul_assert*
 
 // Remove everything else from toggle coverage except:
 // - `prim_alert_sender`: the `alert_test` task under `cip_base_vseq` drives `alert_test_i` and

vendor/lowrisc_ip/dv/tools/vcs/unr.cfg

@@ -10,8 +10,8 @@
 # Provide the reset specification: signal_name, active_value, num clk cycles reset to be active
 -reset rst_ni 0 20
 
-# Black box some of the modules
-# -blackBoxes -type design *
+# Black box common security modules
+ -blackBoxes -type design prim_count+prim_spare_fsm+prim_double_lfsr
 
 # Name of the generated exclusion file
 -save_exclusion $SCRATCH_PATH/cov_unr/unr_exclude.el

vendor/lowrisc_ip/dv/tools/xcelium/cover.ccf

@@ -14,6 +14,9 @@ deselect_coverage -betfs -module prim_esc_sender...
 deselect_coverage -betfs -module prim_esc_receiver...
 deselect_coverage -betfs -module prim_prince...
 deselect_coverage -betfs -module prim_lfsr...
+// csr_assert_fpv is an auto-generated csr read assertion module. So only assertion coverage is
+// meaningful to collect.
+deselect_coverage -betf -module *csr_assert_fpv...
 
 // Only collect toggle coverage on the DUT and the black-boxed IP (above) ports.
 deselect_coverage -toggle -module ${DUT_TOP}...

vendor/lowrisc_ip/dv/tools/xcelium/cover_reg_top.ccf

@@ -8,6 +8,7 @@ include_ccf ${dv_root}/tools/xcelium/common.ccf
 // Only collect code coverage on the *_reg_top instance.
 deselect_coverage -betfs -module ${DUT_TOP}...
 select_coverage -befs -module *_reg_top...
+select_coverage -assert -module tlul_assert
 
 // Include toggle coverage on `prim_alert_sender` because the `alert_test` task under
 // `cip_base_vseq` drives `alert_test_i` and verifies `alert_rx/tx` handshake in each IP.

vendor/lowrisc_ip/dv/verilator/cpp/verilator_memutil.cc

@@ -112,7 +112,7 @@ bool VerilatorMemUtil::ParseCLIArguments(int argc, char **argv,
   // some arguments
   optind = 1;
   while (1) {
-    int c = getopt_long(argc, argv, ":r:m:f:l:E:h", long_options, nullptr);
+    int c = getopt_long(argc, argv, "-:r:m:f:l:E:h", long_options, nullptr);
     if (c == -1) {
       break;
     }
@@ -122,6 +122,7 @@ bool VerilatorMemUtil::ParseCLIArguments(int argc, char **argv,
 
     switch (c) {
       case 0:
+      case 1:
         break;
       case 'r':
         load_args.push_back(

vendor/lowrisc_ip/dv/verilator/memutil_dpi.core

@@ -25,3 +25,8 @@ targets:
   default:
     filesets:
       - files_cpp
+    tools:
+      vcs:
+        vcs_options:
+          - '-CFLAGS -I../../src/lowrisc_dv_verilator_memutil_dpi_0/cpp'
+          - '-lelf'

vendor/lowrisc_ip/dv/verilator/memutil_dpi_scrambled.core

@@ -19,3 +19,8 @@ targets:
   default:
     filesets:
       - files_cpp
+    tools:
+      vcs:
+        vcs_options:
+          - '-CFLAGS -I../../src/lowrisc_dv_verilator_memutil_dpi_scrambled_0/cpp'
+          - '-lelf'

vendor/lowrisc_ip/dv/verilator/simutil_verilator/cpp/sim_ctrl_extension.h

@@ -13,6 +13,13 @@ class SimCtrlExtension {
    * Parse command line arguments
    *
    * Process all recognized command-line arguments from argc/argv.
+   * Note that other extensions might also be registered with their
+   * own command line arguments.
+   *
+   * To make this work properly, the extension must only parse options
+   * (no positional arguments) and must leave the ordering of argv
+   * unchanged. In particular, if the code uses getopt_long, it should
+   * pass an optstring argument starting with a '-' character.
    *
    * @param argc, argv Standard C command line arguments
    * @param exit_app Indicate that program should terminate

vendor/lowrisc_ip/dv/verilator/simutil_verilator/cpp/verilator_sim_ctrl.cc

@@ -114,7 +114,7 @@ bool VerilatorSimCtrl::ParseCommandArgs(int argc, char **argv, bool &exit_app) {
       {nullptr, no_argument, nullptr, 0}};
 
   while (1) {
-    int c = getopt_long(argc, argv, ":c:th", long_options, nullptr);
+    int c = getopt_long(argc, argv, "-:c:th", long_options, nullptr);
     if (c == -1) {
       break;
     }
@@ -124,6 +124,7 @@ bool VerilatorSimCtrl::ParseCommandArgs(int argc, char **argv, bool &exit_app) {
 
     switch (c) {
       case 0:
+      case 1:
         break;
       case 't':
         if (!tracing_possible_) {