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update riscvOVPsim.ic for semihosting mode (#681)
Signed-off-by: Udi <udij@google.com>
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@ -17,5 +17,6 @@
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--override riscvOVPsim/cpu/time_undefined=F
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--override riscvOVPsim/cpu/reset_address=0x80000080
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--override riscvOVPsim/cpu/simulateexceptions=T
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--override riscvOVPsim/cpu/defaultsemihost=F
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--override riscvOVPsim/cpu/wfi_is_nop=T
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--override riscvOVPsim/cpu/tval_ii_code=T
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