Update google_riscv-dv to google/riscv-dv@68ab823

Update code from upstream repository https://github.com/google/riscv-
dv to revision 68ab8230c52ec66b393c04394aef4d6082ee53b4

* [pmp] Ensure MML PMP configurations don't dominate. (Greg Chadwick)
* [pmp] Add option to constrain addresses to stay in 32-bit space
  (Greg Chadwick)
* randomizing mstatus.MIE when priv mode is lower than machine (Saad
  Khalid)

Signed-off-by: Greg Chadwick <gac@lowrisc.org>

vendor/google_riscv-dv.lock.hjson

@@ -9,6 +9,6 @@
   upstream:
   {
     url: https://github.com/google/riscv-dv
-    rev: d7c50c1eb9abe85bd6673878fe2e98489cf5f07e
+    rev: 68ab8230c52ec66b393c04394aef4d6082ee53b4
   }
 }

vendor/google_riscv-dv/src/riscv_pmp_cfg.sv

@@ -50,6 +50,14 @@ class riscv_pmp_cfg extends uvm_object;
   // ePMP machine security configuration - RLB, MMWP, MML
   rand mseccfg_reg_t mseccfg = '{1'b1, 1'b0, 1'b0};
 
+  // allow regions that start above 32-bit address space when XLEN == 32
+  rand bit allow_high_addrs;
+
+  // percentage of configs that will allow high address regions. Set low by default as for cores
+  // where physical addresses do not go beyond 32 bits high regions don't do anything interesting
+  // (though you want some to ensure they're handled correctly).
+  int high_addr_proportion = 10;
+
   // pmp CSR configurations
   rand pmp_cfg_reg_t pmp_cfg[];
 
@@ -95,14 +103,27 @@ class riscv_pmp_cfg extends uvm_object;
 
   constraint xwr_c {
     foreach (pmp_cfg[i]) {
+      solve mseccfg.mml before pmp_cfg[i].w, pmp_cfg[i].r;
       !(!mseccfg.mml && pmp_cfg[i].w && !pmp_cfg[i].r);
     }
   }
 
+  constraint allow_high_addrs_c {
+    allow_high_addrs dist { 0 := 100 - high_addr_proportion,
+                            1 := high_addr_proportion };
+    if (XLEN == 64) {
+      allow_high_addrs == 1'b1;
+    }
+  }
+
   constraint address_modes_c {
     foreach (pmp_cfg[i]) {
       pmp_cfg[i].addr_mode >= 0;
-      pmp_cfg[i].addr_mode <= XLEN;
+      if (allow_high_addrs) {
+        pmp_cfg[i].addr_mode <= XLEN;
+      } else {
+        pmp_cfg[i].addr_mode <= XLEN - 3;
+      }
     }
   }
 
@@ -125,6 +146,7 @@ class riscv_pmp_cfg extends uvm_object;
 
   constraint modes_before_addr_c {
     foreach (pmp_cfg[i]) {
+      solve allow_high_addrs before pmp_cfg[i].addr, pmp_cfg[i].addr_mode;
       solve pmp_cfg[i].a before pmp_cfg[i].addr;
       solve pmp_cfg[i].addr_mode before pmp_cfg[i].addr;
     }
@@ -137,6 +159,10 @@ class riscv_pmp_cfg extends uvm_object;
       if (i > 0 && pmp_cfg[i].a == TOR && (!pmp_allow_illegal_tor || pmp_cfg[i].addr_mode > 0)) {
         pmp_cfg[i].addr > pmp_cfg[i-1].addr;
       }
+
+      if (!allow_high_addrs) {
+        pmp_cfg[i].addr[31:29] == '0;
+      }
     }
   }
 
@@ -151,6 +177,20 @@ class riscv_pmp_cfg extends uvm_object;
           // Unless the largest region is selected make sure the bit just before the ones is set to 0.
           (pmp_cfg[i].addr & (1 << pmp_cfg[i].addr_mode)) == 0;
         }
+
+        if (!allow_high_addrs) {
+          pmp_cfg[i].addr[31:29] == '0;
+        }
+      }
+    }
+  }
+
+  constraint addr_na4_mode_c {
+    foreach (pmp_cfg[i]) {
+      if (pmp_cfg[i].a == NA4) {
+        if (!allow_high_addrs) {
+          pmp_cfg[i].addr[31:29] == '0;
+        }
       }
     }
   }

vendor/google_riscv-dv/src/riscv_privileged_common_seq.sv

@@ -20,6 +20,7 @@ class riscv_privileged_common_seq extends uvm_sequence;
   riscv_instr_gen_config  cfg;
   int                     hart;
   riscv_privil_reg        mstatus;
+  rand bit                mstatus_mie;
   riscv_privil_reg        mie;
   riscv_privil_reg        sstatus;
   riscv_privil_reg        sie;
@@ -88,7 +89,12 @@ class riscv_privileged_common_seq extends uvm_sequence;
     mstatus.set_field("MPP", mode);
     mstatus.set_field("SPP", 0);
     // Enable interrupt
-    mstatus.set_field("MPIE", cfg.enable_interrupt);
+    // Only machine mode requires mstatus.MIE to be 1 for enabling interrupt
+    if (mode == MACHINE_MODE) begin
+      mstatus.set_field("MPIE", cfg.enable_interrupt);
+    end else begin
+      mstatus.set_field("MPIE", cfg.enable_interrupt & mstatus_mie);
+    end
     // MIE is set when returning with mret, avoids trapping before returning
     mstatus.set_field("MIE", 0);
     mstatus.set_field("SPIE", cfg.enable_interrupt);