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[dv] Access CPUCTRLSTS and SECURESEED in riscv_rand_instr_test

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Greg Chadwick 2022-10-29 10:47:00 +01:00 • committed by Greg Chadwick
parent cb01156154
commit 4dca23383a
2 changed files with 3 additions and 1 deletions
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2
dv/uvm/core_ibex/riscv_dv_extension/riscv_core_setting.tpl.sv
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@ -131,6 +131,8 @@ const privileged_reg_t implemented_csr[] = {
MTVAL, // Machine bad address or instruction
MIE, // Machine interrupt enable
MIP, // Machine interrupt pending
12'h7c0, // CPU Control and Status (Ibex Specific)
12'h7c1, // Secure Seed (Ibex Specific)
MCYCLE, // Machine cycle counter (lower 32 bits)
MCYCLEH, // Machine cycle counter (upper 32 bits)
//MINSTRET, // Machine instructions retired counter (lower 32 bits)

2
dv/uvm/core_ibex/riscv_dv_extension/testlist.yaml
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@ -36,7 +36,7 @@
+instr_cnt=10000
+num_of_sub_program=5
+gen_all_csrs_by_default=1
+add_csr_write=MSTATUS,MEPC,MCAUSE,MTVAL,0x7c0
+add_csr_write=MSTATUS,MEPC,MCAUSE,MTVAL,0x7c0,0x7c1
+no_csr_instr=0
rtl_test: core_ibex_base_test