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https://github.com/lowRISC/ibex.git
synced 2025-04-22 04:47:25 -04:00
Rework AGU mux for misaligned loads/stores
This operation only depends on the LSU detecting a misaligned address. Previously, the mux control was scattered across ID stage, controller and decoder. With this commit, all the relevant code for this operation is moved into the ID stage and also streamlined.
This commit is contained in:
Pirmin Vogel
parent
71a1ccc08d
commit
5171ee79f0
4 changed files with 51 additions and 70 deletions
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@ -58,7 +58,6 @@ module ibex_controller (
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output ibex_defines::exc_pc_sel_e exc_pc_mux_o, // IF stage selector for exception PC
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// LSU
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input logic data_misaligned_i,
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input logic load_err_i,
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input logic store_err_i,
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@ -98,9 +97,6 @@ module ibex_controller (
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output logic csr_restore_dret_id_o,
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output logic csr_save_cause_o,
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// forwarding signals
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output ibex_defines::op_fw_sel_e operand_a_fw_mux_sel_o, // regfile ra selector for ID stage
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// stall signals
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output logic halt_if_o,
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output logic halt_id_o,
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@ -526,9 +522,6 @@ module ibex_controller (
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// or in case of illegal instruction
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assign deassert_we_o = ~is_decoding_o | illegal_insn_i;
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// Forwarding control unit
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assign operand_a_fw_mux_sel_o = data_misaligned_i ? SEL_MISALIGNED : SEL_REGFILE;
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// update registers
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always_ff @(posedge clk_i or negedge rst_ni) begin : update_regs
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if (!rst_ni) begin
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@ -30,8 +30,6 @@ module ibex_decoder #(
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// singals running to/from controller
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input logic deassert_we_i, // deassert we, we are stalled or
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// not active
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input logic data_misaligned_i, // misaligned data load/store in
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// progress
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input logic branch_mux_i,
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input logic jump_mux_i,
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output logic illegal_insn_o, // illegal instr encountered
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@ -108,8 +106,8 @@ module ibex_decoder #(
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jump_in_id = 1'b0;
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branch_in_id = 1'b0;
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alu_operator_o = ALU_SLTU;
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alu_op_a_mux_sel_o = OP_A_REGA_OR_FWD;
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alu_op_b_mux_sel_o = OP_B_REGB_OR_FWD;
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alu_op_a_mux_sel_o = OP_A_REG_A;
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alu_op_b_mux_sel_o = OP_B_REG_B;
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imm_a_mux_sel_o = IMM_A_ZERO;
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imm_b_mux_sel_o = IMM_B_I;
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@ -160,7 +158,7 @@ module ibex_decoder #(
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// Calculate and store PC+4
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alu_op_a_mux_sel_o = OP_A_CURRPC;
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alu_op_b_mux_sel_o = OP_B_IMM;
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imm_b_mux_sel_o = IMM_B_PCINCR;
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imm_b_mux_sel_o = IMM_B_INCR_PC;
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alu_operator_o = ALU_ADD;
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regfile_we = 1'b1;
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end
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@ -170,7 +168,7 @@ module ibex_decoder #(
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jump_in_id = 1'b1;
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if (jump_mux_i) begin
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// Calculate jump target
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alu_op_a_mux_sel_o = OP_A_REGA_OR_FWD;
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alu_op_a_mux_sel_o = OP_A_REG_A;
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alu_op_b_mux_sel_o = OP_B_IMM;
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imm_b_mux_sel_o = IMM_B_I;
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alu_operator_o = ALU_ADD;
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@ -179,7 +177,7 @@ module ibex_decoder #(
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// Calculate and store PC+4
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alu_op_a_mux_sel_o = OP_A_CURRPC;
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alu_op_b_mux_sel_o = OP_B_IMM;
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imm_b_mux_sel_o = IMM_B_PCINCR;
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imm_b_mux_sel_o = IMM_B_INCR_PC;
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alu_operator_o = ALU_ADD;
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regfile_we = 1'b1;
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end
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@ -270,7 +268,7 @@ module ibex_decoder #(
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// reg-reg load (different encoding)
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if (instr_rdata_i[14:12] == 3'b111) begin
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// offset from RS2
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alu_op_b_mux_sel_o = OP_B_REGB_OR_FWD;
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alu_op_b_mux_sel_o = OP_B_REG_B;
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// sign/zero extension
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data_sign_extension_o = ~instr_rdata_i[30];
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@ -491,7 +489,7 @@ module ibex_decoder #(
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// rs1 field is used as immediate
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alu_op_a_mux_sel_o = OP_A_IMM;
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end else begin
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alu_op_a_mux_sel_o = OP_A_REGA_OR_FWD;
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alu_op_a_mux_sel_o = OP_A_REG_A;
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end
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unique case (instr_rdata_i[13:12])
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@ -525,21 +523,6 @@ module ibex_decoder #(
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if (illegal_c_insn_i) begin
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illegal_insn_o = 1'b1;
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end
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// misaligned access was detected by the LSU
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// TODO: this section should eventually be moved out of the decoder
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if (data_misaligned_i) begin
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// only part of the pipeline is unstalled, make sure that the
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// correct operands are sent to the AGU
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alu_op_a_mux_sel_o = OP_A_REGA_OR_FWD;
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alu_op_b_mux_sel_o = OP_B_IMM;
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imm_b_mux_sel_o = IMM_B_PCINCR;
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// if prepost increments are used, we do not write back the
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// second address since the first calculated address was
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// the correct one
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regfile_we = 1'b0;
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end
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end
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// deassert we signals (in case of stalls)
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@ -122,15 +122,10 @@ typedef enum logic[3:0] {
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// ID stage //
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//////////////
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// Forwarding operand mux selection
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typedef enum logic {
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SEL_REGFILE,
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SEL_MISALIGNED
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} op_fw_sel_e;
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// Operand a selection
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typedef enum logic[1:0] {
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OP_A_REGA_OR_FWD,
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OP_A_REG_A,
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OP_A_FWD,
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OP_A_CURRPC,
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OP_A_IMM
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} op_a_sel_e;
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@ -143,7 +138,7 @@ typedef enum logic {
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// Operand b selection
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typedef enum logic {
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OP_B_REGB_OR_FWD,
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OP_B_REG_B,
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OP_B_IMM
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} op_b_sel_e;
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@ -154,7 +149,8 @@ typedef enum logic [2:0] {
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IMM_B_B,
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IMM_B_U,
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IMM_B_J,
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IMM_B_PCINCR
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IMM_B_INCR_PC,
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IMM_B_INCR_ADDR
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} imm_b_sel_e;
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@ -207,18 +207,18 @@ module ibex_id_stage #(
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logic [4:0] regfile_addr_rb_id;
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logic [4:0] regfile_alu_waddr_id;
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logic regfile_we_id;
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logic regfile_we_id, regfile_we_dec;
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logic [31:0] regfile_data_ra_id;
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logic [31:0] regfile_data_rb_id;
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// ALU Control
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alu_op_e alu_operator;
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op_a_sel_e alu_op_a_mux_sel;
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op_b_sel_e alu_op_b_mux_sel;
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op_a_sel_e alu_op_a_mux_sel, alu_op_a_mux_sel_dec;
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op_b_sel_e alu_op_b_mux_sel, alu_op_b_mux_sel_dec;
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imm_a_sel_e imm_a_mux_sel;
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imm_b_sel_e imm_b_mux_sel;
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imm_b_sel_e imm_b_mux_sel, imm_b_mux_sel_dec;
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// Multiplier Control
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logic mult_int_en; // use integer multiplier
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@ -239,11 +239,9 @@ module ibex_id_stage #(
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csr_op_e csr_op;
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logic csr_status;
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// Forwarding
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op_fw_sel_e operand_a_fw_mux_sel;
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logic [31:0] operand_a_fw_id;
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logic [31:0] operand_b_fw_id;
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// For tracer
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logic [31:0] operand_a_fw_id, unused_operand_a_fw_id;
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logic [31:0] operand_b_fw_id, unused_operand_b_fw_id;
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logic [31:0] alu_operand_a;
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logic [31:0] alu_operand_b;
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@ -282,6 +280,18 @@ module ibex_id_stage #(
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// signal to 0 for instructions that are done
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assign clear_instr_valid_o = id_ready_o | halt_id;
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/////////////
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// LSU Mux //
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/////////////
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// Misaligned loads/stores result in two aligned loads/stores, compute second address
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assign alu_op_a_mux_sel = data_misaligned_i ? OP_A_FWD : alu_op_a_mux_sel_dec;
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assign alu_op_b_mux_sel = data_misaligned_i ? OP_B_IMM : alu_op_b_mux_sel_dec;
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assign imm_b_mux_sel = data_misaligned_i ? IMM_B_INCR_ADDR : imm_b_mux_sel_dec;
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// do not write back the second address since the first calculated address was the correct one
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assign regfile_we_id = data_misaligned_i ? 1'b0 : regfile_we_dec;
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///////////////
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// Operand A //
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///////////////
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@ -289,7 +299,8 @@ module ibex_id_stage #(
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// ALU_Op_a Mux
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always_comb begin : alu_operand_a_mux
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unique case (alu_op_a_mux_sel)
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OP_A_REGA_OR_FWD: alu_operand_a = operand_a_fw_id;
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OP_A_REG_A: alu_operand_a = regfile_data_ra_id;
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OP_A_FWD: alu_operand_a = misaligned_addr_i;
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OP_A_CURRPC: alu_operand_a = pc_id_i;
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OP_A_IMM: alu_operand_a = imm_a;
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default: alu_operand_a = 'X;
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@ -298,10 +309,6 @@ module ibex_id_stage #(
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assign imm_a = (imm_a_mux_sel == IMM_A_Z) ? zimm_rs1_type : '0;
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// Operand a forwarding mux used with LSU instructions
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assign operand_a_fw_id
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= (operand_a_fw_mux_sel == SEL_MISALIGNED) ? misaligned_addr_i : regfile_data_ra_id;
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///////////////
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// Operand B //
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///////////////
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@ -309,20 +316,27 @@ module ibex_id_stage #(
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// Immediate Mux for operand B
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always_comb begin : immediate_b_mux
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unique case (imm_b_mux_sel)
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IMM_B_I: imm_b = imm_i_type;
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IMM_B_S: imm_b = imm_s_type;
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IMM_B_B: imm_b = imm_b_type;
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IMM_B_U: imm_b = imm_u_type;
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IMM_B_J: imm_b = imm_j_type;
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IMM_B_PCINCR: imm_b = (is_compressed_i && !data_misaligned_i) ? 32'h2 : 32'h4;
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default: imm_b = imm_i_type;
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IMM_B_I: imm_b = imm_i_type;
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IMM_B_S: imm_b = imm_s_type;
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IMM_B_B: imm_b = imm_b_type;
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IMM_B_U: imm_b = imm_u_type;
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IMM_B_J: imm_b = imm_j_type;
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IMM_B_INCR_PC: imm_b = is_compressed_i ? 32'h2 : 32'h4;
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IMM_B_INCR_ADDR: imm_b = 32'h4;
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default: imm_b = imm_i_type;
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endcase
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end
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// ALU_Op_b Mux
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assign alu_operand_b = (alu_op_b_mux_sel == OP_B_IMM) ? imm_b : regfile_data_rb_id;
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// Signals used by tracer
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assign operand_a_fw_id = data_misaligned_i ? misaligned_addr_i : regfile_data_ra_id;
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assign operand_b_fw_id = regfile_data_rb_id;
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assign unused_operand_a_fw_id = operand_a_fw_id;
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assign unused_operand_b_fw_id = operand_b_fw_id;
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///////////////
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// Registers //
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///////////////
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@ -382,7 +396,6 @@ module ibex_id_stage #(
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ibex_decoder #( .RV32M ( RV32M ) ) decoder_i (
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// controller related signals
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.deassert_we_i ( deassert_we ),
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.data_misaligned_i ( data_misaligned_i ),
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.branch_mux_i ( branch_mux_dec ),
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.jump_mux_i ( jump_mux_dec ),
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@ -399,18 +412,18 @@ module ibex_id_stage #(
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// ALU signals
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.alu_operator_o ( alu_operator ),
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.alu_op_a_mux_sel_o ( alu_op_a_mux_sel ),
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.alu_op_b_mux_sel_o ( alu_op_b_mux_sel ),
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.alu_op_a_mux_sel_o ( alu_op_a_mux_sel_dec ),
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.alu_op_b_mux_sel_o ( alu_op_b_mux_sel_dec ),
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.imm_a_mux_sel_o ( imm_a_mux_sel ),
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.imm_b_mux_sel_o ( imm_b_mux_sel ),
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.imm_b_mux_sel_o ( imm_b_mux_sel_dec ),
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.mult_int_en_o ( mult_int_en ),
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.div_int_en_o ( div_int_en ),
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.multdiv_operator_o ( multdiv_operator ),
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.multdiv_signed_mode_o ( multdiv_signed_mode ),
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// Register file control signals
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.regfile_we_o ( regfile_we_id ),
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.regfile_we_o ( regfile_we_dec ),
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// CSR control signals
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.csr_access_o ( csr_access ),
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@ -481,7 +494,6 @@ module ibex_id_stage #(
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.exc_cause_o ( exc_cause_o ),
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// LSU
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.data_misaligned_i ( data_misaligned_i ),
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.load_err_i ( lsu_load_err_i ),
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.store_err_i ( lsu_store_err_i ),
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@ -519,9 +531,6 @@ module ibex_id_stage #(
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.debug_single_step_i ( debug_single_step_i ),
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.debug_ebreakm_i ( debug_ebreakm_i ),
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// Forwarding signals
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.operand_a_fw_mux_sel_o ( operand_a_fw_mux_sel ),
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// Stall signals
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.halt_if_o ( halt_if_o ),
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.halt_id_o ( halt_id ),
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