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Fix and rename branch_2nd_stage signal
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parent
567c0c80fd
commit
5173d347cb
3 changed files with 8 additions and 8 deletions
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@ -165,7 +165,7 @@ module riscv_controller
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output logic load_stall_o,
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// CONFIG_REGION: NO_JUMP_ADDER
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`ifdef NO_JUMP_ADDER
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output logic branch_calc_jump_target_o,
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output logic branch_2nd_stage_o,
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`endif
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input logic id_ready_i, // ID stage is ready
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@ -258,7 +258,7 @@ module riscv_controller
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// CONFIG_REGION: NO_JUMP_ADDER
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`ifdef NO_JUMP_ADDER
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branch_calc_jump_target_o = 1'b0;
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branch_2nd_stage_o = 1'b0;
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`endif
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@ -680,7 +680,7 @@ module riscv_controller
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WAIT_BRANCH_EX:
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begin
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// there is a branch in the EX stage that is taken
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branch_calc_jump_target_o = 1'b1;
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branch_2nd_stage_o = 1'b1;
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halt_if_o = 1'b1;
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if (id_ready_i)
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begin
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@ -43,7 +43,7 @@ module riscv_decoder
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`endif // ONLY_ALIGNED
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// CONFIG_REGION: NO_JUMP_ADDER
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`ifdef NO_JUMP_ADDER
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input logic branch_stall_i,
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input logic branch_2nd_stage_i,
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`endif
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// CONFIG_REGION: MUL_SUPPORT
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`ifdef MUL_SUPPORT
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@ -372,7 +372,7 @@ module riscv_decoder
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rega_used_o = 1'b1;
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regb_used_o = 1'b1;
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if (~branch_stall_i)
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if (~branch_2nd_stage_i)
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begin
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unique case (instr_rdata_i[14:12])
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3'b000: alu_operator_o = ALU_EQ;
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@ -311,7 +311,7 @@ module riscv_id_stage
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`endif
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// CONFIG_REGION: NO_JUMP_ADDER
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`ifdef NO_JUMP_ADDER
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logic branch_calc_jump_target;
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logic branch_2nd_stage;
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`endif
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logic jr_stall;
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logic load_stall;
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@ -1109,7 +1109,7 @@ module riscv_id_stage
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`endif // ONLY_ALIGNED
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// CONFIG_REGION: NO_JUMP_ADDER
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`ifdef NO_JUMP_ADDER
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.branch_calc_jump_target_i ( branch_calc_jump_target ),
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.branch_2nd_stage_i ( branch_2nd_stage ),
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`endif
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// CONFIG_REGION: MUL_SUPPORT
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`ifdef MUL_SUPPORT
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@ -1353,7 +1353,7 @@ module riscv_id_stage
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`endif // ONLY_ALIGNED
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// CONFIG_REGION: NO_JUMP_ADDER
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`ifdef NO_JUMP_ADDER
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.branch_calc_jump_target_o ( branch_calc_jump_target ),
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.branch_2nd_stage_o ( branch_2nd_stage),
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`endif
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.jr_stall_o ( jr_stall ),
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.load_stall_o ( load_stall ),
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