Fix and rename branch_2nd_stage signal

This commit is contained in:
Markus Wegmann 2017-01-09 21:21:08 +01:00
parent 567c0c80fd
commit 5173d347cb
3 changed files with 8 additions and 8 deletions

View file

@ -165,7 +165,7 @@ module riscv_controller
output logic load_stall_o,
// CONFIG_REGION: NO_JUMP_ADDER
`ifdef NO_JUMP_ADDER
output logic branch_calc_jump_target_o,
output logic branch_2nd_stage_o,
`endif
input logic id_ready_i, // ID stage is ready
@ -258,7 +258,7 @@ module riscv_controller
// CONFIG_REGION: NO_JUMP_ADDER
`ifdef NO_JUMP_ADDER
branch_calc_jump_target_o = 1'b0;
branch_2nd_stage_o = 1'b0;
`endif
@ -680,7 +680,7 @@ module riscv_controller
WAIT_BRANCH_EX:
begin
// there is a branch in the EX stage that is taken
branch_calc_jump_target_o = 1'b1;
branch_2nd_stage_o = 1'b1;
halt_if_o = 1'b1;
if (id_ready_i)
begin

View file

@ -43,7 +43,7 @@ module riscv_decoder
`endif // ONLY_ALIGNED
// CONFIG_REGION: NO_JUMP_ADDER
`ifdef NO_JUMP_ADDER
input logic branch_stall_i,
input logic branch_2nd_stage_i,
`endif
// CONFIG_REGION: MUL_SUPPORT
`ifdef MUL_SUPPORT
@ -372,7 +372,7 @@ module riscv_decoder
rega_used_o = 1'b1;
regb_used_o = 1'b1;
if (~branch_stall_i)
if (~branch_2nd_stage_i)
begin
unique case (instr_rdata_i[14:12])
3'b000: alu_operator_o = ALU_EQ;

View file

@ -311,7 +311,7 @@ module riscv_id_stage
`endif
// CONFIG_REGION: NO_JUMP_ADDER
`ifdef NO_JUMP_ADDER
logic branch_calc_jump_target;
logic branch_2nd_stage;
`endif
logic jr_stall;
logic load_stall;
@ -1109,7 +1109,7 @@ module riscv_id_stage
`endif // ONLY_ALIGNED
// CONFIG_REGION: NO_JUMP_ADDER
`ifdef NO_JUMP_ADDER
.branch_calc_jump_target_i ( branch_calc_jump_target ),
.branch_2nd_stage_i ( branch_2nd_stage ),
`endif
// CONFIG_REGION: MUL_SUPPORT
`ifdef MUL_SUPPORT
@ -1353,7 +1353,7 @@ module riscv_id_stage
`endif // ONLY_ALIGNED
// CONFIG_REGION: NO_JUMP_ADDER
`ifdef NO_JUMP_ADDER
.branch_calc_jump_target_o ( branch_calc_jump_target ),
.branch_2nd_stage_o ( branch_2nd_stage),
`endif
.jr_stall_o ( jr_stall ),
.load_stall_o ( load_stall ),