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excluding some not useful at the moment large files

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Saad Khalid 2023-02-02 10:30:02 +00:00 • committed by Greg Chadwick
parent b3733f9a05
commit 539316365f
868 changed files with 6 additions and 8706855 deletions
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vendor/riscv-arch-tests/riscv-test-suite/rv32i_m/D/src/fadd.d_b1-01.S vendored
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vendor/riscv-arch-tests/riscv-test-suite/rv32i_m/D/src/fadd.d_b10-01.S vendored
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vendor/riscv-arch-tests/riscv-test-suite/rv32i_m/D/src/fadd.d_b11-01.S vendored
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vendor/riscv-arch-tests/riscv-test-suite/rv32i_m/D/src/fadd.d_b12-01.S vendored
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// -----------
// This file was generated by riscv_ctg (https://github.com/riscv-software-src/riscv-ctg)
// version : 0.7.1
// timestamp : Fri Jun 17 14:04:18 2022 GMT
// usage : riscv_ctg \
// -- cgf // --cgf /scratch/pawan/work/normalised/RV32D/fadd.d.cgf \
\
// -- xlen 32 \
// --randomize \
// -----------
//
// -----------
// Copyright (c) 2020. RISC-V International. All rights reserved.
// SPDX-License-Identifier: BSD-3-Clause
// -----------
//
// This assembly file tests the fadd.d instruction of the RISC-V RV32FD_Zicsr,RV64FD_Zicsr extension for the fadd.d_b12 covergroup.
//
#include "model_test.h"
#include "arch_test.h"
RVTEST_ISA("RV32IFD_Zicsr,RV64IFD_Zicsr")
.section .text.init
.org 0x80
.globl rvtest_entry_point
rvtest_entry_point:
RVMODEL_BOOT
RVTEST_CODE_BEGIN
#ifdef TEST_CASE_1
RVTEST_CASE(0,"//check ISA:=regex(.*I.*D.*);def TEST_CASE_1=True;",fadd.d_b12)
RVTEST_FP_ENABLE()
RVTEST_VALBASEUPD(x3,test_dataset_0)
RVTEST_SIGBASE(x1,signature_x1_1)
inst_0:
// rs1 == rs2 == rd, rs1==f26, rs2==f26, rd==f26,fs1 == 1 and fe1 == 0x7f5 and fm1 == 0x2b954e52a4bff and fs2 == 0 and fe2 == 0x7fd and fm2 == 0xfa980f38509ed and fcsr == 0x0 and rm_val == 7
/* opcode: fadd.d ; op1:f26; op2:f26; dest:f26; op1val:0xff52b954e52a4bff; op2val:0xff52b954e52a4bff;
valaddr_reg:x3; val_offset:0*FLEN/8; rmval:dyn; fcsr: 0;
correctval:??; testreg:x2
*/
TEST_FPRR_OP(fadd.d, f26, f26, f26, dyn, 0, 0, x3, 0*FLEN/8, x4, x1, x2)
inst_1:
// rs2 == rd != rs1, rs1==f21, rs2==f3, rd==f3,fs1 == 1 and fe1 == 0x7fb and fm1 == 0x49818dfc8788f and fs2 == 0 and fe2 == 0x7fd and fm2 == 0x9a1cc86f24be5 and fcsr == 0x0 and rm_val == 7
/* opcode: fadd.d ; op1:f21; op2:f3; dest:f3; op1val:0xffb49818dfc8788f; op2val:0x7fd9a1cc86f24be5;
valaddr_reg:x3; val_offset:2*FLEN/8; rmval:dyn; fcsr: 0;
correctval:??; testreg:x2
*/
TEST_FPRR_OP(fadd.d, f3, f21, f3, dyn, 0, 0, x3, 2*FLEN/8, x4, x1, x2)
inst_2:
// rs1 == rs2 != rd, rs1==f13, rs2==f13, rd==f22,fs1 == 1 and fe1 == 0x7fb and fm1 == 0xbeb3709a573b7 and fs2 == 0 and fe2 == 0x7fe and fm2 == 0x52162165ec222 and fcsr == 0x0 and rm_val == 7
/* opcode: fadd.d ; op1:f13; op2:f13; dest:f22; op1val:0xffbbeb3709a573b7; op2val:0xffbbeb3709a573b7;
valaddr_reg:x3; val_offset:4*FLEN/8; rmval:dyn; fcsr: 0;
correctval:??; testreg:x2
*/
TEST_FPRR_OP(fadd.d, f22, f13, f13, dyn, 0, 0, x3, 4*FLEN/8, x4, x1, x2)
inst_3:
// rs1 != rs2 and rs1 != rd and rs2 != rd, rs1==f27, rs2==f30, rd==f8,fs1 == 1 and fe1 == 0x7fc and fm1 == 0x83df99d24bacb and fs2 == 0 and fe2 == 0x7fd and fm2 == 0x8125d36d5e46f and fcsr == 0x0 and rm_val == 7
/* opcode: fadd.d ; op1:f27; op2:f30; dest:f8; op1val:0xffc83df99d24bacb; op2val:0x7fd8125d36d5e46f;
valaddr_reg:x3; val_offset:6*FLEN/8; rmval:dyn; fcsr: 0;
correctval:??; testreg:x2
*/
TEST_FPRR_OP(fadd.d, f8, f27, f30, dyn, 0, 0, x3, 6*FLEN/8, x4, x1, x2)
inst_4:
// rs1 == rd != rs2, rs1==f14, rs2==f12, rd==f14,fs1 == 1 and fe1 == 0x7fc and fm1 == 0x874e2eeac1c13 and fs2 == 0 and fe2 == 0x7fe and fm2 == 0x84645048e0d5c and fcsr == 0x0 and rm_val == 7
/* opcode: fadd.d ; op1:f14; op2:f12; dest:f14; op1val:0xffc874e2eeac1c13; op2val:0x7fe84645048e0d5c;
valaddr_reg:x3; val_offset:8*FLEN/8; rmval:dyn; fcsr: 0;
correctval:??; testreg:x2
*/
TEST_FPRR_OP(fadd.d, f14, f14, f12, dyn, 0, 0, x3, 8*FLEN/8, x4, x1, x2)
inst_5:
// rs1==f1, rs2==f24, rd==f17,fs1 == 1 and fe1 == 0x7fc and fm1 == 0xe8af77cda8053 and fs2 == 0 and fe2 == 0x7ff and fm2 == 0x0000000000000 and fcsr == 0x0 and rm_val == 7
/* opcode: fadd.d ; op1:f1; op2:f24; dest:f17; op1val:0xffce8af77cda8053; op2val:0x7ff0000000000000;
valaddr_reg:x3; val_offset:10*FLEN/8; rmval:dyn; fcsr: 0;
correctval:??; testreg:x2
*/
TEST_FPRR_OP(fadd.d, f17, f1, f24, dyn, 0, 0, x3, 10*FLEN/8, x4, x1, x2)
inst_6:
// rs1==f22, rs2==f6, rd==f9,fs1 == 1 and fe1 == 0x7fd and fm1 == 0x0abe7f07f8c6f and fs2 == 0 and fe2 == 0x7ff and fm2 == 0x0000000000000 and fcsr == 0x0 and rm_val == 7
/* opcode: fadd.d ; op1:f22; op2:f6; dest:f9; op1val:0xffd0abe7f07f8c6f; op2val:0x7ff0000000000000;
valaddr_reg:x3; val_offset:12*FLEN/8; rmval:dyn; fcsr: 0;
correctval:??; testreg:x2
*/
TEST_FPRR_OP(fadd.d, f9, f22, f6, dyn, 0, 0, x3, 12*FLEN/8, x4, x1, x2)
inst_7:
// rs1==f6, rs2==f15, rd==f11,fs1 == 1 and fe1 == 0x7fd and fm1 == 0x209a1991e3307 and fs2 == 0 and fe2 == 0x7ff and fm2 == 0x0000000000000 and fcsr == 0x0 and rm_val == 7
/* opcode: fadd.d ; op1:f6; op2:f15; dest:f11; op1val:0xffd209a1991e3307; op2val:0x7ff0000000000000;
valaddr_reg:x3; val_offset:14*FLEN/8; rmval:dyn; fcsr: 0;
correctval:??; testreg:x2
*/
TEST_FPRR_OP(fadd.d, f11, f6, f15, dyn, 0, 0, x3, 14*FLEN/8, x4, x1, x2)
inst_8:
// rs1==f29, rs2==f21, rd==f24,fs1 == 1 and fe1 == 0x7fd and fm1 == 0x3d97530ca446d and fs2 == 0 and fe2 == 0x7ff and fm2 == 0x0000000000000 and fcsr == 0x0 and rm_val == 7
/* opcode: fadd.d ; op1:f29; op2:f21; dest:f24; op1val:0xffd3d97530ca446d; op2val:0x7ff0000000000000;
valaddr_reg:x3; val_offset:16*FLEN/8; rmval:dyn; fcsr: 0;
correctval:??; testreg:x2
*/
TEST_FPRR_OP(fadd.d, f24, f29, f21, dyn, 0, 0, x3, 16*FLEN/8, x4, x1, x2)
inst_9:
// rs1==f25, rs2==f18, rd==f27,fs1 == 1 and fe1 == 0x7fd and fm1 == 0x4d025f5a10f55 and fs2 == 0 and fe2 == 0x7ff and fm2 == 0x0000000000000 and fcsr == 0x0 and rm_val == 7
/* opcode: fadd.d ; op1:f25; op2:f18; dest:f27; op1val:0xffd4d025f5a10f55; op2val:0x7ff0000000000000;
valaddr_reg:x3; val_offset:18*FLEN/8; rmval:dyn; fcsr: 0;
correctval:??; testreg:x2
*/
TEST_FPRR_OP(fadd.d, f27, f25, f18, dyn, 0, 0, x3, 18*FLEN/8, x4, x1, x2)
inst_10:
// rs1==f2, rs2==f7, rd==f29,fs1 == 1 and fe1 == 0x7fd and fm1 == 0xaeaa51052e977 and fs2 == 0 and fe2 == 0x7fe and fm2 == 0x5be5e5006178e and fcsr == 0x0 and rm_val == 7
/* opcode: fadd.d ; op1:f2; op2:f7; dest:f29; op1val:0xffdaeaa51052e977; op2val:0x7fe5be5e5006178e;
valaddr_reg:x3; val_offset:20*FLEN/8; rmval:dyn; fcsr: 0;
correctval:??; testreg:x2
*/
TEST_FPRR_OP(fadd.d, f29, f2, f7, dyn, 0, 0, x3, 20*FLEN/8, x4, x1, x2)
inst_11:
// rs1==f16, rs2==f27, rd==f18,fs1 == 1 and fe1 == 0x7fd and fm1 == 0xbc978aa879221 and fs2 == 0 and fe2 == 0x7ff and fm2 == 0x0000000000000 and fcsr == 0x0 and rm_val == 7
/* opcode: fadd.d ; op1:f16; op2:f27; dest:f18; op1val:0xffdbc978aa879221; op2val:0x7ff0000000000000;
valaddr_reg:x3; val_offset:22*FLEN/8; rmval:dyn; fcsr: 0;
correctval:??; testreg:x2
*/
TEST_FPRR_OP(fadd.d, f18, f16, f27, dyn, 0, 0, x3, 22*FLEN/8, x4, x1, x2)
inst_12:
// rs1==f10, rs2==f19, rd==f15,fs1 == 1 and fe1 == 0x7fd and fm1 == 0xcd606a3f0f54d and fs2 == 0 and fe2 == 0x7ff and fm2 == 0x0000000000000 and fcsr == 0x0 and rm_val == 7
/* opcode: fadd.d ; op1:f10; op2:f19; dest:f15; op1val:0xffdcd606a3f0f54d; op2val:0x7ff0000000000000;
valaddr_reg:x3; val_offset:24*FLEN/8; rmval:dyn; fcsr: 0;
correctval:??; testreg:x2
*/
TEST_FPRR_OP(fadd.d, f15, f10, f19, dyn, 0, 0, x3, 24*FLEN/8, x4, x1, x2)
inst_13:
// rs1==f5, rs2==f31, rd==f28,fs1 == 1 and fe1 == 0x7fd and fm1 == 0xe3796147a7f97 and fs2 == 0 and fe2 == 0x7fe and fm2 == 0x254bcc7a78811 and fcsr == 0x0 and rm_val == 7
/* opcode: fadd.d ; op1:f5; op2:f31; dest:f28; op1val:0xffde3796147a7f97; op2val:0x7fe254bcc7a78811;
valaddr_reg:x3; val_offset:26*FLEN/8; rmval:dyn; fcsr: 0;
correctval:??; testreg:x2
*/
TEST_FPRR_OP(fadd.d, f28, f5, f31, dyn, 0, 0, x3, 26*FLEN/8, x4, x1, x2)
inst_14:
// rs1==f28, rs2==f8, rd==f0,fs1 == 1 and fe1 == 0x7fd and fm1 == 0xe7f7bd88d7c8f and fs2 == 0 and fe2 == 0x7fe and fm2 == 0x21f9542fdc1b0 and fcsr == 0x0 and rm_val == 7
/* opcode: fadd.d ; op1:f28; op2:f8; dest:f0; op1val:0xffde7f7bd88d7c8f; op2val:0x7fe21f9542fdc1b0;
valaddr_reg:x3; val_offset:28*FLEN/8; rmval:dyn; fcsr: 0;
correctval:??; testreg:x2
*/
TEST_FPRR_OP(fadd.d, f0, f28, f8, dyn, 0, 0, x3, 28*FLEN/8, x4, x1, x2)
inst_15:
// rs1==f23, rs2==f2, rd==f12,fs1 == 1 and fe1 == 0x7fd and fm1 == 0xe809082dd48fb and fs2 == 0 and fe2 == 0x7ff and fm2 == 0x0000000000000 and fcsr == 0x0 and rm_val == 7
/* opcode: fadd.d ; op1:f23; op2:f2; dest:f12; op1val:0xffde809082dd48fb; op2val:0x7ff0000000000000;
valaddr_reg:x3; val_offset:30*FLEN/8; rmval:dyn; fcsr: 0;
correctval:??; testreg:x2
*/
TEST_FPRR_OP(fadd.d, f12, f23, f2, dyn, 0, 0, x3, 30*FLEN/8, x4, x1, x2)
inst_16:
// rs1==f12, rs2==f25, rd==f10,fs1 == 1 and fe1 == 0x7fd and fm1 == 0xe8754038aa2cf and fs2 == 0 and fe2 == 0x7ff and fm2 == 0x0000000000000 and fcsr == 0x0 and rm_val == 7
/* opcode: fadd.d ; op1:f12; op2:f25; dest:f10; op1val:0xffde8754038aa2cf; op2val:0x7ff0000000000000;
valaddr_reg:x3; val_offset:32*FLEN/8; rmval:dyn; fcsr: 0;
correctval:??; testreg:x2
*/
TEST_FPRR_OP(fadd.d, f10, f12, f25, dyn, 0, 0, x3, 32*FLEN/8, x4, x1, x2)
inst_17:
// rs1==f4, rs2==f11, rd==f30,fs1 == 1 and fe1 == 0x7fe and fm1 == 0x0410cbbfdec45 and fs2 == 0 and fe2 == 0x7ff and fm2 == 0x0000000000000 and fcsr == 0x0 and rm_val == 7
/* opcode: fadd.d ; op1:f4; op2:f11; dest:f30; op1val:0xffe0410cbbfdec45; op2val:0x7ff0000000000000;
valaddr_reg:x3; val_offset:34*FLEN/8; rmval:dyn; fcsr: 0;
correctval:??; testreg:x2
*/
TEST_FPRR_OP(fadd.d, f30, f4, f11, dyn, 0, 0, x3, 34*FLEN/8, x4, x1, x2)
inst_18:
// rs1==f3, rs2==f5, rd==f21,fs1 == 1 and fe1 == 0x7fe and fm1 == 0x05c5ccdf19706 and fs2 == 0 and fe2 == 0x7fe and fm2 == 0xd51953d9ddca4 and fcsr == 0x0 and rm_val == 7
/* opcode: fadd.d ; op1:f3; op2:f5; dest:f21; op1val:0xffe05c5ccdf19706; op2val:0x7fed51953d9ddca4;
valaddr_reg:x3; val_offset:36*FLEN/8; rmval:dyn; fcsr: 0;
correctval:??; testreg:x2
*/
TEST_FPRR_OP(fadd.d, f21, f3, f5, dyn, 0, 0, x3, 36*FLEN/8, x4, x1, x2)
inst_19:
// rs1==f11, rs2==f9, rd==f6,fs1 == 1 and fe1 == 0x7fe and fm1 == 0x14c9836bbe6ff and fs2 == 0 and fe2 == 0x7fe and fm2 == 0xdd2178215e056 and fcsr == 0x0 and rm_val == 7
/* opcode: fadd.d ; op1:f11; op2:f9; dest:f6; op1val:0xffe14c9836bbe6ff; op2val:0x7fedd2178215e056;
valaddr_reg:x3; val_offset:38*FLEN/8; rmval:dyn; fcsr: 0;
correctval:??; testreg:x2
*/
TEST_FPRR_OP(fadd.d, f6, f11, f9, dyn, 0, 0, x3, 38*FLEN/8, x4, x1, x2)
inst_20:
// rs1==f0, rs2==f4, rd==f31,fs1 == 1 and fe1 == 0x7fe and fm1 == 0x18ef1d7a9fa74 and fs2 == 0 and fe2 == 0x7fe and fm2 == 0x201f96c097d1c and fcsr == 0x0 and rm_val == 7
/* opcode: fadd.d ; op1:f0; op2:f4; dest:f31; op1val:0xffe18ef1d7a9fa74; op2val:0x7fe201f96c097d1c;
valaddr_reg:x3; val_offset:40*FLEN/8; rmval:dyn; fcsr: 0;
correctval:??; testreg:x2
*/
TEST_FPRR_OP(fadd.d, f31, f0, f4, dyn, 0, 0, x3, 40*FLEN/8, x4, x1, x2)
inst_21:
// rs1==f20, rs2==f17, rd==f13,fs1 == 1 and fe1 == 0x7fe and fm1 == 0x26bbbacf7eaef and fs2 == 0 and fe2 == 0x7fe and fm2 == 0xbb61cc5b43304 and fcsr == 0x0 and rm_val == 7
/* opcode: fadd.d ; op1:f20; op2:f17; dest:f13; op1val:0xffe26bbbacf7eaef; op2val:0x7febb61cc5b43304;
valaddr_reg:x3; val_offset:42*FLEN/8; rmval:dyn; fcsr: 0;
correctval:??; testreg:x2
*/
TEST_FPRR_OP(fadd.d, f13, f20, f17, dyn, 0, 0, x3, 42*FLEN/8, x4, x1, x2)
inst_22:
// rs1==f19, rs2==f10, rd==f25,fs1 == 1 and fe1 == 0x7fe and fm1 == 0x2cdc24d268f9f and fs2 == 0 and fe2 == 0x7ff and fm2 == 0x0000000000000 and fcsr == 0x0 and rm_val == 7
/* opcode: fadd.d ; op1:f19; op2:f10; dest:f25; op1val:0xffe2cdc24d268f9f; op2val:0x7ff0000000000000;
valaddr_reg:x3; val_offset:44*FLEN/8; rmval:dyn; fcsr: 0;
correctval:??; testreg:x2
*/
TEST_FPRR_OP(fadd.d, f25, f19, f10, dyn, 0, 0, x3, 44*FLEN/8, x4, x1, x2)
inst_23:
// rs1==f24, rs2==f20, rd==f16,fs1 == 1 and fe1 == 0x7fe and fm1 == 0x314c82f3115df and fs2 == 0 and fe2 == 0x7fe and fm2 == 0xf65e46475bdcb and fcsr == 0x0 and rm_val == 7
/* opcode: fadd.d ; op1:f24; op2:f20; dest:f16; op1val:0xffe314c82f3115df; op2val:0x7fef65e46475bdcb;
valaddr_reg:x3; val_offset:46*FLEN/8; rmval:dyn; fcsr: 0;
correctval:??; testreg:x2
*/
TEST_FPRR_OP(fadd.d, f16, f24, f20, dyn, 0, 0, x3, 46*FLEN/8, x4, x1, x2)
inst_24:
// rs1==f18, rs2==f1, rd==f23,fs1 == 1 and fe1 == 0x7fe and fm1 == 0x39bd67fecd9d5 and fs2 == 0 and fe2 == 0x7ff and fm2 == 0x0000000000000 and fcsr == 0x0 and rm_val == 7
/* opcode: fadd.d ; op1:f18; op2:f1; dest:f23; op1val:0xffe39bd67fecd9d5; op2val:0x7ff0000000000000;
valaddr_reg:x3; val_offset:48*FLEN/8; rmval:dyn; fcsr: 0;
correctval:??; testreg:x2
*/
TEST_FPRR_OP(fadd.d, f23, f18, f1, dyn, 0, 0, x3, 48*FLEN/8, x4, x1, x2)
inst_25:
// rs1==f30, rs2==f23, rd==f2,fs1 == 1 and fe1 == 0x7fe and fm1 == 0x39beb50761e3d and fs2 == 0 and fe2 == 0x7ff and fm2 == 0x0000000000000 and fcsr == 0x0 and rm_val == 7
/* opcode: fadd.d ; op1:f30; op2:f23; dest:f2; op1val:0xffe39beb50761e3d; op2val:0x7ff0000000000000;
valaddr_reg:x3; val_offset:50*FLEN/8; rmval:dyn; fcsr: 0;
correctval:??; testreg:x2
*/
TEST_FPRR_OP(fadd.d, f2, f30, f23, dyn, 0, 0, x3, 50*FLEN/8, x4, x1, x2)
inst_26:
// rs1==f9, rs2==f29, rd==f5,fs1 == 1 and fe1 == 0x7fe and fm1 == 0x3c9adc7329695 and fs2 == 0 and fe2 == 0x7fe and fm2 == 0xbcdd3a7258aa7 and fcsr == 0x0 and rm_val == 7
/* opcode: fadd.d ; op1:f9; op2:f29; dest:f5; op1val:0xffe3c9adc7329695; op2val:0x7febcdd3a7258aa7;
valaddr_reg:x3; val_offset:52*FLEN/8; rmval:dyn; fcsr: 0;
correctval:??; testreg:x2
*/
TEST_FPRR_OP(fadd.d, f5, f9, f29, dyn, 0, 0, x3, 52*FLEN/8, x4, x1, x2)
inst_27:
// rs1==f31, rs2==f16, rd==f1,fs1 == 1 and fe1 == 0x7fe and fm1 == 0x691ae7e1929e8 and fs2 == 0 and fe2 == 0x7fe and fm2 == 0xf63ad242f7a0b and fcsr == 0x0 and rm_val == 7
/* opcode: fadd.d ; op1:f31; op2:f16; dest:f1; op1val:0xffe691ae7e1929e8; op2val:0x7fef63ad242f7a0b;
valaddr_reg:x3; val_offset:54*FLEN/8; rmval:dyn; fcsr: 0;
correctval:??; testreg:x2
*/
TEST_FPRR_OP(fadd.d, f1, f31, f16, dyn, 0, 0, x3, 54*FLEN/8, x4, x1, x2)
inst_28:
// rs1==f8, rs2==f14, rd==f7,fs1 == 1 and fe1 == 0x7fe and fm1 == 0x69c26ac7fce60 and fs2 == 0 and fe2 == 0x7ff and fm2 == 0x0000000000000 and fcsr == 0x0 and rm_val == 7
/* opcode: fadd.d ; op1:f8; op2:f14; dest:f7; op1val:0xffe69c26ac7fce60; op2val:0x7ff0000000000000;
valaddr_reg:x3; val_offset:56*FLEN/8; rmval:dyn; fcsr: 0;
correctval:??; testreg:x2
*/
TEST_FPRR_OP(fadd.d, f7, f8, f14, dyn, 0, 0, x3, 56*FLEN/8, x4, x1, x2)
inst_29:
// rs1==f17, rs2==f22, rd==f19,fs1 == 1 and fe1 == 0x7fe and fm1 == 0x707d21f5c40de and fs2 == 0 and fe2 == 0x7ff and fm2 == 0x0000000000000 and fcsr == 0x0 and rm_val == 7
/* opcode: fadd.d ; op1:f17; op2:f22; dest:f19; op1val:0xffe707d21f5c40de; op2val:0x7ff0000000000000;
valaddr_reg:x3; val_offset:58*FLEN/8; rmval:dyn; fcsr: 0;
correctval:??; testreg:x2
*/
TEST_FPRR_OP(fadd.d, f19, f17, f22, dyn, 0, 0, x3, 58*FLEN/8, x4, x1, x2)
inst_30:
// rs1==f7, rs2==f28, rd==f20,fs1 == 1 and fe1 == 0x7fe and fm1 == 0x83e4a9485598d and fs2 == 0 and fe2 == 0x7ff and fm2 == 0x0000000000000 and fcsr == 0x0 and rm_val == 7
/* opcode: fadd.d ; op1:f7; op2:f28; dest:f20; op1val:0xffe83e4a9485598d; op2val:0x7ff0000000000000;
valaddr_reg:x3; val_offset:60*FLEN/8; rmval:dyn; fcsr: 0;
correctval:??; testreg:x2
*/
TEST_FPRR_OP(fadd.d, f20, f7, f28, dyn, 0, 0, x3, 60*FLEN/8, x4, x1, x2)
inst_31:
// rs1==f15, rs2==f0, rd==f4,fs1 == 1 and fe1 == 0x7fe and fm1 == 0x914e0c751c4f4 and fs2 == 0 and fe2 == 0x7ff and fm2 == 0x0000000000000 and fcsr == 0x0 and rm_val == 7
/* opcode: fadd.d ; op1:f15; op2:f0; dest:f4; op1val:0xffe914e0c751c4f4; op2val:0x7ff0000000000000;
valaddr_reg:x3; val_offset:62*FLEN/8; rmval:dyn; fcsr: 0;
correctval:??; testreg:x2
*/
TEST_FPRR_OP(fadd.d, f4, f15, f0, dyn, 0, 0, x3, 62*FLEN/8, x4, x1, x2)
inst_32:
// fs1 == 1 and fe1 == 0x7fe and fm1 == 0x962eb496df1c1 and fs2 == 0 and fe2 == 0x7fe and fm2 == 0xc05b7f6ba0d90 and fcsr == 0x0 and rm_val == 7
/* opcode: fadd.d ; op1:f30; op2:f29; dest:f31; op1val:0xffe962eb496df1c1; op2val:0x7fec05b7f6ba0d90;
valaddr_reg:x3; val_offset:64*FLEN/8; rmval:dyn; fcsr: 0;
correctval:??; testreg:x2
*/
TEST_FPRR_OP(fadd.d, f31, f30, f29, dyn, 0, 0, x3, 64*FLEN/8, x4, x1, x2)
inst_33:
// fs1 == 1 and fe1 == 0x7fe and fm1 == 0x9b3a56e2c058e and fs2 == 0 and fe2 == 0x7ff and fm2 == 0x0000000000000 and fcsr == 0x0 and rm_val == 7
/* opcode: fadd.d ; op1:f30; op2:f29; dest:f31; op1val:0xffe9b3a56e2c058e; op2val:0x7ff0000000000000;
valaddr_reg:x3; val_offset:66*FLEN/8; rmval:dyn; fcsr: 0;
correctval:??; testreg:x2
*/
TEST_FPRR_OP(fadd.d, f31, f30, f29, dyn, 0, 0, x3, 66*FLEN/8, x4, x1, x2)
inst_34:
// fs1 == 1 and fe1 == 0x7fe and fm1 == 0x9ed4cb2685903 and fs2 == 0 and fe2 == 0x7ff and fm2 == 0x0000000000000 and fcsr == 0x0 and rm_val == 7
/* opcode: fadd.d ; op1:f30; op2:f29; dest:f31; op1val:0xffe9ed4cb2685903; op2val:0x7ff0000000000000;
valaddr_reg:x3; val_offset:68*FLEN/8; rmval:dyn; fcsr: 0;
correctval:??; testreg:x2
*/
TEST_FPRR_OP(fadd.d, f31, f30, f29, dyn, 0, 0, x3, 68*FLEN/8, x4, x1, x2)
inst_35:
// fs1 == 1 and fe1 == 0x7fe and fm1 == 0x9f8dcc4f1275c and fs2 == 0 and fe2 == 0x7ff and fm2 == 0x0000000000000 and fcsr == 0x0 and rm_val == 7
/* opcode: fadd.d ; op1:f30; op2:f29; dest:f31; op1val:0xffe9f8dcc4f1275c; op2val:0x7ff0000000000000;
valaddr_reg:x3; val_offset:70*FLEN/8; rmval:dyn; fcsr: 0;
correctval:??; testreg:x2
*/
TEST_FPRR_OP(fadd.d, f31, f30, f29, dyn, 0, 0, x3, 70*FLEN/8, x4, x1, x2)
inst_36:
// fs1 == 1 and fe1 == 0x7fe and fm1 == 0xa101ccfb0623a and fs2 == 0 and fe2 == 0x7ff and fm2 == 0x0000000000000 and fcsr == 0x0 and rm_val == 7
/* opcode: fadd.d ; op1:f30; op2:f29; dest:f31; op1val:0xffea101ccfb0623a; op2val:0x7ff0000000000000;
valaddr_reg:x3; val_offset:72*FLEN/8; rmval:dyn; fcsr: 0;
correctval:??; testreg:x2
*/
TEST_FPRR_OP(fadd.d, f31, f30, f29, dyn, 0, 0, x3, 72*FLEN/8, x4, x1, x2)
inst_37:
// fs1 == 1 and fe1 == 0x7fe and fm1 == 0xa65214b23e38e and fs2 == 0 and fe2 == 0x7ff and fm2 == 0x0000000000000 and fcsr == 0x0 and rm_val == 7
/* opcode: fadd.d ; op1:f30; op2:f29; dest:f31; op1val:0xffea65214b23e38e; op2val:0x7ff0000000000000;
valaddr_reg:x3; val_offset:74*FLEN/8; rmval:dyn; fcsr: 0;
correctval:??; testreg:x2
*/
TEST_FPRR_OP(fadd.d, f31, f30, f29, dyn, 0, 0, x3, 74*FLEN/8, x4, x1, x2)
inst_38:
// fs1 == 1 and fe1 == 0x7fe and fm1 == 0xb0580f98a7dbd and fs2 == 0 and fe2 == 0x7ff and fm2 == 0x0000000000000 and fcsr == 0x0 and rm_val == 7
/* opcode: fadd.d ; op1:f30; op2:f29; dest:f31; op1val:0xffeb0580f98a7dbd; op2val:0x7ff0000000000000;
valaddr_reg:x3; val_offset:76*FLEN/8; rmval:dyn; fcsr: 0;
correctval:??; testreg:x2
*/
TEST_FPRR_OP(fadd.d, f31, f30, f29, dyn, 0, 0, x3, 76*FLEN/8, x4, x1, x2)
inst_39:
// fs1 == 1 and fe1 == 0x7fe and fm1 == 0xbc366e555215f and fs2 == 0 and fe2 == 0x7ff and fm2 == 0x0000000000000 and fcsr == 0x0 and rm_val == 7
/* opcode: fadd.d ; op1:f30; op2:f29; dest:f31; op1val:0xffebc366e555215f; op2val:0x7ff0000000000000;
valaddr_reg:x3; val_offset:78*FLEN/8; rmval:dyn; fcsr: 0;
correctval:??; testreg:x2
*/
TEST_FPRR_OP(fadd.d, f31, f30, f29, dyn, 0, 0, x3, 78*FLEN/8, x4, x1, x2)
inst_40:
// fs1 == 1 and fe1 == 0x7fe and fm1 == 0xca428c2b7c81f and fs2 == 0 and fe2 == 0x7ff and fm2 == 0x0000000000000 and fcsr == 0x0 and rm_val == 7
/* opcode: fadd.d ; op1:f30; op2:f29; dest:f31; op1val:0xffeca428c2b7c81f; op2val:0x7ff0000000000000;
valaddr_reg:x3; val_offset:80*FLEN/8; rmval:dyn; fcsr: 0;
correctval:??; testreg:x2
*/
TEST_FPRR_OP(fadd.d, f31, f30, f29, dyn, 0, 0, x3, 80*FLEN/8, x4, x1, x2)
inst_41:
// fs1 == 1 and fe1 == 0x7fe and fm1 == 0xcbdd58ecc1b45 and fs2 == 0 and fe2 == 0x7ff and fm2 == 0x0000000000000 and fcsr == 0x0 and rm_val == 7
/* opcode: fadd.d ; op1:f30; op2:f29; dest:f31; op1val:0xffecbdd58ecc1b45; op2val:0x7ff0000000000000;
valaddr_reg:x3; val_offset:82*FLEN/8; rmval:dyn; fcsr: 0;
correctval:??; testreg:x2
*/
TEST_FPRR_OP(fadd.d, f31, f30, f29, dyn, 0, 0, x3, 82*FLEN/8, x4, x1, x2)
inst_42:
// fs1 == 1 and fe1 == 0x7fe and fm1 == 0xcc3488366e29b and fs2 == 0 and fe2 == 0x7ff and fm2 == 0x0000000000000 and fcsr == 0x0 and rm_val == 7
/* opcode: fadd.d ; op1:f30; op2:f29; dest:f31; op1val:0xffecc3488366e29b; op2val:0x7ff0000000000000;
valaddr_reg:x3; val_offset:84*FLEN/8; rmval:dyn; fcsr: 0;
correctval:??; testreg:x2
*/
TEST_FPRR_OP(fadd.d, f31, f30, f29, dyn, 0, 0, x3, 84*FLEN/8, x4, x1, x2)
inst_43:
// fs1 == 1 and fe1 == 0x7fe and fm1 == 0xd0f42c0dfaf72 and fs2 == 0 and fe2 == 0x7ff and fm2 == 0x0000000000000 and fcsr == 0x0 and rm_val == 7
/* opcode: fadd.d ; op1:f30; op2:f29; dest:f31; op1val:0xffed0f42c0dfaf72; op2val:0x7ff0000000000000;
valaddr_reg:x3; val_offset:86*FLEN/8; rmval:dyn; fcsr: 0;
correctval:??; testreg:x2
*/
TEST_FPRR_OP(fadd.d, f31, f30, f29, dyn, 0, 0, x3, 86*FLEN/8, x4, x1, x2)
inst_44:
// fs1 == 1 and fe1 == 0x7fe and fm1 == 0xd1ca42e21585b and fs2 == 0 and fe2 == 0x7ff and fm2 == 0x0000000000000 and fcsr == 0x0 and rm_val == 7
/* opcode: fadd.d ; op1:f30; op2:f29; dest:f31; op1val:0xffed1ca42e21585b; op2val:0x7ff0000000000000;
valaddr_reg:x3; val_offset:88*FLEN/8; rmval:dyn; fcsr: 0;
correctval:??; testreg:x2
*/
TEST_FPRR_OP(fadd.d, f31, f30, f29, dyn, 0, 0, x3, 88*FLEN/8, x4, x1, x2)
inst_45:
// fs1 == 1 and fe1 == 0x7fe and fm1 == 0xd3762f4d1629c and fs2 == 0 and fe2 == 0x7ff and fm2 == 0x0000000000000 and fcsr == 0x0 and rm_val == 7
/* opcode: fadd.d ; op1:f30; op2:f29; dest:f31; op1val:0xffed3762f4d1629c; op2val:0x7ff0000000000000;
valaddr_reg:x3; val_offset:90*FLEN/8; rmval:dyn; fcsr: 0;
correctval:??; testreg:x2
*/
TEST_FPRR_OP(fadd.d, f31, f30, f29, dyn, 0, 0, x3, 90*FLEN/8, x4, x1, x2)
inst_46:
// fs1 == 1 and fe1 == 0x7fe and fm1 == 0xd8c56582791a6 and fs2 == 0 and fe2 == 0x7ff and fm2 == 0x0000000000000 and fcsr == 0x0 and rm_val == 7
/* opcode: fadd.d ; op1:f30; op2:f29; dest:f31; op1val:0xffed8c56582791a6; op2val:0x7ff0000000000000;
valaddr_reg:x3; val_offset:92*FLEN/8; rmval:dyn; fcsr: 0;
correctval:??; testreg:x2
*/
TEST_FPRR_OP(fadd.d, f31, f30, f29, dyn, 0, 0, x3, 92*FLEN/8, x4, x1, x2)
inst_47:
// fs1 == 1 and fe1 == 0x7fe and fm1 == 0xe64794dad7d48 and fs2 == 0 and fe2 == 0x7ff and fm2 == 0x0000000000000 and fcsr == 0x0 and rm_val == 7
/* opcode: fadd.d ; op1:f30; op2:f29; dest:f31; op1val:0xffee64794dad7d48; op2val:0x7ff0000000000000;
valaddr_reg:x3; val_offset:94*FLEN/8; rmval:dyn; fcsr: 0;
correctval:??; testreg:x2
*/
TEST_FPRR_OP(fadd.d, f31, f30, f29, dyn, 0, 0, x3, 94*FLEN/8, x4, x1, x2)
inst_48:
// fs1 == 1 and fe1 == 0x7fe and fm1 == 0xed7c3ef329d04 and fs2 == 0 and fe2 == 0x7ff and fm2 == 0x0000000000000 and fcsr == 0x0 and rm_val == 7
/* opcode: fadd.d ; op1:f30; op2:f29; dest:f31; op1val:0xffeed7c3ef329d04; op2val:0x7ff0000000000000;
valaddr_reg:x3; val_offset:96*FLEN/8; rmval:dyn; fcsr: 0;
correctval:??; testreg:x2
*/
TEST_FPRR_OP(fadd.d, f31, f30, f29, dyn, 0, 0, x3, 96*FLEN/8, x4, x1, x2)
inst_49:
// fs1 == 1 and fe1 == 0x7fe and fm1 == 0xfe1581ecd07ea and fs2 == 0 and fe2 == 0x7ff and fm2 == 0x0000000000000 and fcsr == 0x0 and rm_val == 7
/* opcode: fadd.d ; op1:f30; op2:f29; dest:f31; op1val:0xffefe1581ecd07ea; op2val:0x7ff0000000000000;
valaddr_reg:x3; val_offset:98*FLEN/8; rmval:dyn; fcsr: 0;
correctval:??; testreg:x2
*/
TEST_FPRR_OP(fadd.d, f31, f30, f29, dyn, 0, 0, x3, 98*FLEN/8, x4, x1, x2)
inst_50:
// fs1 == 1 and fe1 == 0x7f5 and fm1 == 0x2b954e52a4bff and fs2 == 0 and fe2 == 0x7fd and fm2 == 0xfa980f38509ed and fcsr == 0x0 and rm_val == 7
/* opcode: fadd.d ; op1:f30; op2:f29; dest:f31; op1val:0xff52b954e52a4bff; op2val:0x7fdfa980f38509ed;
valaddr_reg:x3; val_offset:100*FLEN/8; rmval:dyn; fcsr: 0;
correctval:??; testreg:x2
*/
TEST_FPRR_OP(fadd.d, f31, f30, f29, dyn, 0, 0, x3, 100*FLEN/8, x4, x1, x2)
inst_51:
// fs1 == 1 and fe1 == 0x7fb and fm1 == 0x49818dfc8788f and fs2 == 0 and fe2 == 0x7fd and fm2 == 0x9a1cc86f24be5 and fcsr == 0x0 and rm_val == 7
/* opcode: fadd.d ; op1:f30; op2:f29; dest:f31; op1val:0xffb49818dfc8788f; op2val:0x7fd9a1cc86f24be5;
valaddr_reg:x3; val_offset:102*FLEN/8; rmval:dyn; fcsr: 0;
correctval:??; testreg:x2
*/
TEST_FPRR_OP(fadd.d, f31, f30, f29, dyn, 0, 0, x3, 102*FLEN/8, x4, x1, x2)
inst_52:
// fs1 == 1 and fe1 == 0x7fb and fm1 == 0xbeb3709a573b7 and fs2 == 0 and fe2 == 0x7fe and fm2 == 0x52162165ec222 and fcsr == 0x0 and rm_val == 7
/* opcode: fadd.d ; op1:f30; op2:f29; dest:f31; op1val:0xffbbeb3709a573b7; op2val:0x7fe52162165ec222;
valaddr_reg:x3; val_offset:104*FLEN/8; rmval:dyn; fcsr: 0;
correctval:??; testreg:x2
*/
TEST_FPRR_OP(fadd.d, f31, f30, f29, dyn, 0, 0, x3, 104*FLEN/8, x4, x1, x2)
inst_53:
// fs1 == 1 and fe1 == 0x7fc and fm1 == 0x874e2eeac1c13 and fs2 == 0 and fe2 == 0x7fe and fm2 == 0x84645048e0d5c and fcsr == 0x0 and rm_val == 7
/* opcode: fadd.d ; op1:f30; op2:f29; dest:f31; op1val:0xffc874e2eeac1c13; op2val:0x7fe84645048e0d5c;
valaddr_reg:x3; val_offset:106*FLEN/8; rmval:dyn; fcsr: 0;
correctval:??; testreg:x2
*/
TEST_FPRR_OP(fadd.d, f31, f30, f29, dyn, 0, 0, x3, 106*FLEN/8, x4, x1, x2)
#endif
RVTEST_CODE_END
RVMODEL_HALT
RVTEST_DATA_BEGIN
.align 4
rvtest_data:
.word 0xbabecafe
.word 0xabecafeb
.word 0xbecafeba
.word 0xecafebab
test_dataset_0:
NAN_BOXED(18397971202035043327,64,FLEN)
NAN_BOXED(18397971202035043327,64,FLEN)
NAN_BOXED(18425519208080636047,64,FLEN)
NAN_BOXED(9212572412572486629,64,FLEN)
NAN_BOXED(18427580921934082999,64,FLEN)
NAN_BOXED(18427580921934082999,64,FLEN)
NAN_BOXED(18431049617306335947,64,FLEN)
NAN_BOXED(9212133229347595375,64,FLEN)
NAN_BOXED(18431109993029442579,64,FLEN)
NAN_BOXED(9216693899656826204,64,FLEN)
NAN_BOXED(18432823120430268499,64,FLEN)
NAN_BOXED(9218868437227405312,64,FLEN)
NAN_BOXED(18433422287488126063,64,FLEN)
NAN_BOXED(9218868437227405312,64,FLEN)
NAN_BOXED(18433806814444139271,64,FLEN)
NAN_BOXED(9218868437227405312,64,FLEN)
NAN_BOXED(18434316797110535277,64,FLEN)
NAN_BOXED(9218868437227405312,64,FLEN)
NAN_BOXED(18434588036187623253,64,FLEN)
NAN_BOXED(9218868437227405312,64,FLEN)
NAN_BOXED(18436306019258919287,64,FLEN)
NAN_BOXED(9215981524762367886,64,FLEN)
NAN_BOXED(18436551019665527329,64,FLEN)
NAN_BOXED(9218868437227405312,64,FLEN)
NAN_BOXED(18436846298556593485,64,FLEN)
NAN_BOXED(9218868437227405312,64,FLEN)
NAN_BOXED(18437235042229583767,64,FLEN)
NAN_BOXED(9215020957333686289,64,FLEN)
NAN_BOXED(18437314094392245391,64,FLEN)
NAN_BOXED(9214962513487970736,64,FLEN)
NAN_BOXED(18437315282660575483,64,FLEN)
NAN_BOXED(9218868437227405312,64,FLEN)
NAN_BOXED(18437322719407809231,64,FLEN)
NAN_BOXED(9218868437227405312,64,FLEN)
NAN_BOXED(18437808397404204101,64,FLEN)
NAN_BOXED(9218868437227405312,64,FLEN)
NAN_BOXED(18437838428116719366,64,FLEN)
NAN_BOXED(9218113713723006116,64,FLEN)
NAN_BOXED(18438102566068545279,64,FLEN)
NAN_BOXED(9218255010705825878,64,FLEN)
NAN_BOXED(18438175518788024948,64,FLEN)
NAN_BOXED(9214929958324501788,64,FLEN)
NAN_BOXED(18438418278213217007,64,FLEN)
NAN_BOXED(9217661297036112644,64,FLEN)
NAN_BOXED(18438526058809954207,64,FLEN)
NAN_BOXED(9218868437227405312,64,FLEN)
NAN_BOXED(18438604149402703327,64,FLEN)
NAN_BOXED(9218698993863081419,64,FLEN)
NAN_BOXED(18438752644956477909,64,FLEN)
NAN_BOXED(9218868437227405312,64,FLEN)
NAN_BOXED(18438752734354480701,64,FLEN)
NAN_BOXED(9218868437227405312,64,FLEN)
NAN_BOXED(18438803047593449109,64,FLEN)
NAN_BOXED(9217687371269900967,64,FLEN)
NAN_BOXED(18439585902940989928,64,FLEN)
NAN_BOXED(9218696557538277899,64,FLEN)
NAN_BOXED(18439597414231821920,64,FLEN)
NAN_BOXED(9218868437227405312,64,FLEN)
NAN_BOXED(18439715798342451422,64,FLEN)
NAN_BOXED(9218868437227405312,64,FLEN)
NAN_BOXED(18440057164308765069,64,FLEN)
NAN_BOXED(9218868437227405312,64,FLEN)
NAN_BOXED(18440293104894461172,64,FLEN)
NAN_BOXED(9218868437227405312,64,FLEN)
NAN_BOXED(18440378911933985217,64,FLEN)
NAN_BOXED(9217748824997105040,64,FLEN)
NAN_BOXED(18440467672344561038,64,FLEN)
NAN_BOXED(9218868437227405312,64,FLEN)
NAN_BOXED(18440531062911686915,64,FLEN)
NAN_BOXED(9218868437227405312,64,FLEN)
NAN_BOXED(18440543776325838684,64,FLEN)
NAN_BOXED(9218868437227405312,64,FLEN)
NAN_BOXED(18440569340151489082,64,FLEN)
NAN_BOXED(9218868437227405312,64,FLEN)
NAN_BOXED(18440662817890886542,64,FLEN)
NAN_BOXED(9218868437227405312,64,FLEN)
NAN_BOXED(18440839150699183549,64,FLEN)
NAN_BOXED(9218868437227405312,64,FLEN)
NAN_BOXED(18441047945900269919,64,FLEN)
NAN_BOXED(9218868437227405312,64,FLEN)
NAN_BOXED(18441295069147809823,64,FLEN)
NAN_BOXED(9218868437227405312,64,FLEN)
NAN_BOXED(18441323299096763205,64,FLEN)
NAN_BOXED(9218868437227405312,64,FLEN)
NAN_BOXED(18441329290384958107,64,FLEN)
NAN_BOXED(9218868437227405312,64,FLEN)
NAN_BOXED(18441412828530192242,64,FLEN)
NAN_BOXED(9218868437227405312,64,FLEN)
NAN_BOXED(18441427540626200667,64,FLEN)
NAN_BOXED(9218868437227405312,64,FLEN)
NAN_BOXED(18441456947305734812,64,FLEN)
NAN_BOXED(9218868437227405312,64,FLEN)
NAN_BOXED(18441550351626113446,64,FLEN)
NAN_BOXED(9218868437227405312,64,FLEN)
NAN_BOXED(18441787996285795656,64,FLEN)
NAN_BOXED(9218868437227405312,64,FLEN)
NAN_BOXED(18441914760660425988,64,FLEN)
NAN_BOXED(9218868437227405312,64,FLEN)
NAN_BOXED(18442206767695595498,64,FLEN)
NAN_BOXED(9218868437227405312,64,FLEN)
NAN_BOXED(18397971202035043327,64,FLEN)
NAN_BOXED(9214269733929814509,64,FLEN)
NAN_BOXED(18425519208080636047,64,FLEN)
NAN_BOXED(9212572412572486629,64,FLEN)
NAN_BOXED(18427580921934082999,64,FLEN)
NAN_BOXED(9215808917649408546,64,FLEN)
NAN_BOXED(18431109993029442579,64,FLEN)
NAN_BOXED(9216693899656826204,64,FLEN)
RVTEST_DATA_END
RVMODEL_DATA_BEGIN
rvtest_sig_begin:
sig_begin_canary:
CANARY;
signature_x1_0:
.fill 0*((SIGALIGN)/4),4,0xdeadbeef
signature_x1_1:
.fill 108*((SIGALIGN)/4),4,0xdeadbeef
#ifdef rvtest_mtrap_routine
tsig_begin_canary:
CANARY;
tsig_begin_canary:
CANARY;
mtrap_sigptr:
.fill 64*(XLEN/32),4,0xdeadbeef
tsig_end_canary:
CANARY;
tsig_end_canary:
CANARY;
#endif
#ifdef rvtest_gpr_save
gpr_save:
.fill 32*XLEN/32,4,0xdeadbeef
#endif
sig_end_canary:
CANARY;
rvtest_sig_end:
RVMODEL_DATA_END

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// -----------
// This file was generated by riscv_ctg (https://github.com/riscv-software-src/riscv-ctg)
// version : 0.7.1
// timestamp : Thu Jun 30 07:22:55 2022 GMT
// usage : riscv_ctg \
// -- cgf // --cgf /scratch/pawan/work/normalised/RV32D/fclass.d.cgf \
\
// -- xlen 32 \
// --randomize \
// -----------
//
// -----------
// Copyright (c) 2020. RISC-V International. All rights reserved.
// SPDX-License-Identifier: BSD-3-Clause
// -----------
//
// This assembly file tests the fclass.d instruction of the RISC-V RV32FD_Zicsr,RV64FD_Zicsr extension for the fclass.d_b1 covergroup.
//
#include "model_test.h"
#include "arch_test.h"
RVTEST_ISA("RV32IFD_Zicsr,RV64IFD_Zicsr")
.section .text.init
.org 0x80
.globl rvtest_entry_point
rvtest_entry_point:
RVMODEL_BOOT
RVTEST_CODE_BEGIN
#ifdef TEST_CASE_1
RVTEST_CASE(0,"//check ISA:=regex(.*I.*D.*);def TEST_CASE_1=True;",fclass.d_b1)
RVTEST_FP_ENABLE()
RVTEST_VALBASEUPD(x5,test_dataset_0)
RVTEST_SIGBASE(x11,signature_x11_1)
inst_0:// rs1==f14, rd==x20,fs1 == 0 and fe1 == 0x000 and fm1 == 0x0000000000000 and fcsr == 0
/* opcode: fclass.d ; op1:f14; dest:x20; op1val:0x0; valaddr_reg:x5;
val_offset:0*FLEN/8; correctval:??; testreg:x19;
fcsr_val:0*/
TEST_FPID_OP_NRM(fclass.d, x20, f14, 0, 0, x5, 0*FLEN/8, x13, x11, x19)
inst_1:// rs1==f3, rd==x1,fs1 == 1 and fe1 == 0x000 and fm1 == 0x0000000000000 and fcsr == 0
/* opcode: fclass.d ; op1:f3; dest:x1; op1val:0x8000000000000000; valaddr_reg:x5;
val_offset:1*FLEN/8; correctval:??; testreg:x19;
fcsr_val:0*/
TEST_FPID_OP_NRM(fclass.d, x1, f3, 0, 0, x5, 1*FLEN/8, x13, x11, x19)
inst_2:// rs1==f29, rd==x8,fs1 == 0 and fe1 == 0x000 and fm1 == 0x0000000000001 and fcsr == 0
/* opcode: fclass.d ; op1:f29; dest:x8; op1val:0x1; valaddr_reg:x5;
val_offset:2*FLEN/8; correctval:??; testreg:x19;
fcsr_val:0*/
TEST_FPID_OP_NRM(fclass.d, x8, f29, 0, 0, x5, 2*FLEN/8, x13, x11, x19)
inst_3:// rs1==f5, rd==x23,fs1 == 1 and fe1 == 0x000 and fm1 == 0x0000000000001 and fcsr == 0
/* opcode: fclass.d ; op1:f5; dest:x23; op1val:0x8000000000000001; valaddr_reg:x5;
val_offset:3*FLEN/8; correctval:??; testreg:x19;
fcsr_val:0*/
TEST_FPID_OP_NRM(fclass.d, x23, f5, 0, 0, x5, 3*FLEN/8, x13, x11, x19)
inst_4:// rs1==f4, rd==x0,fs1 == 0 and fe1 == 0x000 and fm1 == 0x0000000000002 and fcsr == 0
/* opcode: fclass.d ; op1:f4; dest:x0; op1val:0x2; valaddr_reg:x5;
val_offset:4*FLEN/8; correctval:??; testreg:x19;
fcsr_val:0*/
TEST_FPID_OP_NRM(fclass.d, x0, f4, 0, 0, x5, 4*FLEN/8, x13, x11, x19)
inst_5:// rs1==f17, rd==x9,fs1 == 1 and fe1 == 0x000 and fm1 == 0x0000000000002 and fcsr == 0
/* opcode: fclass.d ; op1:f17; dest:x9; op1val:0x8000000000000002; valaddr_reg:x5;
val_offset:5*FLEN/8; correctval:??; testreg:x19;
fcsr_val:0*/
TEST_FPID_OP_NRM(fclass.d, x9, f17, 0, 0, x5, 5*FLEN/8, x13, x11, x19)
inst_6:// rs1==f8, rd==x6,fs1 == 0 and fe1 == 0x000 and fm1 == 0xfffffffffffff and fcsr == 0
/* opcode: fclass.d ; op1:f8; dest:x6; op1val:0xfffffffffffff; valaddr_reg:x5;
val_offset:6*FLEN/8; correctval:??; testreg:x19;
fcsr_val:0*/
TEST_FPID_OP_NRM(fclass.d, x6, f8, 0, 0, x5, 6*FLEN/8, x13, x11, x19)
inst_7:// rs1==f24, rd==x24,fs1 == 1 and fe1 == 0x000 and fm1 == 0xfffffffffffff and fcsr == 0
/* opcode: fclass.d ; op1:f24; dest:x24; op1val:0x800fffffffffffff; valaddr_reg:x5;
val_offset:7*FLEN/8; correctval:??; testreg:x19;
fcsr_val:0*/
TEST_FPID_OP_NRM(fclass.d, x24, f24, 0, 0, x5, 7*FLEN/8, x13, x11, x19)
inst_8:// rs1==f9, rd==x17,fs1 == 0 and fe1 == 0x001 and fm1 == 0x0000000000000 and fcsr == 0
/* opcode: fclass.d ; op1:f9; dest:x17; op1val:0x10000000000000; valaddr_reg:x5;
val_offset:8*FLEN/8; correctval:??; testreg:x19;
fcsr_val:0*/
TEST_FPID_OP_NRM(fclass.d, x17, f9, 0, 0, x5, 8*FLEN/8, x13, x11, x19)
inst_9:// rs1==f6, rd==x22,fs1 == 1 and fe1 == 0x001 and fm1 == 0x0000000000000 and fcsr == 0
/* opcode: fclass.d ; op1:f6; dest:x22; op1val:0x8010000000000000; valaddr_reg:x5;
val_offset:9*FLEN/8; correctval:??; testreg:x19;
fcsr_val:0*/
TEST_FPID_OP_NRM(fclass.d, x22, f6, 0, 0, x5, 9*FLEN/8, x13, x11, x19)
inst_10:// rs1==f1, rd==x10,fs1 == 0 and fe1 == 0x001 and fm1 == 0x0000000000002 and fcsr == 0
/* opcode: fclass.d ; op1:f1; dest:x10; op1val:0x10000000000002; valaddr_reg:x5;
val_offset:10*FLEN/8; correctval:??; testreg:x19;
fcsr_val:0*/
TEST_FPID_OP_NRM(fclass.d, x10, f1, 0, 0, x5, 10*FLEN/8, x13, x11, x19)
inst_11:// rs1==f13, rd==x27,fs1 == 1 and fe1 == 0x001 and fm1 == 0x0000000000002 and fcsr == 0
/* opcode: fclass.d ; op1:f13; dest:x27; op1val:0x8010000000000002; valaddr_reg:x5;
val_offset:11*FLEN/8; correctval:??; testreg:x19;
fcsr_val:0*/
TEST_FPID_OP_NRM(fclass.d, x27, f13, 0, 0, x5, 11*FLEN/8, x13, x11, x19)
inst_12:// rs1==f2, rd==x3,fs1 == 0 and fe1 == 0x7fe and fm1 == 0xfffffffffffff and fcsr == 0
/* opcode: fclass.d ; op1:f2; dest:x3; op1val:0x7fefffffffffffff; valaddr_reg:x5;
val_offset:12*FLEN/8; correctval:??; testreg:x19;
fcsr_val:0*/
TEST_FPID_OP_NRM(fclass.d, x3, f2, 0, 0, x5, 12*FLEN/8, x13, x11, x19)
inst_13:// rs1==f27, rd==x28,fs1 == 1 and fe1 == 0x7fe and fm1 == 0xfffffffffffff and fcsr == 0
/* opcode: fclass.d ; op1:f27; dest:x28; op1val:0xffefffffffffffff; valaddr_reg:x5;
val_offset:13*FLEN/8; correctval:??; testreg:x19;
fcsr_val:0*/
TEST_FPID_OP_NRM(fclass.d, x28, f27, 0, 0, x5, 13*FLEN/8, x13, x11, x19)
inst_14:// rs1==f26, rd==x18,fs1 == 0 and fe1 == 0x7ff and fm1 == 0x0000000000000 and fcsr == 0
/* opcode: fclass.d ; op1:f26; dest:x18; op1val:0x7ff0000000000000; valaddr_reg:x5;
val_offset:14*FLEN/8; correctval:??; testreg:x19;
fcsr_val:0*/
TEST_FPID_OP_NRM(fclass.d, x18, f26, 0, 0, x5, 14*FLEN/8, x13, x11, x19)
inst_15:// rs1==f31, rd==x31,fs1 == 1 and fe1 == 0x7ff and fm1 == 0x0000000000000 and fcsr == 0
/* opcode: fclass.d ; op1:f31; dest:x31; op1val:0xfff0000000000000; valaddr_reg:x5;
val_offset:15*FLEN/8; correctval:??; testreg:x19;
fcsr_val:0*/
TEST_FPID_OP_NRM(fclass.d, x31, f31, 0, 0, x5, 15*FLEN/8, x13, x11, x19)
inst_16:// rs1==f11, rd==x7,fs1 == 0 and fe1 == 0x7ff and fm1 == 0x8000000000000 and fcsr == 0
/* opcode: fclass.d ; op1:f11; dest:x7; op1val:0x7ff8000000000000; valaddr_reg:x5;
val_offset:16*FLEN/8; correctval:??; testreg:x19;
fcsr_val:0*/
TEST_FPID_OP_NRM(fclass.d, x7, f11, 0, 0, x5, 16*FLEN/8, x13, x11, x19)
inst_17:// rs1==f28, rd==x12,fs1 == 1 and fe1 == 0x7ff and fm1 == 0x8000000000000 and fcsr == 0
/* opcode: fclass.d ; op1:f28; dest:x12; op1val:0xfff8000000000000; valaddr_reg:x5;
val_offset:17*FLEN/8; correctval:??; testreg:x19;
fcsr_val:0*/
TEST_FPID_OP_NRM(fclass.d, x12, f28, 0, 0, x5, 17*FLEN/8, x13, x11, x19)
inst_18:// rs1==f18, rd==x29,fs1 == 0 and fe1 == 0x7ff and fm1 == 0x8000000000001 and fcsr == 0
/* opcode: fclass.d ; op1:f18; dest:x29; op1val:0x7ff8000000000001; valaddr_reg:x5;
val_offset:18*FLEN/8; correctval:??; testreg:x19;
fcsr_val:0*/
TEST_FPID_OP_NRM(fclass.d, x29, f18, 0, 0, x5, 18*FLEN/8, x13, x11, x19)
inst_19:// rs1==f21, rd==x25,fs1 == 1 and fe1 == 0x7ff and fm1 == 0x8000000000001 and fcsr == 0
/* opcode: fclass.d ; op1:f21; dest:x25; op1val:0xfff8000000000001; valaddr_reg:x5;
val_offset:19*FLEN/8; correctval:??; testreg:x19;
fcsr_val:0*/
TEST_FPID_OP_NRM(fclass.d, x25, f21, 0, 0, x5, 19*FLEN/8, x13, x11, x19)
inst_20:// rs1==f0, rd==x14,fs1 == 0 and fe1 == 0x7ff and fm1 == 0x0000000000001 and fcsr == 0
/* opcode: fclass.d ; op1:f0; dest:x14; op1val:0x7ff0000000000001; valaddr_reg:x5;
val_offset:20*FLEN/8; correctval:??; testreg:x19;
fcsr_val:0*/
TEST_FPID_OP_NRM(fclass.d, x14, f0, 0, 0, x5, 20*FLEN/8, x13, x11, x19)
inst_21:// rs1==f10, rd==x4,fs1 == 1 and fe1 == 0x7ff and fm1 == 0x0000000000001 and fcsr == 0
/* opcode: fclass.d ; op1:f10; dest:x4; op1val:0xfff0000000000001; valaddr_reg:x5;
val_offset:21*FLEN/8; correctval:??; testreg:x19;
fcsr_val:0*/
TEST_FPID_OP_NRM(fclass.d, x4, f10, 0, 0, x5, 21*FLEN/8, x13, x11, x19)
inst_22:// rs1==f15, rd==x2,fs1 == 0 and fe1 == 0x3ff and fm1 == 0x0000000000000 and fcsr == 0
/* opcode: fclass.d ; op1:f15; dest:x2; op1val:0x3ff0000000000000; valaddr_reg:x5;
val_offset:22*FLEN/8; correctval:??; testreg:x19;
fcsr_val:0*/
TEST_FPID_OP_NRM(fclass.d, x2, f15, 0, 0, x5, 22*FLEN/8, x13, x11, x19)
inst_23:// rs1==f25, rd==x15,fs1 == 1 and fe1 == 0x3f8 and fm1 == 0x0000000000000 and fcsr == 0
/* opcode: fclass.d ; op1:f25; dest:x15; op1val:0xbf80000000000000; valaddr_reg:x5;
val_offset:23*FLEN/8; correctval:??; testreg:x19;
fcsr_val:0*/
TEST_FPID_OP_NRM(fclass.d, x15, f25, 0, 0, x5, 23*FLEN/8, x13, x11, x19)
inst_24:// rs1==f19, rd==x16,
/* opcode: fclass.d ; op1:f19; dest:x16; op1val:0x0; valaddr_reg:x5;
val_offset:24*FLEN/8; correctval:??; testreg:x19;
fcsr_val:0*/
TEST_FPID_OP_NRM(fclass.d, x16, f19, 0, 0, x5, 24*FLEN/8, x13, x11, x19)
RVTEST_VALBASEUPD(x3,test_dataset_1)
inst_25:// rs1==f12, rd==x13,
/* opcode: fclass.d ; op1:f12; dest:x13; op1val:0x0; valaddr_reg:x3;
val_offset:0*FLEN/8; correctval:??; testreg:x19;
fcsr_val:0*/
TEST_FPID_OP_NRM(fclass.d, x13, f12, 0, 0, x3, 0*FLEN/8, x4, x11, x19)
inst_26:// rs1==f16, rd==x5,
/* opcode: fclass.d ; op1:f16; dest:x5; op1val:0x0; valaddr_reg:x3;
val_offset:1*FLEN/8; correctval:??; testreg:x19;
fcsr_val:0*/
TEST_FPID_OP_NRM(fclass.d, x5, f16, 0, 0, x3, 1*FLEN/8, x4, x11, x19)
inst_27:// rs1==f7, rd==x19,
/* opcode: fclass.d ; op1:f7; dest:x19; op1val:0x0; valaddr_reg:x3;
val_offset:2*FLEN/8; correctval:??; testreg:x2;
fcsr_val:0*/
TEST_FPID_OP_NRM(fclass.d, x19, f7, 0, 0, x3, 2*FLEN/8, x4, x11, x2)
RVTEST_SIGBASE(x1,signature_x1_0)
inst_28:// rs1==f30, rd==x21,
/* opcode: fclass.d ; op1:f30; dest:x21; op1val:0x0; valaddr_reg:x3;
val_offset:3*FLEN/8; correctval:??; testreg:x2;
fcsr_val:0*/
TEST_FPID_OP_NRM(fclass.d, x21, f30, 0, 0, x3, 3*FLEN/8, x4, x1, x2)
inst_29:// rs1==f22, rd==x30,
/* opcode: fclass.d ; op1:f22; dest:x30; op1val:0x0; valaddr_reg:x3;
val_offset:4*FLEN/8; correctval:??; testreg:x2;
fcsr_val:0*/
TEST_FPID_OP_NRM(fclass.d, x30, f22, 0, 0, x3, 4*FLEN/8, x4, x1, x2)
inst_30:// rs1==f23, rd==x11,
/* opcode: fclass.d ; op1:f23; dest:x11; op1val:0x0; valaddr_reg:x3;
val_offset:5*FLEN/8; correctval:??; testreg:x2;
fcsr_val:0*/
TEST_FPID_OP_NRM(fclass.d, x11, f23, 0, 0, x3, 5*FLEN/8, x4, x1, x2)
inst_31:// rs1==f20, rd==x26,
/* opcode: fclass.d ; op1:f20; dest:x26; op1val:0x0; valaddr_reg:x3;
val_offset:6*FLEN/8; correctval:??; testreg:x2;
fcsr_val:0*/
TEST_FPID_OP_NRM(fclass.d, x26, f20, 0, 0, x3, 6*FLEN/8, x4, x1, x2)
inst_32:// fs1 == 0 and fe1 == 0x000 and fm1 == 0x0000000000002 and fcsr == 0
/* opcode: fclass.d ; op1:f31; dest:x31; op1val:0x2; valaddr_reg:x3;
val_offset:7*FLEN/8; correctval:??; testreg:x2;
fcsr_val:0*/
TEST_FPID_OP_NRM(fclass.d, x31, f31, 0, 0, x3, 7*FLEN/8, x4, x1, x2)
#endif
RVTEST_CODE_END
RVMODEL_HALT
RVTEST_DATA_BEGIN
.align 4
rvtest_data:
.word 0xbabecafe
.word 0xabecafeb
.word 0xbecafeba
.word 0xecafebab
test_dataset_0:
NAN_BOXED(0,64,FLEN)
NAN_BOXED(9223372036854775808,64,FLEN)
NAN_BOXED(1,64,FLEN)
NAN_BOXED(9223372036854775809,64,FLEN)
NAN_BOXED(2,64,FLEN)
NAN_BOXED(9223372036854775810,64,FLEN)
NAN_BOXED(4503599627370495,64,FLEN)
NAN_BOXED(9227875636482146303,64,FLEN)
NAN_BOXED(4503599627370496,64,FLEN)
NAN_BOXED(9227875636482146304,64,FLEN)
NAN_BOXED(4503599627370498,64,FLEN)
NAN_BOXED(9227875636482146306,64,FLEN)
NAN_BOXED(9218868437227405311,64,FLEN)
NAN_BOXED(18442240474082181119,64,FLEN)
NAN_BOXED(9218868437227405312,64,FLEN)
NAN_BOXED(18442240474082181120,64,FLEN)
NAN_BOXED(9221120237041090560,64,FLEN)
NAN_BOXED(18444492273895866368,64,FLEN)
NAN_BOXED(9221120237041090561,64,FLEN)
NAN_BOXED(18444492273895866369,64,FLEN)
NAN_BOXED(9218868437227405313,64,FLEN)
NAN_BOXED(18442240474082181121,64,FLEN)
NAN_BOXED(4607182418800017408,64,FLEN)
NAN_BOXED(13799029258263199744,64,FLEN)
NAN_BOXED(0,64,FLEN)
test_dataset_1:
NAN_BOXED(0,64,FLEN)
NAN_BOXED(0,64,FLEN)
NAN_BOXED(0,64,FLEN)
NAN_BOXED(0,64,FLEN)
NAN_BOXED(0,64,FLEN)
NAN_BOXED(0,64,FLEN)
NAN_BOXED(0,64,FLEN)
NAN_BOXED(2,64,FLEN)
RVTEST_DATA_END
RVMODEL_DATA_BEGIN
rvtest_sig_begin:
sig_begin_canary:
CANARY;
signature_x11_0:
.fill 0*((SIGALIGN)/4),4,0xdeadbeef
signature_x11_1:
.fill 56*((SIGALIGN)/4),4,0xdeadbeef
signature_x1_0:
.fill 10*((SIGALIGN)/4),4,0xdeadbeef
#ifdef rvtest_mtrap_routine
tsig_begin_canary:
CANARY;
tsig_begin_canary:
CANARY;
mtrap_sigptr:
.fill 64*(XLEN/32),4,0xdeadbeef
tsig_end_canary:
CANARY;
tsig_end_canary:
CANARY;
#endif
#ifdef rvtest_gpr_save
gpr_save:
.fill 32*XLEN/32,4,0xdeadbeef
#endif
sig_end_canary:
CANARY;
rvtest_sig_end:
RVMODEL_DATA_END

356
vendor/riscv-arch-tests/riscv-test-suite/rv32i_m/D/src/fcvt.d.s_b1-01.S vendored
View file

@ -1,356 +0,0 @@
// -----------
// This file was generated by riscv_ctg (https://github.com/riscv-software-src/riscv-ctg)
// version : 0.7.1
// timestamp : Fri Jun 17 14:03:32 2022 GMT
// usage : riscv_ctg \
// -- cgf // --cgf /scratch/pawan/work/normalised/RV32D/fcvt.d.s.cgf \
\
// -- xlen 32 \
// --randomize \
// -----------
//
// -----------
// Copyright (c) 2020. RISC-V International. All rights reserved.
// SPDX-License-Identifier: BSD-3-Clause
// -----------
//
// This assembly file tests the fcvt.d.s instruction of the RISC-V RV32FD_Zicsr,RV64FD_Zicsr extension for the fcvt.d.s_b1 covergroup.
//
#include "model_test.h"
#include "arch_test.h"
RVTEST_ISA("RV32IFD_Zicsr,RV64IFD_Zicsr")
.section .text.init
.org 0x80
.globl rvtest_entry_point
rvtest_entry_point:
RVMODEL_BOOT
RVTEST_CODE_BEGIN
#ifdef TEST_CASE_1
RVTEST_CASE(0,"//check ISA:=regex(.*I.*D.*);def TEST_CASE_1=True;",fcvt.d.s_b1)
RVTEST_FP_ENABLE()
RVTEST_VALBASEUPD(x3,test_dataset_0)
RVTEST_SIGBASE(x1,signature_x1_1)
inst_0:
// rs1 == rd, rs1==f9, rd==f9,fs1 == 0 and fe1 == 0x00 and fm1 == 0x000000 and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffffffff
/* opcode: fcvt.d.s ; op1:f9; dest:f9; op1val:0x0; valaddr_reg:x3;
val_offset:0*FLEN/8; correctval:??; testreg:x2;
fcsr_val: 0 */
TEST_FPSR_OP_NRM(fcvt.d.s, f9, f9, 0, 0, x3, 0*FLEN/8, x4, x1, x2)
inst_1:
// rs1 != rd, rs1==f10, rd==f6,fs1 == 0 and fe1 == 0x00 and fm1 == 0x000001 and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffffffff
/* opcode: fcvt.d.s ; op1:f10; dest:f6; op1val:0x1; valaddr_reg:x3;
val_offset:1*FLEN/8; correctval:??; testreg:x2;
fcsr_val: 0 */
TEST_FPSR_OP_NRM(fcvt.d.s, f6, f10, 0, 0, x3, 1*FLEN/8, x4, x1, x2)
inst_2:
// rs1==f20, rd==f13,fs1 == 0 and fe1 == 0x00 and fm1 == 0x000002 and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffffffff
/* opcode: fcvt.d.s ; op1:f20; dest:f13; op1val:0x2; valaddr_reg:x3;
val_offset:2*FLEN/8; correctval:??; testreg:x2;
fcsr_val: 0 */
TEST_FPSR_OP_NRM(fcvt.d.s, f13, f20, 0, 0, x3, 2*FLEN/8, x4, x1, x2)
inst_3:
// rs1==f27, rd==f26,fs1 == 0 and fe1 == 0x00 and fm1 == 0x7fffff and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffffffff
/* opcode: fcvt.d.s ; op1:f27; dest:f26; op1val:0x7fffff; valaddr_reg:x3;
val_offset:3*FLEN/8; correctval:??; testreg:x2;
fcsr_val: 0 */
TEST_FPSR_OP_NRM(fcvt.d.s, f26, f27, 0, 0, x3, 3*FLEN/8, x4, x1, x2)
inst_4:
// rs1==f29, rd==f24,fs1 == 0 and fe1 == 0x01 and fm1 == 0x000000 and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffffffff
/* opcode: fcvt.d.s ; op1:f29; dest:f24; op1val:0x10000000000000; valaddr_reg:x3;
val_offset:4*FLEN/8; correctval:??; testreg:x2;
fcsr_val: 0 */
TEST_FPSR_OP_NRM(fcvt.d.s, f24, f29, 0, 0, x3, 4*FLEN/8, x4, x1, x2)
inst_5:
// rs1==f17, rd==f25,fs1 == 0 and fe1 == 0x01 and fm1 == 0x000001 and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffffffff
/* opcode: fcvt.d.s ; op1:f17; dest:f25; op1val:0x10000000000001; valaddr_reg:x3;
val_offset:5*FLEN/8; correctval:??; testreg:x2;
fcsr_val: 0 */
TEST_FPSR_OP_NRM(fcvt.d.s, f25, f17, 0, 0, x3, 5*FLEN/8, x4, x1, x2)
inst_6:
// rs1==f25, rd==f15,fs1 == 0 and fe1 == 0x7f and fm1 == 0x000000 and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffffffff
/* opcode: fcvt.d.s ; op1:f25; dest:f15; op1val:0x7f0000000000000; valaddr_reg:x3;
val_offset:6*FLEN/8; correctval:??; testreg:x2;
fcsr_val: 0 */
TEST_FPSR_OP_NRM(fcvt.d.s, f15, f25, 0, 0, x3, 6*FLEN/8, x4, x1, x2)
inst_7:
// rs1==f11, rd==f27,fs1 == 0 and fe1 == 0xfe and fm1 == 0x7fffff and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffffffff
/* opcode: fcvt.d.s ; op1:f11; dest:f27; op1val:0xfe00000007fffff; valaddr_reg:x3;
val_offset:7*FLEN/8; correctval:??; testreg:x2;
fcsr_val: 0 */
TEST_FPSR_OP_NRM(fcvt.d.s, f27, f11, 0, 0, x3, 7*FLEN/8, x4, x1, x2)
inst_8:
// rs1==f8, rd==f29,fs1 == 0 and fe1 == 0xff and fm1 == 0x000000 and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffffffff
/* opcode: fcvt.d.s ; op1:f8; dest:f29; op1val:0xff0000000000000; valaddr_reg:x3;
val_offset:8*FLEN/8; correctval:??; testreg:x2;
fcsr_val: 0 */
TEST_FPSR_OP_NRM(fcvt.d.s, f29, f8, 0, 0, x3, 8*FLEN/8, x4, x1, x2)
inst_9:
// rs1==f5, rd==f1,fs1 == 0 and fe1 == 0xff and fm1 == 0x000001 and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffffffff
/* opcode: fcvt.d.s ; op1:f5; dest:f1; op1val:0xff0000000000001; valaddr_reg:x3;
val_offset:9*FLEN/8; correctval:??; testreg:x2;
fcsr_val: 0 */
TEST_FPSR_OP_NRM(fcvt.d.s, f1, f5, 0, 0, x3, 9*FLEN/8, x4, x1, x2)
inst_10:
// rs1==f22, rd==f18,fs1 == 0 and fe1 == 0xff and fm1 == 0x400000 and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffffffff
/* opcode: fcvt.d.s ; op1:f22; dest:f18; op1val:0xff0000000400000; valaddr_reg:x3;
val_offset:10*FLEN/8; correctval:??; testreg:x2;
fcsr_val: 0 */
TEST_FPSR_OP_NRM(fcvt.d.s, f18, f22, 0, 0, x3, 10*FLEN/8, x4, x1, x2)
inst_11:
// rs1==f16, rd==f22,fs1 == 0 and fe1 == 0xff and fm1 == 0x400001 and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffffffff
/* opcode: fcvt.d.s ; op1:f16; dest:f22; op1val:0xff0000000400001; valaddr_reg:x3;
val_offset:11*FLEN/8; correctval:??; testreg:x2;
fcsr_val: 0 */
TEST_FPSR_OP_NRM(fcvt.d.s, f22, f16, 0, 0, x3, 11*FLEN/8, x4, x1, x2)
inst_12:
// rs1==f15, rd==f11,fs1 == 1 and fe1 == 0x00 and fm1 == 0x000000 and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffffffff
/* opcode: fcvt.d.s ; op1:f15; dest:f11; op1val:0x8000000000000000; valaddr_reg:x3;
val_offset:12*FLEN/8; correctval:??; testreg:x2;
fcsr_val: 0 */
TEST_FPSR_OP_NRM(fcvt.d.s, f11, f15, 0, 0, x3, 12*FLEN/8, x4, x1, x2)
inst_13:
// rs1==f14, rd==f0,fs1 == 1 and fe1 == 0x00 and fm1 == 0x000001 and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffffffff
/* opcode: fcvt.d.s ; op1:f14; dest:f0; op1val:0x8000000000000001; valaddr_reg:x3;
val_offset:13*FLEN/8; correctval:??; testreg:x2;
fcsr_val: 0 */
TEST_FPSR_OP_NRM(fcvt.d.s, f0, f14, 0, 0, x3, 13*FLEN/8, x4, x1, x2)
inst_14:
// rs1==f31, rd==f4,fs1 == 1 and fe1 == 0x00 and fm1 == 0x7ffffe and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffffffff
/* opcode: fcvt.d.s ; op1:f31; dest:f4; op1val:0x80000000007ffffe; valaddr_reg:x3;
val_offset:14*FLEN/8; correctval:??; testreg:x2;
fcsr_val: 0 */
TEST_FPSR_OP_NRM(fcvt.d.s, f4, f31, 0, 0, x3, 14*FLEN/8, x4, x1, x2)
inst_15:
// rs1==f19, rd==f7,fs1 == 1 and fe1 == 0x00 and fm1 == 0x7fffff and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffffffff
/* opcode: fcvt.d.s ; op1:f19; dest:f7; op1val:0x80000000007fffff; valaddr_reg:x3;
val_offset:15*FLEN/8; correctval:??; testreg:x2;
fcsr_val: 0 */
TEST_FPSR_OP_NRM(fcvt.d.s, f7, f19, 0, 0, x3, 15*FLEN/8, x4, x1, x2)
inst_16:
// rs1==f24, rd==f20,fs1 == 1 and fe1 == 0x01 and fm1 == 0x000000 and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffffffff
/* opcode: fcvt.d.s ; op1:f24; dest:f20; op1val:0x8010000000000000; valaddr_reg:x3;
val_offset:16*FLEN/8; correctval:??; testreg:x2;
fcsr_val: 0 */
TEST_FPSR_OP_NRM(fcvt.d.s, f20, f24, 0, 0, x3, 16*FLEN/8, x4, x1, x2)
inst_17:
// rs1==f13, rd==f5,fs1 == 1 and fe1 == 0x01 and fm1 == 0x055555 and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffffffff
/* opcode: fcvt.d.s ; op1:f13; dest:f5; op1val:0x8010000000055555; valaddr_reg:x3;
val_offset:17*FLEN/8; correctval:??; testreg:x2;
fcsr_val: 0 */
TEST_FPSR_OP_NRM(fcvt.d.s, f5, f13, 0, 0, x3, 17*FLEN/8, x4, x1, x2)
inst_18:
// rs1==f12, rd==f21,fs1 == 1 and fe1 == 0x7f and fm1 == 0x000000 and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffffffff
/* opcode: fcvt.d.s ; op1:f12; dest:f21; op1val:0x87f0000000000000; valaddr_reg:x3;
val_offset:18*FLEN/8; correctval:??; testreg:x2;
fcsr_val: 0 */
TEST_FPSR_OP_NRM(fcvt.d.s, f21, f12, 0, 0, x3, 18*FLEN/8, x4, x1, x2)
inst_19:
// rs1==f21, rd==f16,fs1 == 1 and fe1 == 0xfe and fm1 == 0x7fffff and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffffffff
/* opcode: fcvt.d.s ; op1:f21; dest:f16; op1val:0x8fe00000007fffff; valaddr_reg:x3;
val_offset:19*FLEN/8; correctval:??; testreg:x2;
fcsr_val: 0 */
TEST_FPSR_OP_NRM(fcvt.d.s, f16, f21, 0, 0, x3, 19*FLEN/8, x4, x1, x2)
inst_20:
// rs1==f2, rd==f28,fs1 == 1 and fe1 == 0xff and fm1 == 0x000000 and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffffffff
/* opcode: fcvt.d.s ; op1:f2; dest:f28; op1val:0x8ff0000000000000; valaddr_reg:x3;
val_offset:20*FLEN/8; correctval:??; testreg:x2;
fcsr_val: 0 */
TEST_FPSR_OP_NRM(fcvt.d.s, f28, f2, 0, 0, x3, 20*FLEN/8, x4, x1, x2)
inst_21:
// rs1==f7, rd==f17,fs1 == 1 and fe1 == 0xff and fm1 == 0x2aaaaa and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffffffff
/* opcode: fcvt.d.s ; op1:f7; dest:f17; op1val:0x8ff00000002aaaaa; valaddr_reg:x3;
val_offset:21*FLEN/8; correctval:??; testreg:x2;
fcsr_val: 0 */
TEST_FPSR_OP_NRM(fcvt.d.s, f17, f7, 0, 0, x3, 21*FLEN/8, x4, x1, x2)
inst_22:
// rs1==f3, rd==f14,fs1 == 1 and fe1 == 0xff and fm1 == 0x400000 and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffffffff
/* opcode: fcvt.d.s ; op1:f3; dest:f14; op1val:0x8ff0000000400000; valaddr_reg:x3;
val_offset:22*FLEN/8; correctval:??; testreg:x2;
fcsr_val: 0 */
TEST_FPSR_OP_NRM(fcvt.d.s, f14, f3, 0, 0, x3, 22*FLEN/8, x4, x1, x2)
inst_23:
// rs1==f28, rd==f12,fs1 == 1 and fe1 == 0xff and fm1 == 0x455555 and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffffffff
/* opcode: fcvt.d.s ; op1:f28; dest:f12; op1val:0x8ff0000000455555; valaddr_reg:x3;
val_offset:23*FLEN/8; correctval:??; testreg:x2;
fcsr_val: 0 */
TEST_FPSR_OP_NRM(fcvt.d.s, f12, f28, 0, 0, x3, 23*FLEN/8, x4, x1, x2)
inst_24:
// rs1==f4, rd==f2,
/* opcode: fcvt.d.s ; op1:f4; dest:f2; op1val:0x0; valaddr_reg:x3;
val_offset:24*FLEN/8; correctval:??; testreg:x2;
fcsr_val: 0 */
TEST_FPSR_OP_NRM(fcvt.d.s, f2, f4, 0, 0, x3, 24*FLEN/8, x4, x1, x2)
inst_25:
// rs1==f26, rd==f3,
/* opcode: fcvt.d.s ; op1:f26; dest:f3; op1val:0x0; valaddr_reg:x3;
val_offset:25*FLEN/8; correctval:??; testreg:x2;
fcsr_val: 0 */
TEST_FPSR_OP_NRM(fcvt.d.s, f3, f26, 0, 0, x3, 25*FLEN/8, x4, x1, x2)
inst_26:
// rs1==f30, rd==f23,
/* opcode: fcvt.d.s ; op1:f30; dest:f23; op1val:0x0; valaddr_reg:x3;
val_offset:26*FLEN/8; correctval:??; testreg:x2;
fcsr_val: 0 */
TEST_FPSR_OP_NRM(fcvt.d.s, f23, f30, 0, 0, x3, 26*FLEN/8, x4, x1, x2)
inst_27:
// rs1==f1, rd==f8,
/* opcode: fcvt.d.s ; op1:f1; dest:f8; op1val:0x0; valaddr_reg:x3;
val_offset:27*FLEN/8; correctval:??; testreg:x2;
fcsr_val: 0 */
TEST_FPSR_OP_NRM(fcvt.d.s, f8, f1, 0, 0, x3, 27*FLEN/8, x4, x1, x2)
inst_28:
// rs1==f6, rd==f30,
/* opcode: fcvt.d.s ; op1:f6; dest:f30; op1val:0x0; valaddr_reg:x3;
val_offset:28*FLEN/8; correctval:??; testreg:x2;
fcsr_val: 0 */
TEST_FPSR_OP_NRM(fcvt.d.s, f30, f6, 0, 0, x3, 28*FLEN/8, x4, x1, x2)
inst_29:
// rs1==f18, rd==f19,
/* opcode: fcvt.d.s ; op1:f18; dest:f19; op1val:0x0; valaddr_reg:x3;
val_offset:29*FLEN/8; correctval:??; testreg:x2;
fcsr_val: 0 */
TEST_FPSR_OP_NRM(fcvt.d.s, f19, f18, 0, 0, x3, 29*FLEN/8, x4, x1, x2)
inst_30:
// rs1==f0, rd==f10,
/* opcode: fcvt.d.s ; op1:f0; dest:f10; op1val:0x0; valaddr_reg:x3;
val_offset:30*FLEN/8; correctval:??; testreg:x2;
fcsr_val: 0 */
TEST_FPSR_OP_NRM(fcvt.d.s, f10, f0, 0, 0, x3, 30*FLEN/8, x4, x1, x2)
inst_31:
// rs1==f23, rd==f31,
/* opcode: fcvt.d.s ; op1:f23; dest:f31; op1val:0x0; valaddr_reg:x3;
val_offset:31*FLEN/8; correctval:??; testreg:x2;
fcsr_val: 0 */
TEST_FPSR_OP_NRM(fcvt.d.s, f31, f23, 0, 0, x3, 31*FLEN/8, x4, x1, x2)
inst_32:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000000 and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffffffff
/* opcode: fcvt.d.s ; op1:f30; dest:f31; op1val:0x0; valaddr_reg:x3;
val_offset:32*FLEN/8; correctval:??; testreg:x2;
fcsr_val: 0 */
TEST_FPSR_OP_NRM(fcvt.d.s, f31, f30, 0, 0, x3, 32*FLEN/8, x4, x1, x2)
#endif
RVTEST_CODE_END
RVMODEL_HALT
RVTEST_DATA_BEGIN
.align 4
rvtest_data:
.word 0xbabecafe
.word 0xabecafeb
.word 0xbecafeba
.word 0xecafebab
test_dataset_0:
NAN_BOXED(0,64,FLEN)
NAN_BOXED(1,64,FLEN)
NAN_BOXED(2,64,FLEN)
NAN_BOXED(8388607,64,FLEN)
NAN_BOXED(4503599627370496,64,FLEN)
NAN_BOXED(4503599627370497,64,FLEN)
NAN_BOXED(571957152676052992,64,FLEN)
NAN_BOXED(1143914305360494591,64,FLEN)
NAN_BOXED(1148417904979476480,64,FLEN)
NAN_BOXED(1148417904979476481,64,FLEN)
NAN_BOXED(1148417904983670784,64,FLEN)
NAN_BOXED(1148417904983670785,64,FLEN)
NAN_BOXED(9223372036854775808,64,FLEN)
NAN_BOXED(9223372036854775809,64,FLEN)
NAN_BOXED(9223372036863164414,64,FLEN)
NAN_BOXED(9223372036863164415,64,FLEN)
NAN_BOXED(9227875636482146304,64,FLEN)
NAN_BOXED(9227875636482495829,64,FLEN)
NAN_BOXED(9795329189530828800,64,FLEN)
NAN_BOXED(10367286342215270399,64,FLEN)
NAN_BOXED(10371789941834252288,64,FLEN)
NAN_BOXED(10371789941837048490,64,FLEN)
NAN_BOXED(10371789941838446592,64,FLEN)
NAN_BOXED(10371789941838796117,64,FLEN)
NAN_BOXED(0,64,FLEN)
NAN_BOXED(0,64,FLEN)
NAN_BOXED(0,64,FLEN)
NAN_BOXED(0,64,FLEN)
NAN_BOXED(0,64,FLEN)
NAN_BOXED(0,64,FLEN)
NAN_BOXED(0,64,FLEN)
NAN_BOXED(0,64,FLEN)
NAN_BOXED(0,64,FLEN)
RVTEST_DATA_END
RVMODEL_DATA_BEGIN
rvtest_sig_begin:
sig_begin_canary:
CANARY;
signature_x1_0:
.fill 0*((SIGALIGN)/4),4,0xdeadbeef
signature_x1_1:
.fill 66*((SIGALIGN)/4),4,0xdeadbeef
#ifdef rvtest_mtrap_routine
tsig_begin_canary:
CANARY;
tsig_begin_canary:
CANARY;
mtrap_sigptr:
.fill 64*(XLEN/32),4,0xdeadbeef
tsig_end_canary:
CANARY;
tsig_end_canary:
CANARY;
#endif
#ifdef rvtest_gpr_save
gpr_save:
.fill 32*XLEN/32,4,0xdeadbeef
#endif
sig_end_canary:
CANARY;
rvtest_sig_end:
RVMODEL_DATA_END

356
vendor/riscv-arch-tests/riscv-test-suite/rv32i_m/D/src/fcvt.d.s_b22-01.S vendored
View file

@ -1,356 +0,0 @@
// -----------
// This file was generated by riscv_ctg (https://github.com/riscv-software-src/riscv-ctg)
// version : 0.7.1
// timestamp : Fri Jun 17 14:03:32 2022 GMT
// usage : riscv_ctg \
// -- cgf // --cgf /scratch/pawan/work/normalised/RV32D/fcvt.d.s.cgf \
\
// -- xlen 32 \
// --randomize \
// -----------
//
// -----------
// Copyright (c) 2020. RISC-V International. All rights reserved.
// SPDX-License-Identifier: BSD-3-Clause
// -----------
//
// This assembly file tests the fcvt.d.s instruction of the RISC-V RV32FD_Zicsr,RV64FD_Zicsr extension for the fcvt.d.s_b22 covergroup.
//
#include "model_test.h"
#include "arch_test.h"
RVTEST_ISA("RV32IFD_Zicsr,RV64IFD_Zicsr")
.section .text.init
.org 0x80
.globl rvtest_entry_point
rvtest_entry_point:
RVMODEL_BOOT
RVTEST_CODE_BEGIN
#ifdef TEST_CASE_1
RVTEST_CASE(0,"//check ISA:=regex(.*I.*D.*);def TEST_CASE_1=True;",fcvt.d.s_b22)
RVTEST_FP_ENABLE()
RVTEST_VALBASEUPD(x3,test_dataset_0)
RVTEST_SIGBASE(x1,signature_x1_1)
inst_0:
// rs1 == rd, rs1==f14, rd==f14,fs1 == 0 and fe1 == 0x67 and fm1 == 0x53a4fc and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffffffff
/* opcode: fcvt.d.s ; op1:f14; dest:f14; op1val:0x67000000053a4fc; valaddr_reg:x3;
val_offset:0*FLEN/8; correctval:??; testreg:x2;
fcsr_val: 0 */
TEST_FPSR_OP_NRM(fcvt.d.s, f14, f14, 0, 0, x3, 0*FLEN/8, x4, x1, x2)
inst_1:
// rs1 != rd, rs1==f7, rd==f26,fs1 == 0 and fe1 == 0x7c and fm1 == 0x4923b8 and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffffffff
/* opcode: fcvt.d.s ; op1:f7; dest:f26; op1val:0x7c00000004923b8; valaddr_reg:x3;
val_offset:1*FLEN/8; correctval:??; testreg:x2;
fcsr_val: 0 */
TEST_FPSR_OP_NRM(fcvt.d.s, f26, f7, 0, 0, x3, 1*FLEN/8, x4, x1, x2)
inst_2:
// rs1==f30, rd==f29,fs1 == 0 and fe1 == 0x7d and fm1 == 0x36e5d6 and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffffffff
/* opcode: fcvt.d.s ; op1:f30; dest:f29; op1val:0x7d000000036e5d6; valaddr_reg:x3;
val_offset:2*FLEN/8; correctval:??; testreg:x2;
fcsr_val: 0 */
TEST_FPSR_OP_NRM(fcvt.d.s, f29, f30, 0, 0, x3, 2*FLEN/8, x4, x1, x2)
inst_3:
// rs1==f9, rd==f25,fs1 == 0 and fe1 == 0x7e and fm1 == 0x49fee5 and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffffffff
/* opcode: fcvt.d.s ; op1:f9; dest:f25; op1val:0x7e000000049fee5; valaddr_reg:x3;
val_offset:3*FLEN/8; correctval:??; testreg:x2;
fcsr_val: 0 */
TEST_FPSR_OP_NRM(fcvt.d.s, f25, f9, 0, 0, x3, 3*FLEN/8, x4, x1, x2)
inst_4:
// rs1==f23, rd==f1,fs1 == 0 and fe1 == 0x7f and fm1 == 0x1a616d and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffffffff
/* opcode: fcvt.d.s ; op1:f23; dest:f1; op1val:0x7f00000001a616d; valaddr_reg:x3;
val_offset:4*FLEN/8; correctval:??; testreg:x2;
fcsr_val: 0 */
TEST_FPSR_OP_NRM(fcvt.d.s, f1, f23, 0, 0, x3, 4*FLEN/8, x4, x1, x2)
inst_5:
// rs1==f21, rd==f3,fs1 == 0 and fe1 == 0x80 and fm1 == 0x681ae9 and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffffffff
/* opcode: fcvt.d.s ; op1:f21; dest:f3; op1val:0x800000000681ae9; valaddr_reg:x3;
val_offset:5*FLEN/8; correctval:??; testreg:x2;
fcsr_val: 0 */
TEST_FPSR_OP_NRM(fcvt.d.s, f3, f21, 0, 0, x3, 5*FLEN/8, x4, x1, x2)
inst_6:
// rs1==f15, rd==f8,fs1 == 0 and fe1 == 0x81 and fm1 == 0x696b5c and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffffffff
/* opcode: fcvt.d.s ; op1:f15; dest:f8; op1val:0x810000000696b5c; valaddr_reg:x3;
val_offset:6*FLEN/8; correctval:??; testreg:x2;
fcsr_val: 0 */
TEST_FPSR_OP_NRM(fcvt.d.s, f8, f15, 0, 0, x3, 6*FLEN/8, x4, x1, x2)
inst_7:
// rs1==f17, rd==f6,fs1 == 0 and fe1 == 0xc4 and fm1 == 0x046756 and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffffffff
/* opcode: fcvt.d.s ; op1:f17; dest:f6; op1val:0xc40000000046756; valaddr_reg:x3;
val_offset:7*FLEN/8; correctval:??; testreg:x2;
fcsr_val: 0 */
TEST_FPSR_OP_NRM(fcvt.d.s, f6, f17, 0, 0, x3, 7*FLEN/8, x4, x1, x2)
inst_8:
// rs1==f18, rd==f27,
/* opcode: fcvt.d.s ; op1:f18; dest:f27; op1val:0x0; valaddr_reg:x3;
val_offset:8*FLEN/8; correctval:??; testreg:x2;
fcsr_val: 0 */
TEST_FPSR_OP_NRM(fcvt.d.s, f27, f18, 0, 0, x3, 8*FLEN/8, x4, x1, x2)
inst_9:
// rs1==f28, rd==f9,
/* opcode: fcvt.d.s ; op1:f28; dest:f9; op1val:0x0; valaddr_reg:x3;
val_offset:9*FLEN/8; correctval:??; testreg:x2;
fcsr_val: 0 */
TEST_FPSR_OP_NRM(fcvt.d.s, f9, f28, 0, 0, x3, 9*FLEN/8, x4, x1, x2)
inst_10:
// rs1==f16, rd==f12,
/* opcode: fcvt.d.s ; op1:f16; dest:f12; op1val:0x0; valaddr_reg:x3;
val_offset:10*FLEN/8; correctval:??; testreg:x2;
fcsr_val: 0 */
TEST_FPSR_OP_NRM(fcvt.d.s, f12, f16, 0, 0, x3, 10*FLEN/8, x4, x1, x2)
inst_11:
// rs1==f29, rd==f13,
/* opcode: fcvt.d.s ; op1:f29; dest:f13; op1val:0x0; valaddr_reg:x3;
val_offset:11*FLEN/8; correctval:??; testreg:x2;
fcsr_val: 0 */
TEST_FPSR_OP_NRM(fcvt.d.s, f13, f29, 0, 0, x3, 11*FLEN/8, x4, x1, x2)
inst_12:
// rs1==f10, rd==f20,
/* opcode: fcvt.d.s ; op1:f10; dest:f20; op1val:0x0; valaddr_reg:x3;
val_offset:12*FLEN/8; correctval:??; testreg:x2;
fcsr_val: 0 */
TEST_FPSR_OP_NRM(fcvt.d.s, f20, f10, 0, 0, x3, 12*FLEN/8, x4, x1, x2)
inst_13:
// rs1==f25, rd==f18,
/* opcode: fcvt.d.s ; op1:f25; dest:f18; op1val:0x0; valaddr_reg:x3;
val_offset:13*FLEN/8; correctval:??; testreg:x2;
fcsr_val: 0 */
TEST_FPSR_OP_NRM(fcvt.d.s, f18, f25, 0, 0, x3, 13*FLEN/8, x4, x1, x2)
inst_14:
// rs1==f6, rd==f23,
/* opcode: fcvt.d.s ; op1:f6; dest:f23; op1val:0x0; valaddr_reg:x3;
val_offset:14*FLEN/8; correctval:??; testreg:x2;
fcsr_val: 0 */
TEST_FPSR_OP_NRM(fcvt.d.s, f23, f6, 0, 0, x3, 14*FLEN/8, x4, x1, x2)
inst_15:
// rs1==f24, rd==f10,
/* opcode: fcvt.d.s ; op1:f24; dest:f10; op1val:0x0; valaddr_reg:x3;
val_offset:15*FLEN/8; correctval:??; testreg:x2;
fcsr_val: 0 */
TEST_FPSR_OP_NRM(fcvt.d.s, f10, f24, 0, 0, x3, 15*FLEN/8, x4, x1, x2)
inst_16:
// rs1==f5, rd==f4,
/* opcode: fcvt.d.s ; op1:f5; dest:f4; op1val:0x0; valaddr_reg:x3;
val_offset:16*FLEN/8; correctval:??; testreg:x2;
fcsr_val: 0 */
TEST_FPSR_OP_NRM(fcvt.d.s, f4, f5, 0, 0, x3, 16*FLEN/8, x4, x1, x2)
inst_17:
// rs1==f8, rd==f19,
/* opcode: fcvt.d.s ; op1:f8; dest:f19; op1val:0x0; valaddr_reg:x3;
val_offset:17*FLEN/8; correctval:??; testreg:x2;
fcsr_val: 0 */
TEST_FPSR_OP_NRM(fcvt.d.s, f19, f8, 0, 0, x3, 17*FLEN/8, x4, x1, x2)
inst_18:
// rs1==f2, rd==f0,
/* opcode: fcvt.d.s ; op1:f2; dest:f0; op1val:0x0; valaddr_reg:x3;
val_offset:18*FLEN/8; correctval:??; testreg:x2;
fcsr_val: 0 */
TEST_FPSR_OP_NRM(fcvt.d.s, f0, f2, 0, 0, x3, 18*FLEN/8, x4, x1, x2)
inst_19:
// rs1==f0, rd==f11,
/* opcode: fcvt.d.s ; op1:f0; dest:f11; op1val:0x0; valaddr_reg:x3;
val_offset:19*FLEN/8; correctval:??; testreg:x2;
fcsr_val: 0 */
TEST_FPSR_OP_NRM(fcvt.d.s, f11, f0, 0, 0, x3, 19*FLEN/8, x4, x1, x2)
inst_20:
// rs1==f4, rd==f7,
/* opcode: fcvt.d.s ; op1:f4; dest:f7; op1val:0x0; valaddr_reg:x3;
val_offset:20*FLEN/8; correctval:??; testreg:x2;
fcsr_val: 0 */
TEST_FPSR_OP_NRM(fcvt.d.s, f7, f4, 0, 0, x3, 20*FLEN/8, x4, x1, x2)
inst_21:
// rs1==f20, rd==f22,
/* opcode: fcvt.d.s ; op1:f20; dest:f22; op1val:0x0; valaddr_reg:x3;
val_offset:21*FLEN/8; correctval:??; testreg:x2;
fcsr_val: 0 */
TEST_FPSR_OP_NRM(fcvt.d.s, f22, f20, 0, 0, x3, 21*FLEN/8, x4, x1, x2)
inst_22:
// rs1==f3, rd==f17,
/* opcode: fcvt.d.s ; op1:f3; dest:f17; op1val:0x0; valaddr_reg:x3;
val_offset:22*FLEN/8; correctval:??; testreg:x2;
fcsr_val: 0 */
TEST_FPSR_OP_NRM(fcvt.d.s, f17, f3, 0, 0, x3, 22*FLEN/8, x4, x1, x2)
inst_23:
// rs1==f27, rd==f31,
/* opcode: fcvt.d.s ; op1:f27; dest:f31; op1val:0x0; valaddr_reg:x3;
val_offset:23*FLEN/8; correctval:??; testreg:x2;
fcsr_val: 0 */
TEST_FPSR_OP_NRM(fcvt.d.s, f31, f27, 0, 0, x3, 23*FLEN/8, x4, x1, x2)
inst_24:
// rs1==f31, rd==f21,
/* opcode: fcvt.d.s ; op1:f31; dest:f21; op1val:0x0; valaddr_reg:x3;
val_offset:24*FLEN/8; correctval:??; testreg:x2;
fcsr_val: 0 */
TEST_FPSR_OP_NRM(fcvt.d.s, f21, f31, 0, 0, x3, 24*FLEN/8, x4, x1, x2)
inst_25:
// rs1==f19, rd==f5,
/* opcode: fcvt.d.s ; op1:f19; dest:f5; op1val:0x0; valaddr_reg:x3;
val_offset:25*FLEN/8; correctval:??; testreg:x2;
fcsr_val: 0 */
TEST_FPSR_OP_NRM(fcvt.d.s, f5, f19, 0, 0, x3, 25*FLEN/8, x4, x1, x2)
inst_26:
// rs1==f1, rd==f24,
/* opcode: fcvt.d.s ; op1:f1; dest:f24; op1val:0x0; valaddr_reg:x3;
val_offset:26*FLEN/8; correctval:??; testreg:x2;
fcsr_val: 0 */
TEST_FPSR_OP_NRM(fcvt.d.s, f24, f1, 0, 0, x3, 26*FLEN/8, x4, x1, x2)
inst_27:
// rs1==f13, rd==f2,
/* opcode: fcvt.d.s ; op1:f13; dest:f2; op1val:0x0; valaddr_reg:x3;
val_offset:27*FLEN/8; correctval:??; testreg:x2;
fcsr_val: 0 */
TEST_FPSR_OP_NRM(fcvt.d.s, f2, f13, 0, 0, x3, 27*FLEN/8, x4, x1, x2)
inst_28:
// rs1==f26, rd==f28,
/* opcode: fcvt.d.s ; op1:f26; dest:f28; op1val:0x0; valaddr_reg:x3;
val_offset:28*FLEN/8; correctval:??; testreg:x2;
fcsr_val: 0 */
TEST_FPSR_OP_NRM(fcvt.d.s, f28, f26, 0, 0, x3, 28*FLEN/8, x4, x1, x2)
inst_29:
// rs1==f12, rd==f15,
/* opcode: fcvt.d.s ; op1:f12; dest:f15; op1val:0x0; valaddr_reg:x3;
val_offset:29*FLEN/8; correctval:??; testreg:x2;
fcsr_val: 0 */
TEST_FPSR_OP_NRM(fcvt.d.s, f15, f12, 0, 0, x3, 29*FLEN/8, x4, x1, x2)
inst_30:
// rs1==f11, rd==f16,
/* opcode: fcvt.d.s ; op1:f11; dest:f16; op1val:0x0; valaddr_reg:x3;
val_offset:30*FLEN/8; correctval:??; testreg:x2;
fcsr_val: 0 */
TEST_FPSR_OP_NRM(fcvt.d.s, f16, f11, 0, 0, x3, 30*FLEN/8, x4, x1, x2)
inst_31:
// rs1==f22, rd==f30,
/* opcode: fcvt.d.s ; op1:f22; dest:f30; op1val:0x0; valaddr_reg:x3;
val_offset:31*FLEN/8; correctval:??; testreg:x2;
fcsr_val: 0 */
TEST_FPSR_OP_NRM(fcvt.d.s, f30, f22, 0, 0, x3, 31*FLEN/8, x4, x1, x2)
inst_32:
// fs1 == 0 and fe1 == 0x67 and fm1 == 0x53a4fc and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffffffff
/* opcode: fcvt.d.s ; op1:f30; dest:f31; op1val:0x67000000053a4fc; valaddr_reg:x3;
val_offset:32*FLEN/8; correctval:??; testreg:x2;
fcsr_val: 0 */
TEST_FPSR_OP_NRM(fcvt.d.s, f31, f30, 0, 0, x3, 32*FLEN/8, x4, x1, x2)
#endif
RVTEST_CODE_END
RVMODEL_HALT
RVTEST_DATA_BEGIN
.align 4
rvtest_data:
.word 0xbabecafe
.word 0xabecafeb
.word 0xbecafeba
.word 0xecafebab
test_dataset_0:
NAN_BOXED(463870761624642812,64,FLEN)
NAN_BOXED(558446353798734776,64,FLEN)
NAN_BOXED(562949953424909782,64,FLEN)
NAN_BOXED(567453553053531877,64,FLEN)
NAN_BOXED(571957152677781869,64,FLEN)
NAN_BOXED(576460752310246121,64,FLEN)
NAN_BOXED(580964351937702748,64,FLEN)
NAN_BOXED(882705526964905814,64,FLEN)
NAN_BOXED(0,64,FLEN)
NAN_BOXED(0,64,FLEN)
NAN_BOXED(0,64,FLEN)
NAN_BOXED(0,64,FLEN)
NAN_BOXED(0,64,FLEN)
NAN_BOXED(0,64,FLEN)
NAN_BOXED(0,64,FLEN)
NAN_BOXED(0,64,FLEN)
NAN_BOXED(0,64,FLEN)
NAN_BOXED(0,64,FLEN)
NAN_BOXED(0,64,FLEN)
NAN_BOXED(0,64,FLEN)
NAN_BOXED(0,64,FLEN)
NAN_BOXED(0,64,FLEN)
NAN_BOXED(0,64,FLEN)
NAN_BOXED(0,64,FLEN)
NAN_BOXED(0,64,FLEN)
NAN_BOXED(0,64,FLEN)
NAN_BOXED(0,64,FLEN)
NAN_BOXED(0,64,FLEN)
NAN_BOXED(0,64,FLEN)
NAN_BOXED(0,64,FLEN)
NAN_BOXED(0,64,FLEN)
NAN_BOXED(0,64,FLEN)
NAN_BOXED(463870761624642812,64,FLEN)
RVTEST_DATA_END
RVMODEL_DATA_BEGIN
rvtest_sig_begin:
sig_begin_canary:
CANARY;
signature_x1_0:
.fill 0*((SIGALIGN)/4),4,0xdeadbeef
signature_x1_1:
.fill 66*((SIGALIGN)/4),4,0xdeadbeef
#ifdef rvtest_mtrap_routine
tsig_begin_canary:
CANARY;
tsig_begin_canary:
CANARY;
mtrap_sigptr:
.fill 64*(XLEN/32),4,0xdeadbeef
tsig_end_canary:
CANARY;
tsig_end_canary:
CANARY;
#endif
#ifdef rvtest_gpr_save
gpr_save:
.fill 32*XLEN/32,4,0xdeadbeef
#endif
sig_end_canary:
CANARY;
rvtest_sig_end:
RVMODEL_DATA_END

356
vendor/riscv-arch-tests/riscv-test-suite/rv32i_m/D/src/fcvt.d.s_b23-01.S vendored
View file

@ -1,356 +0,0 @@
// -----------
// This file was generated by riscv_ctg (https://github.com/riscv-software-src/riscv-ctg)
// version : 0.7.1
// timestamp : Fri Jun 17 14:03:32 2022 GMT
// usage : riscv_ctg \
// -- cgf // --cgf /scratch/pawan/work/normalised/RV32D/fcvt.d.s.cgf \
\
// -- xlen 32 \
// --randomize \
// -----------
//
// -----------
// Copyright (c) 2020. RISC-V International. All rights reserved.
// SPDX-License-Identifier: BSD-3-Clause
// -----------
//
// This assembly file tests the fcvt.d.s instruction of the RISC-V RV32FD_Zicsr,RV64FD_Zicsr extension for the fcvt.d.s_b23 covergroup.
//
#include "model_test.h"
#include "arch_test.h"
RVTEST_ISA("RV32IFD_Zicsr,RV64IFD_Zicsr")
.section .text.init
.org 0x80
.globl rvtest_entry_point
rvtest_entry_point:
RVMODEL_BOOT
RVTEST_CODE_BEGIN
#ifdef TEST_CASE_1
RVTEST_CASE(0,"//check ISA:=regex(.*I.*D.*);def TEST_CASE_1=True;",fcvt.d.s_b23)
RVTEST_FP_ENABLE()
RVTEST_VALBASEUPD(x3,test_dataset_0)
RVTEST_SIGBASE(x1,signature_x1_1)
inst_0:
// rs1 == rd, rs1==f14, rd==f14,fs1 == 0 and fe1 == 0x9d and fm1 == 0x7ffffc and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffffffff
/* opcode: fcvt.d.s ; op1:f14; dest:f14; op1val:0x9d00000007ffffc; valaddr_reg:x3;
val_offset:0*FLEN/8; correctval:??; testreg:x2;
fcsr_val: 0 */
TEST_FPSR_OP_NRM(fcvt.d.s, f14, f14, 0, 0, x3, 0*FLEN/8, x4, x1, x2)
inst_1:
// rs1 != rd, rs1==f5, rd==f9,fs1 == 0 and fe1 == 0x9d and fm1 == 0x7ffffd and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffffffff
/* opcode: fcvt.d.s ; op1:f5; dest:f9; op1val:0x9d00000007ffffd; valaddr_reg:x3;
val_offset:1*FLEN/8; correctval:??; testreg:x2;
fcsr_val: 0 */
TEST_FPSR_OP_NRM(fcvt.d.s, f9, f5, 0, 0, x3, 1*FLEN/8, x4, x1, x2)
inst_2:
// rs1==f10, rd==f28,fs1 == 0 and fe1 == 0x9d and fm1 == 0x7ffffe and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffffffff
/* opcode: fcvt.d.s ; op1:f10; dest:f28; op1val:0x9d00000007ffffe; valaddr_reg:x3;
val_offset:2*FLEN/8; correctval:??; testreg:x2;
fcsr_val: 0 */
TEST_FPSR_OP_NRM(fcvt.d.s, f28, f10, 0, 0, x3, 2*FLEN/8, x4, x1, x2)
inst_3:
// rs1==f3, rd==f22,fs1 == 0 and fe1 == 0x9d and fm1 == 0x7fffff and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffffffff
/* opcode: fcvt.d.s ; op1:f3; dest:f22; op1val:0x9d00000007fffff; valaddr_reg:x3;
val_offset:3*FLEN/8; correctval:??; testreg:x2;
fcsr_val: 0 */
TEST_FPSR_OP_NRM(fcvt.d.s, f22, f3, 0, 0, x3, 3*FLEN/8, x4, x1, x2)
inst_4:
// rs1==f30, rd==f24,fs1 == 0 and fe1 == 0x9e and fm1 == 0x000000 and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffffffff
/* opcode: fcvt.d.s ; op1:f30; dest:f24; op1val:0x9e0000000000000; valaddr_reg:x3;
val_offset:4*FLEN/8; correctval:??; testreg:x2;
fcsr_val: 0 */
TEST_FPSR_OP_NRM(fcvt.d.s, f24, f30, 0, 0, x3, 4*FLEN/8, x4, x1, x2)
inst_5:
// rs1==f18, rd==f30,fs1 == 0 and fe1 == 0x9e and fm1 == 0x000001 and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffffffff
/* opcode: fcvt.d.s ; op1:f18; dest:f30; op1val:0x9e0000000000001; valaddr_reg:x3;
val_offset:5*FLEN/8; correctval:??; testreg:x2;
fcsr_val: 0 */
TEST_FPSR_OP_NRM(fcvt.d.s, f30, f18, 0, 0, x3, 5*FLEN/8, x4, x1, x2)
inst_6:
// rs1==f29, rd==f2,fs1 == 0 and fe1 == 0x9e and fm1 == 0x000002 and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffffffff
/* opcode: fcvt.d.s ; op1:f29; dest:f2; op1val:0x9e0000000000002; valaddr_reg:x3;
val_offset:6*FLEN/8; correctval:??; testreg:x2;
fcsr_val: 0 */
TEST_FPSR_OP_NRM(fcvt.d.s, f2, f29, 0, 0, x3, 6*FLEN/8, x4, x1, x2)
inst_7:
// rs1==f23, rd==f27,fs1 == 0 and fe1 == 0x9e and fm1 == 0x000003 and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffffffff
/* opcode: fcvt.d.s ; op1:f23; dest:f27; op1val:0x9e0000000000003; valaddr_reg:x3;
val_offset:7*FLEN/8; correctval:??; testreg:x2;
fcsr_val: 0 */
TEST_FPSR_OP_NRM(fcvt.d.s, f27, f23, 0, 0, x3, 7*FLEN/8, x4, x1, x2)
inst_8:
// rs1==f17, rd==f4,fs1 == 0 and fe1 == 0x9e and fm1 == 0x000004 and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffffffff
/* opcode: fcvt.d.s ; op1:f17; dest:f4; op1val:0x9e0000000000004; valaddr_reg:x3;
val_offset:8*FLEN/8; correctval:??; testreg:x2;
fcsr_val: 0 */
TEST_FPSR_OP_NRM(fcvt.d.s, f4, f17, 0, 0, x3, 8*FLEN/8, x4, x1, x2)
inst_9:
// rs1==f22, rd==f31,
/* opcode: fcvt.d.s ; op1:f22; dest:f31; op1val:0x0; valaddr_reg:x3;
val_offset:9*FLEN/8; correctval:??; testreg:x2;
fcsr_val: 0 */
TEST_FPSR_OP_NRM(fcvt.d.s, f31, f22, 0, 0, x3, 9*FLEN/8, x4, x1, x2)
inst_10:
// rs1==f9, rd==f17,
/* opcode: fcvt.d.s ; op1:f9; dest:f17; op1val:0x0; valaddr_reg:x3;
val_offset:10*FLEN/8; correctval:??; testreg:x2;
fcsr_val: 0 */
TEST_FPSR_OP_NRM(fcvt.d.s, f17, f9, 0, 0, x3, 10*FLEN/8, x4, x1, x2)
inst_11:
// rs1==f0, rd==f6,
/* opcode: fcvt.d.s ; op1:f0; dest:f6; op1val:0x0; valaddr_reg:x3;
val_offset:11*FLEN/8; correctval:??; testreg:x2;
fcsr_val: 0 */
TEST_FPSR_OP_NRM(fcvt.d.s, f6, f0, 0, 0, x3, 11*FLEN/8, x4, x1, x2)
inst_12:
// rs1==f4, rd==f18,
/* opcode: fcvt.d.s ; op1:f4; dest:f18; op1val:0x0; valaddr_reg:x3;
val_offset:12*FLEN/8; correctval:??; testreg:x2;
fcsr_val: 0 */
TEST_FPSR_OP_NRM(fcvt.d.s, f18, f4, 0, 0, x3, 12*FLEN/8, x4, x1, x2)
inst_13:
// rs1==f31, rd==f13,
/* opcode: fcvt.d.s ; op1:f31; dest:f13; op1val:0x0; valaddr_reg:x3;
val_offset:13*FLEN/8; correctval:??; testreg:x2;
fcsr_val: 0 */
TEST_FPSR_OP_NRM(fcvt.d.s, f13, f31, 0, 0, x3, 13*FLEN/8, x4, x1, x2)
inst_14:
// rs1==f13, rd==f1,
/* opcode: fcvt.d.s ; op1:f13; dest:f1; op1val:0x0; valaddr_reg:x3;
val_offset:14*FLEN/8; correctval:??; testreg:x2;
fcsr_val: 0 */
TEST_FPSR_OP_NRM(fcvt.d.s, f1, f13, 0, 0, x3, 14*FLEN/8, x4, x1, x2)
inst_15:
// rs1==f20, rd==f16,
/* opcode: fcvt.d.s ; op1:f20; dest:f16; op1val:0x0; valaddr_reg:x3;
val_offset:15*FLEN/8; correctval:??; testreg:x2;
fcsr_val: 0 */
TEST_FPSR_OP_NRM(fcvt.d.s, f16, f20, 0, 0, x3, 15*FLEN/8, x4, x1, x2)
inst_16:
// rs1==f2, rd==f0,
/* opcode: fcvt.d.s ; op1:f2; dest:f0; op1val:0x0; valaddr_reg:x3;
val_offset:16*FLEN/8; correctval:??; testreg:x2;
fcsr_val: 0 */
TEST_FPSR_OP_NRM(fcvt.d.s, f0, f2, 0, 0, x3, 16*FLEN/8, x4, x1, x2)
inst_17:
// rs1==f7, rd==f8,
/* opcode: fcvt.d.s ; op1:f7; dest:f8; op1val:0x0; valaddr_reg:x3;
val_offset:17*FLEN/8; correctval:??; testreg:x2;
fcsr_val: 0 */
TEST_FPSR_OP_NRM(fcvt.d.s, f8, f7, 0, 0, x3, 17*FLEN/8, x4, x1, x2)
inst_18:
// rs1==f15, rd==f7,
/* opcode: fcvt.d.s ; op1:f15; dest:f7; op1val:0x0; valaddr_reg:x3;
val_offset:18*FLEN/8; correctval:??; testreg:x2;
fcsr_val: 0 */
TEST_FPSR_OP_NRM(fcvt.d.s, f7, f15, 0, 0, x3, 18*FLEN/8, x4, x1, x2)
inst_19:
// rs1==f26, rd==f20,
/* opcode: fcvt.d.s ; op1:f26; dest:f20; op1val:0x0; valaddr_reg:x3;
val_offset:19*FLEN/8; correctval:??; testreg:x2;
fcsr_val: 0 */
TEST_FPSR_OP_NRM(fcvt.d.s, f20, f26, 0, 0, x3, 19*FLEN/8, x4, x1, x2)
inst_20:
// rs1==f12, rd==f10,
/* opcode: fcvt.d.s ; op1:f12; dest:f10; op1val:0x0; valaddr_reg:x3;
val_offset:20*FLEN/8; correctval:??; testreg:x2;
fcsr_val: 0 */
TEST_FPSR_OP_NRM(fcvt.d.s, f10, f12, 0, 0, x3, 20*FLEN/8, x4, x1, x2)
inst_21:
// rs1==f28, rd==f29,
/* opcode: fcvt.d.s ; op1:f28; dest:f29; op1val:0x0; valaddr_reg:x3;
val_offset:21*FLEN/8; correctval:??; testreg:x2;
fcsr_val: 0 */
TEST_FPSR_OP_NRM(fcvt.d.s, f29, f28, 0, 0, x3, 21*FLEN/8, x4, x1, x2)
inst_22:
// rs1==f16, rd==f19,
/* opcode: fcvt.d.s ; op1:f16; dest:f19; op1val:0x0; valaddr_reg:x3;
val_offset:22*FLEN/8; correctval:??; testreg:x2;
fcsr_val: 0 */
TEST_FPSR_OP_NRM(fcvt.d.s, f19, f16, 0, 0, x3, 22*FLEN/8, x4, x1, x2)
inst_23:
// rs1==f6, rd==f12,
/* opcode: fcvt.d.s ; op1:f6; dest:f12; op1val:0x0; valaddr_reg:x3;
val_offset:23*FLEN/8; correctval:??; testreg:x2;
fcsr_val: 0 */
TEST_FPSR_OP_NRM(fcvt.d.s, f12, f6, 0, 0, x3, 23*FLEN/8, x4, x1, x2)
inst_24:
// rs1==f8, rd==f21,
/* opcode: fcvt.d.s ; op1:f8; dest:f21; op1val:0x0; valaddr_reg:x3;
val_offset:24*FLEN/8; correctval:??; testreg:x2;
fcsr_val: 0 */
TEST_FPSR_OP_NRM(fcvt.d.s, f21, f8, 0, 0, x3, 24*FLEN/8, x4, x1, x2)
inst_25:
// rs1==f27, rd==f3,
/* opcode: fcvt.d.s ; op1:f27; dest:f3; op1val:0x0; valaddr_reg:x3;
val_offset:25*FLEN/8; correctval:??; testreg:x2;
fcsr_val: 0 */
TEST_FPSR_OP_NRM(fcvt.d.s, f3, f27, 0, 0, x3, 25*FLEN/8, x4, x1, x2)
inst_26:
// rs1==f24, rd==f5,
/* opcode: fcvt.d.s ; op1:f24; dest:f5; op1val:0x0; valaddr_reg:x3;
val_offset:26*FLEN/8; correctval:??; testreg:x2;
fcsr_val: 0 */
TEST_FPSR_OP_NRM(fcvt.d.s, f5, f24, 0, 0, x3, 26*FLEN/8, x4, x1, x2)
inst_27:
// rs1==f19, rd==f25,
/* opcode: fcvt.d.s ; op1:f19; dest:f25; op1val:0x0; valaddr_reg:x3;
val_offset:27*FLEN/8; correctval:??; testreg:x2;
fcsr_val: 0 */
TEST_FPSR_OP_NRM(fcvt.d.s, f25, f19, 0, 0, x3, 27*FLEN/8, x4, x1, x2)
inst_28:
// rs1==f1, rd==f15,
/* opcode: fcvt.d.s ; op1:f1; dest:f15; op1val:0x0; valaddr_reg:x3;
val_offset:28*FLEN/8; correctval:??; testreg:x2;
fcsr_val: 0 */
TEST_FPSR_OP_NRM(fcvt.d.s, f15, f1, 0, 0, x3, 28*FLEN/8, x4, x1, x2)
inst_29:
// rs1==f11, rd==f26,
/* opcode: fcvt.d.s ; op1:f11; dest:f26; op1val:0x0; valaddr_reg:x3;
val_offset:29*FLEN/8; correctval:??; testreg:x2;
fcsr_val: 0 */
TEST_FPSR_OP_NRM(fcvt.d.s, f26, f11, 0, 0, x3, 29*FLEN/8, x4, x1, x2)
inst_30:
// rs1==f25, rd==f11,
/* opcode: fcvt.d.s ; op1:f25; dest:f11; op1val:0x0; valaddr_reg:x3;
val_offset:30*FLEN/8; correctval:??; testreg:x2;
fcsr_val: 0 */
TEST_FPSR_OP_NRM(fcvt.d.s, f11, f25, 0, 0, x3, 30*FLEN/8, x4, x1, x2)
inst_31:
// rs1==f21, rd==f23,
/* opcode: fcvt.d.s ; op1:f21; dest:f23; op1val:0x0; valaddr_reg:x3;
val_offset:31*FLEN/8; correctval:??; testreg:x2;
fcsr_val: 0 */
TEST_FPSR_OP_NRM(fcvt.d.s, f23, f21, 0, 0, x3, 31*FLEN/8, x4, x1, x2)
inst_32:
// fs1 == 0 and fe1 == 0x9d and fm1 == 0x7ffffc and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffffffff
/* opcode: fcvt.d.s ; op1:f30; dest:f31; op1val:0x9d00000007ffffc; valaddr_reg:x3;
val_offset:32*FLEN/8; correctval:??; testreg:x2;
fcsr_val: 0 */
TEST_FPSR_OP_NRM(fcvt.d.s, f31, f30, 0, 0, x3, 32*FLEN/8, x4, x1, x2)
#endif
RVTEST_CODE_END
RVMODEL_HALT
RVTEST_DATA_BEGIN
.align 4
rvtest_data:
.word 0xbabecafe
.word 0xabecafeb
.word 0xbecafeba
.word 0xecafebab
test_dataset_0:
NAN_BOXED(707065141505556476,64,FLEN)
NAN_BOXED(707065141505556477,64,FLEN)
NAN_BOXED(707065141505556478,64,FLEN)
NAN_BOXED(707065141505556479,64,FLEN)
NAN_BOXED(711568741124538368,64,FLEN)
NAN_BOXED(711568741124538369,64,FLEN)
NAN_BOXED(711568741124538370,64,FLEN)
NAN_BOXED(711568741124538371,64,FLEN)
NAN_BOXED(711568741124538372,64,FLEN)
NAN_BOXED(0,64,FLEN)
NAN_BOXED(0,64,FLEN)
NAN_BOXED(0,64,FLEN)
NAN_BOXED(0,64,FLEN)
NAN_BOXED(0,64,FLEN)
NAN_BOXED(0,64,FLEN)
NAN_BOXED(0,64,FLEN)
NAN_BOXED(0,64,FLEN)
NAN_BOXED(0,64,FLEN)
NAN_BOXED(0,64,FLEN)
NAN_BOXED(0,64,FLEN)
NAN_BOXED(0,64,FLEN)
NAN_BOXED(0,64,FLEN)
NAN_BOXED(0,64,FLEN)
NAN_BOXED(0,64,FLEN)
NAN_BOXED(0,64,FLEN)
NAN_BOXED(0,64,FLEN)
NAN_BOXED(0,64,FLEN)
NAN_BOXED(0,64,FLEN)
NAN_BOXED(0,64,FLEN)
NAN_BOXED(0,64,FLEN)
NAN_BOXED(0,64,FLEN)
NAN_BOXED(0,64,FLEN)
NAN_BOXED(707065141505556476,64,FLEN)
RVTEST_DATA_END
RVMODEL_DATA_BEGIN
rvtest_sig_begin:
sig_begin_canary:
CANARY;
signature_x1_0:
.fill 0*((SIGALIGN)/4),4,0xdeadbeef
signature_x1_1:
.fill 66*((SIGALIGN)/4),4,0xdeadbeef
#ifdef rvtest_mtrap_routine
tsig_begin_canary:
CANARY;
tsig_begin_canary:
CANARY;
mtrap_sigptr:
.fill 64*(XLEN/32),4,0xdeadbeef
tsig_end_canary:
CANARY;
tsig_end_canary:
CANARY;
#endif
#ifdef rvtest_gpr_save
gpr_save:
.fill 32*XLEN/32,4,0xdeadbeef
#endif
sig_end_canary:
CANARY;
rvtest_sig_end:
RVMODEL_DATA_END

356
vendor/riscv-arch-tests/riscv-test-suite/rv32i_m/D/src/fcvt.d.s_b24-01.S vendored
View file

@ -1,356 +0,0 @@
// -----------
// This file was generated by riscv_ctg (https://github.com/riscv-software-src/riscv-ctg)
// version : 0.7.1
// timestamp : Fri Jun 17 14:03:32 2022 GMT
// usage : riscv_ctg \
// -- cgf // --cgf /scratch/pawan/work/normalised/RV32D/fcvt.d.s.cgf \
\
// -- xlen 32 \
// --randomize \
// -----------
//
// -----------
// Copyright (c) 2020. RISC-V International. All rights reserved.
// SPDX-License-Identifier: BSD-3-Clause
// -----------
//
// This assembly file tests the fcvt.d.s instruction of the RISC-V RV32FD_Zicsr,RV64FD_Zicsr extension for the fcvt.d.s_b24 covergroup.
//
#include "model_test.h"
#include "arch_test.h"
RVTEST_ISA("RV32IFD_Zicsr,RV64IFD_Zicsr")
.section .text.init
.org 0x80
.globl rvtest_entry_point
rvtest_entry_point:
RVMODEL_BOOT
RVTEST_CODE_BEGIN
#ifdef TEST_CASE_1
RVTEST_CASE(0,"//check ISA:=regex(.*I.*D.*);def TEST_CASE_1=True;",fcvt.d.s_b24)
RVTEST_FP_ENABLE()
RVTEST_VALBASEUPD(x3,test_dataset_0)
RVTEST_SIGBASE(x1,signature_x1_1)
inst_0:
// rs1 == rd, rs1==f16, rd==f16,fs1 == 0 and fe1 == 0x00 and fm1 == 0x0007f0 and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffffffff
/* opcode: fcvt.d.s ; op1:f16; dest:f16; op1val:0x7f0; valaddr_reg:x3;
val_offset:0*FLEN/8; correctval:??; testreg:x2;
fcsr_val: 0 */
TEST_FPSR_OP_NRM(fcvt.d.s, f16, f16, 0, 0, x3, 0*FLEN/8, x4, x1, x2)
inst_1:
// rs1 != rd, rs1==f31, rd==f12,fs1 == 0 and fe1 == 0x78 and fm1 == 0x23d70a and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffffffff
/* opcode: fcvt.d.s ; op1:f31; dest:f12; op1val:0x78000000023d70a; valaddr_reg:x3;
val_offset:1*FLEN/8; correctval:??; testreg:x2;
fcsr_val: 0 */
TEST_FPSR_OP_NRM(fcvt.d.s, f12, f31, 0, 0, x3, 1*FLEN/8, x4, x1, x2)
inst_2:
// rs1==f24, rd==f27,fs1 == 0 and fe1 == 0x7b and fm1 == 0x4ccccc and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffffffff
/* opcode: fcvt.d.s ; op1:f24; dest:f27; op1val:0x7b00000004ccccc; valaddr_reg:x3;
val_offset:2*FLEN/8; correctval:??; testreg:x2;
fcsr_val: 0 */
TEST_FPSR_OP_NRM(fcvt.d.s, f27, f24, 0, 0, x3, 2*FLEN/8, x4, x1, x2)
inst_3:
// rs1==f2, rd==f10,fs1 == 0 and fe1 == 0x7b and fm1 == 0x6147ae and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffffffff
/* opcode: fcvt.d.s ; op1:f2; dest:f10; op1val:0x7b00000006147ae; valaddr_reg:x3;
val_offset:3*FLEN/8; correctval:??; testreg:x2;
fcsr_val: 0 */
TEST_FPSR_OP_NRM(fcvt.d.s, f10, f2, 0, 0, x3, 3*FLEN/8, x4, x1, x2)
inst_4:
// rs1==f19, rd==f6,fs1 == 0 and fe1 == 0x7e and fm1 == 0x63d70a and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffffffff
/* opcode: fcvt.d.s ; op1:f19; dest:f6; op1val:0x7e000000063d70a; valaddr_reg:x3;
val_offset:4*FLEN/8; correctval:??; testreg:x2;
fcsr_val: 0 */
TEST_FPSR_OP_NRM(fcvt.d.s, f6, f19, 0, 0, x3, 4*FLEN/8, x4, x1, x2)
inst_5:
// rs1==f28, rd==f21,fs1 == 0 and fe1 == 0x7e and fm1 == 0x666666 and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffffffff
/* opcode: fcvt.d.s ; op1:f28; dest:f21; op1val:0x7e0000000666666; valaddr_reg:x3;
val_offset:5*FLEN/8; correctval:??; testreg:x2;
fcsr_val: 0 */
TEST_FPSR_OP_NRM(fcvt.d.s, f21, f28, 0, 0, x3, 5*FLEN/8, x4, x1, x2)
inst_6:
// rs1==f22, rd==f29,fs1 == 0 and fe1 == 0x7e and fm1 == 0x7d70a3 and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffffffff
/* opcode: fcvt.d.s ; op1:f22; dest:f29; op1val:0x7e00000007d70a3; valaddr_reg:x3;
val_offset:6*FLEN/8; correctval:??; testreg:x2;
fcsr_val: 0 */
TEST_FPSR_OP_NRM(fcvt.d.s, f29, f22, 0, 0, x3, 6*FLEN/8, x4, x1, x2)
inst_7:
// rs1==f27, rd==f24,fs1 == 0 and fe1 == 0x7f and fm1 == 0x000000 and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffffffff
/* opcode: fcvt.d.s ; op1:f27; dest:f24; op1val:0x7f0000000000000; valaddr_reg:x3;
val_offset:7*FLEN/8; correctval:??; testreg:x2;
fcsr_val: 0 */
TEST_FPSR_OP_NRM(fcvt.d.s, f24, f27, 0, 0, x3, 7*FLEN/8, x4, x1, x2)
inst_8:
// rs1==f21, rd==f0,fs1 == 0 and fe1 == 0x7f and fm1 == 0x0147ae and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffffffff
/* opcode: fcvt.d.s ; op1:f21; dest:f0; op1val:0x7f00000000147ae; valaddr_reg:x3;
val_offset:8*FLEN/8; correctval:??; testreg:x2;
fcsr_val: 0 */
TEST_FPSR_OP_NRM(fcvt.d.s, f0, f21, 0, 0, x3, 8*FLEN/8, x4, x1, x2)
inst_9:
// rs1==f15, rd==f17,fs1 == 0 and fe1 == 0x7f and fm1 == 0x0ccccc and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffffffff
/* opcode: fcvt.d.s ; op1:f15; dest:f17; op1val:0x7f00000000ccccc; valaddr_reg:x3;
val_offset:9*FLEN/8; correctval:??; testreg:x2;
fcsr_val: 0 */
TEST_FPSR_OP_NRM(fcvt.d.s, f17, f15, 0, 0, x3, 9*FLEN/8, x4, x1, x2)
inst_10:
// rs1==f23, rd==f15,fs1 == 0 and fe1 == 0x7f and fm1 == 0x0e147a and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffffffff
/* opcode: fcvt.d.s ; op1:f23; dest:f15; op1val:0x7f00000000e147a; valaddr_reg:x3;
val_offset:10*FLEN/8; correctval:??; testreg:x2;
fcsr_val: 0 */
TEST_FPSR_OP_NRM(fcvt.d.s, f15, f23, 0, 0, x3, 10*FLEN/8, x4, x1, x2)
inst_11:
// rs1==f29, rd==f13,fs1 == 1 and fe1 == 0x78 and fm1 == 0x23d70a and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffffffff
/* opcode: fcvt.d.s ; op1:f29; dest:f13; op1val:0x878000000023d70a; valaddr_reg:x3;
val_offset:11*FLEN/8; correctval:??; testreg:x2;
fcsr_val: 0 */
TEST_FPSR_OP_NRM(fcvt.d.s, f13, f29, 0, 0, x3, 11*FLEN/8, x4, x1, x2)
inst_12:
// rs1==f5, rd==f22,fs1 == 1 and fe1 == 0x7b and fm1 == 0x4ccccc and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffffffff
/* opcode: fcvt.d.s ; op1:f5; dest:f22; op1val:0x87b00000004ccccc; valaddr_reg:x3;
val_offset:12*FLEN/8; correctval:??; testreg:x2;
fcsr_val: 0 */
TEST_FPSR_OP_NRM(fcvt.d.s, f22, f5, 0, 0, x3, 12*FLEN/8, x4, x1, x2)
inst_13:
// rs1==f12, rd==f20,fs1 == 1 and fe1 == 0x7b and fm1 == 0x6147ae and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffffffff
/* opcode: fcvt.d.s ; op1:f12; dest:f20; op1val:0x87b00000006147ae; valaddr_reg:x3;
val_offset:13*FLEN/8; correctval:??; testreg:x2;
fcsr_val: 0 */
TEST_FPSR_OP_NRM(fcvt.d.s, f20, f12, 0, 0, x3, 13*FLEN/8, x4, x1, x2)
inst_14:
// rs1==f9, rd==f26,fs1 == 1 and fe1 == 0x7e and fm1 == 0x63d70a and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffffffff
/* opcode: fcvt.d.s ; op1:f9; dest:f26; op1val:0x87e000000063d70a; valaddr_reg:x3;
val_offset:14*FLEN/8; correctval:??; testreg:x2;
fcsr_val: 0 */
TEST_FPSR_OP_NRM(fcvt.d.s, f26, f9, 0, 0, x3, 14*FLEN/8, x4, x1, x2)
inst_15:
// rs1==f20, rd==f11,fs1 == 1 and fe1 == 0x7e and fm1 == 0x666666 and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffffffff
/* opcode: fcvt.d.s ; op1:f20; dest:f11; op1val:0x87e0000000666666; valaddr_reg:x3;
val_offset:15*FLEN/8; correctval:??; testreg:x2;
fcsr_val: 0 */
TEST_FPSR_OP_NRM(fcvt.d.s, f11, f20, 0, 0, x3, 15*FLEN/8, x4, x1, x2)
inst_16:
// rs1==f18, rd==f3,fs1 == 1 and fe1 == 0x7e and fm1 == 0x7d70a3 and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffffffff
/* opcode: fcvt.d.s ; op1:f18; dest:f3; op1val:0x87e00000007d70a3; valaddr_reg:x3;
val_offset:16*FLEN/8; correctval:??; testreg:x2;
fcsr_val: 0 */
TEST_FPSR_OP_NRM(fcvt.d.s, f3, f18, 0, 0, x3, 16*FLEN/8, x4, x1, x2)
inst_17:
// rs1==f30, rd==f9,fs1 == 1 and fe1 == 0x7f and fm1 == 0x000000 and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffffffff
/* opcode: fcvt.d.s ; op1:f30; dest:f9; op1val:0x87f0000000000000; valaddr_reg:x3;
val_offset:17*FLEN/8; correctval:??; testreg:x2;
fcsr_val: 0 */
TEST_FPSR_OP_NRM(fcvt.d.s, f9, f30, 0, 0, x3, 17*FLEN/8, x4, x1, x2)
inst_18:
// rs1==f10, rd==f30,fs1 == 1 and fe1 == 0x7f and fm1 == 0x0147ae and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffffffff
/* opcode: fcvt.d.s ; op1:f10; dest:f30; op1val:0x87f00000000147ae; valaddr_reg:x3;
val_offset:18*FLEN/8; correctval:??; testreg:x2;
fcsr_val: 0 */
TEST_FPSR_OP_NRM(fcvt.d.s, f30, f10, 0, 0, x3, 18*FLEN/8, x4, x1, x2)
inst_19:
// rs1==f0, rd==f5,fs1 == 1 and fe1 == 0x7f and fm1 == 0x0ccccc and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffffffff
/* opcode: fcvt.d.s ; op1:f0; dest:f5; op1val:0x87f00000000ccccc; valaddr_reg:x3;
val_offset:19*FLEN/8; correctval:??; testreg:x2;
fcsr_val: 0 */
TEST_FPSR_OP_NRM(fcvt.d.s, f5, f0, 0, 0, x3, 19*FLEN/8, x4, x1, x2)
inst_20:
// rs1==f13, rd==f19,fs1 == 1 and fe1 == 0x7f and fm1 == 0x0e147a and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffffffff
/* opcode: fcvt.d.s ; op1:f13; dest:f19; op1val:0x87f00000000e147a; valaddr_reg:x3;
val_offset:20*FLEN/8; correctval:??; testreg:x2;
fcsr_val: 0 */
TEST_FPSR_OP_NRM(fcvt.d.s, f19, f13, 0, 0, x3, 20*FLEN/8, x4, x1, x2)
inst_21:
// rs1==f6, rd==f2,
/* opcode: fcvt.d.s ; op1:f6; dest:f2; op1val:0x0; valaddr_reg:x3;
val_offset:21*FLEN/8; correctval:??; testreg:x2;
fcsr_val: 0 */
TEST_FPSR_OP_NRM(fcvt.d.s, f2, f6, 0, 0, x3, 21*FLEN/8, x4, x1, x2)
inst_22:
// rs1==f7, rd==f1,
/* opcode: fcvt.d.s ; op1:f7; dest:f1; op1val:0x0; valaddr_reg:x3;
val_offset:22*FLEN/8; correctval:??; testreg:x2;
fcsr_val: 0 */
TEST_FPSR_OP_NRM(fcvt.d.s, f1, f7, 0, 0, x3, 22*FLEN/8, x4, x1, x2)
inst_23:
// rs1==f14, rd==f23,
/* opcode: fcvt.d.s ; op1:f14; dest:f23; op1val:0x0; valaddr_reg:x3;
val_offset:23*FLEN/8; correctval:??; testreg:x2;
fcsr_val: 0 */
TEST_FPSR_OP_NRM(fcvt.d.s, f23, f14, 0, 0, x3, 23*FLEN/8, x4, x1, x2)
inst_24:
// rs1==f8, rd==f14,
/* opcode: fcvt.d.s ; op1:f8; dest:f14; op1val:0x0; valaddr_reg:x3;
val_offset:24*FLEN/8; correctval:??; testreg:x2;
fcsr_val: 0 */
TEST_FPSR_OP_NRM(fcvt.d.s, f14, f8, 0, 0, x3, 24*FLEN/8, x4, x1, x2)
inst_25:
// rs1==f4, rd==f25,
/* opcode: fcvt.d.s ; op1:f4; dest:f25; op1val:0x0; valaddr_reg:x3;
val_offset:25*FLEN/8; correctval:??; testreg:x2;
fcsr_val: 0 */
TEST_FPSR_OP_NRM(fcvt.d.s, f25, f4, 0, 0, x3, 25*FLEN/8, x4, x1, x2)
inst_26:
// rs1==f3, rd==f18,
/* opcode: fcvt.d.s ; op1:f3; dest:f18; op1val:0x0; valaddr_reg:x3;
val_offset:26*FLEN/8; correctval:??; testreg:x2;
fcsr_val: 0 */
TEST_FPSR_OP_NRM(fcvt.d.s, f18, f3, 0, 0, x3, 26*FLEN/8, x4, x1, x2)
inst_27:
// rs1==f1, rd==f8,
/* opcode: fcvt.d.s ; op1:f1; dest:f8; op1val:0x0; valaddr_reg:x3;
val_offset:27*FLEN/8; correctval:??; testreg:x2;
fcsr_val: 0 */
TEST_FPSR_OP_NRM(fcvt.d.s, f8, f1, 0, 0, x3, 27*FLEN/8, x4, x1, x2)
inst_28:
// rs1==f25, rd==f28,
/* opcode: fcvt.d.s ; op1:f25; dest:f28; op1val:0x0; valaddr_reg:x3;
val_offset:28*FLEN/8; correctval:??; testreg:x2;
fcsr_val: 0 */
TEST_FPSR_OP_NRM(fcvt.d.s, f28, f25, 0, 0, x3, 28*FLEN/8, x4, x1, x2)
inst_29:
// rs1==f11, rd==f4,
/* opcode: fcvt.d.s ; op1:f11; dest:f4; op1val:0x0; valaddr_reg:x3;
val_offset:29*FLEN/8; correctval:??; testreg:x2;
fcsr_val: 0 */
TEST_FPSR_OP_NRM(fcvt.d.s, f4, f11, 0, 0, x3, 29*FLEN/8, x4, x1, x2)
inst_30:
// rs1==f26, rd==f31,
/* opcode: fcvt.d.s ; op1:f26; dest:f31; op1val:0x0; valaddr_reg:x3;
val_offset:30*FLEN/8; correctval:??; testreg:x2;
fcsr_val: 0 */
TEST_FPSR_OP_NRM(fcvt.d.s, f31, f26, 0, 0, x3, 30*FLEN/8, x4, x1, x2)
inst_31:
// rs1==f17, rd==f7,
/* opcode: fcvt.d.s ; op1:f17; dest:f7; op1val:0x0; valaddr_reg:x3;
val_offset:31*FLEN/8; correctval:??; testreg:x2;
fcsr_val: 0 */
TEST_FPSR_OP_NRM(fcvt.d.s, f7, f17, 0, 0, x3, 31*FLEN/8, x4, x1, x2)
inst_32:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x0007f0 and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffffffff
/* opcode: fcvt.d.s ; op1:f30; dest:f31; op1val:0x7f0; valaddr_reg:x3;
val_offset:32*FLEN/8; correctval:??; testreg:x2;
fcsr_val: 0 */
TEST_FPSR_OP_NRM(fcvt.d.s, f31, f30, 0, 0, x3, 32*FLEN/8, x4, x1, x2)
#endif
RVTEST_CODE_END
RVMODEL_HALT
RVTEST_DATA_BEGIN
.align 4
rvtest_data:
.word 0xbabecafe
.word 0xabecafeb
.word 0xbecafeba
.word 0xecafebab
test_dataset_0:
NAN_BOXED(2032,64,FLEN)
NAN_BOXED(540431955286808330,64,FLEN)
NAN_BOXED(553942754171604172,64,FLEN)
NAN_BOXED(553942754172946350,64,FLEN)
NAN_BOXED(567453553055225610,64,FLEN)
NAN_BOXED(567453553055393382,64,FLEN)
NAN_BOXED(567453553056903331,64,FLEN)
NAN_BOXED(571957152676052992,64,FLEN)
NAN_BOXED(571957152676136878,64,FLEN)
NAN_BOXED(571957152676891852,64,FLEN)
NAN_BOXED(571957152676975738,64,FLEN)
NAN_BOXED(9763803992141584138,64,FLEN)
NAN_BOXED(9777314791026379980,64,FLEN)
NAN_BOXED(9777314791027722158,64,FLEN)
NAN_BOXED(9790825589910001418,64,FLEN)
NAN_BOXED(9790825589910169190,64,FLEN)
NAN_BOXED(9790825589911679139,64,FLEN)
NAN_BOXED(9795329189530828800,64,FLEN)
NAN_BOXED(9795329189530912686,64,FLEN)
NAN_BOXED(9795329189531667660,64,FLEN)
NAN_BOXED(9795329189531751546,64,FLEN)
NAN_BOXED(0,64,FLEN)
NAN_BOXED(0,64,FLEN)
NAN_BOXED(0,64,FLEN)
NAN_BOXED(0,64,FLEN)
NAN_BOXED(0,64,FLEN)
NAN_BOXED(0,64,FLEN)
NAN_BOXED(0,64,FLEN)
NAN_BOXED(0,64,FLEN)
NAN_BOXED(0,64,FLEN)
NAN_BOXED(0,64,FLEN)
NAN_BOXED(0,64,FLEN)
NAN_BOXED(2032,64,FLEN)
RVTEST_DATA_END
RVMODEL_DATA_BEGIN
rvtest_sig_begin:
sig_begin_canary:
CANARY;
signature_x1_0:
.fill 0*((SIGALIGN)/4),4,0xdeadbeef
signature_x1_1:
.fill 66*((SIGALIGN)/4),4,0xdeadbeef
#ifdef rvtest_mtrap_routine
tsig_begin_canary:
CANARY;
tsig_begin_canary:
CANARY;
mtrap_sigptr:
.fill 64*(XLEN/32),4,0xdeadbeef
tsig_end_canary:
CANARY;
tsig_end_canary:
CANARY;
#endif
#ifdef rvtest_gpr_save
gpr_save:
.fill 32*XLEN/32,4,0xdeadbeef
#endif
sig_end_canary:
CANARY;
rvtest_sig_end:
RVMODEL_DATA_END

356
vendor/riscv-arch-tests/riscv-test-suite/rv32i_m/D/src/fcvt.d.s_b27-01.S vendored
View file

@ -1,356 +0,0 @@
// -----------
// This file was generated by riscv_ctg (https://github.com/riscv-software-src/riscv-ctg)
// version : 0.7.1
// timestamp : Fri Jun 17 14:03:32 2022 GMT
// usage : riscv_ctg \
// -- cgf // --cgf /scratch/pawan/work/normalised/RV32D/fcvt.d.s.cgf \
\
// -- xlen 32 \
// --randomize \
// -----------
//
// -----------
// Copyright (c) 2020. RISC-V International. All rights reserved.
// SPDX-License-Identifier: BSD-3-Clause
// -----------
//
// This assembly file tests the fcvt.d.s instruction of the RISC-V RV32FD_Zicsr,RV64FD_Zicsr extension for the fcvt.d.s_b27 covergroup.
//
#include "model_test.h"
#include "arch_test.h"
RVTEST_ISA("RV32IFD_Zicsr,RV64IFD_Zicsr")
.section .text.init
.org 0x80
.globl rvtest_entry_point
rvtest_entry_point:
RVMODEL_BOOT
RVTEST_CODE_BEGIN
#ifdef TEST_CASE_1
RVTEST_CASE(0,"//check ISA:=regex(.*I.*D.*);def TEST_CASE_1=True;",fcvt.d.s_b27)
RVTEST_FP_ENABLE()
RVTEST_VALBASEUPD(x3,test_dataset_0)
RVTEST_SIGBASE(x1,signature_x1_1)
inst_0:
// rs1 == rd, rs1==f0, rd==f0,fs1 == 0 and fe1 == 0xff and fm1 == 0x000001 and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffffffff
/* opcode: fcvt.d.s ; op1:f0; dest:f0; op1val:0xff0000000000001; valaddr_reg:x3;
val_offset:0*FLEN/8; correctval:??; testreg:x2;
fcsr_val: 0 */
TEST_FPSR_OP_NRM(fcvt.d.s, f0, f0, 0, 0, x3, 0*FLEN/8, x4, x1, x2)
inst_1:
// rs1 != rd, rs1==f29, rd==f30,fs1 == 0 and fe1 == 0xff and fm1 == 0x2aaaaa and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffffffff
/* opcode: fcvt.d.s ; op1:f29; dest:f30; op1val:0xff00000002aaaaa; valaddr_reg:x3;
val_offset:1*FLEN/8; correctval:??; testreg:x2;
fcsr_val: 0 */
TEST_FPSR_OP_NRM(fcvt.d.s, f30, f29, 0, 0, x3, 1*FLEN/8, x4, x1, x2)
inst_2:
// rs1==f23, rd==f29,fs1 == 0 and fe1 == 0xff and fm1 == 0x400001 and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffffffff
/* opcode: fcvt.d.s ; op1:f23; dest:f29; op1val:0xff0000000400001; valaddr_reg:x3;
val_offset:2*FLEN/8; correctval:??; testreg:x2;
fcsr_val: 0 */
TEST_FPSR_OP_NRM(fcvt.d.s, f29, f23, 0, 0, x3, 2*FLEN/8, x4, x1, x2)
inst_3:
// rs1==f18, rd==f5,fs1 == 0 and fe1 == 0xff and fm1 == 0x455555 and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffffffff
/* opcode: fcvt.d.s ; op1:f18; dest:f5; op1val:0xff0000000455555; valaddr_reg:x3;
val_offset:3*FLEN/8; correctval:??; testreg:x2;
fcsr_val: 0 */
TEST_FPSR_OP_NRM(fcvt.d.s, f5, f18, 0, 0, x3, 3*FLEN/8, x4, x1, x2)
inst_4:
// rs1==f16, rd==f28,fs1 == 1 and fe1 == 0xff and fm1 == 0x000001 and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffffffff
/* opcode: fcvt.d.s ; op1:f16; dest:f28; op1val:0x8ff0000000000001; valaddr_reg:x3;
val_offset:4*FLEN/8; correctval:??; testreg:x2;
fcsr_val: 0 */
TEST_FPSR_OP_NRM(fcvt.d.s, f28, f16, 0, 0, x3, 4*FLEN/8, x4, x1, x2)
inst_5:
// rs1==f30, rd==f13,fs1 == 1 and fe1 == 0xff and fm1 == 0x2aaaaa and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffffffff
/* opcode: fcvt.d.s ; op1:f30; dest:f13; op1val:0x8ff00000002aaaaa; valaddr_reg:x3;
val_offset:5*FLEN/8; correctval:??; testreg:x2;
fcsr_val: 0 */
TEST_FPSR_OP_NRM(fcvt.d.s, f13, f30, 0, 0, x3, 5*FLEN/8, x4, x1, x2)
inst_6:
// rs1==f21, rd==f8,fs1 == 1 and fe1 == 0xff and fm1 == 0x400001 and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffffffff
/* opcode: fcvt.d.s ; op1:f21; dest:f8; op1val:0x8ff0000000400001; valaddr_reg:x3;
val_offset:6*FLEN/8; correctval:??; testreg:x2;
fcsr_val: 0 */
TEST_FPSR_OP_NRM(fcvt.d.s, f8, f21, 0, 0, x3, 6*FLEN/8, x4, x1, x2)
inst_7:
// rs1==f8, rd==f19,fs1 == 1 and fe1 == 0xff and fm1 == 0x455555 and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffffffff
/* opcode: fcvt.d.s ; op1:f8; dest:f19; op1val:0x8ff0000000455555; valaddr_reg:x3;
val_offset:7*FLEN/8; correctval:??; testreg:x2;
fcsr_val: 0 */
TEST_FPSR_OP_NRM(fcvt.d.s, f19, f8, 0, 0, x3, 7*FLEN/8, x4, x1, x2)
inst_8:
// rs1==f17, rd==f10,
/* opcode: fcvt.d.s ; op1:f17; dest:f10; op1val:0x0; valaddr_reg:x3;
val_offset:8*FLEN/8; correctval:??; testreg:x2;
fcsr_val: 0 */
TEST_FPSR_OP_NRM(fcvt.d.s, f10, f17, 0, 0, x3, 8*FLEN/8, x4, x1, x2)
inst_9:
// rs1==f22, rd==f24,
/* opcode: fcvt.d.s ; op1:f22; dest:f24; op1val:0x0; valaddr_reg:x3;
val_offset:9*FLEN/8; correctval:??; testreg:x2;
fcsr_val: 0 */
TEST_FPSR_OP_NRM(fcvt.d.s, f24, f22, 0, 0, x3, 9*FLEN/8, x4, x1, x2)
inst_10:
// rs1==f10, rd==f11,
/* opcode: fcvt.d.s ; op1:f10; dest:f11; op1val:0x0; valaddr_reg:x3;
val_offset:10*FLEN/8; correctval:??; testreg:x2;
fcsr_val: 0 */
TEST_FPSR_OP_NRM(fcvt.d.s, f11, f10, 0, 0, x3, 10*FLEN/8, x4, x1, x2)
inst_11:
// rs1==f19, rd==f22,
/* opcode: fcvt.d.s ; op1:f19; dest:f22; op1val:0x0; valaddr_reg:x3;
val_offset:11*FLEN/8; correctval:??; testreg:x2;
fcsr_val: 0 */
TEST_FPSR_OP_NRM(fcvt.d.s, f22, f19, 0, 0, x3, 11*FLEN/8, x4, x1, x2)
inst_12:
// rs1==f25, rd==f3,
/* opcode: fcvt.d.s ; op1:f25; dest:f3; op1val:0x0; valaddr_reg:x3;
val_offset:12*FLEN/8; correctval:??; testreg:x2;
fcsr_val: 0 */
TEST_FPSR_OP_NRM(fcvt.d.s, f3, f25, 0, 0, x3, 12*FLEN/8, x4, x1, x2)
inst_13:
// rs1==f5, rd==f16,
/* opcode: fcvt.d.s ; op1:f5; dest:f16; op1val:0x0; valaddr_reg:x3;
val_offset:13*FLEN/8; correctval:??; testreg:x2;
fcsr_val: 0 */
TEST_FPSR_OP_NRM(fcvt.d.s, f16, f5, 0, 0, x3, 13*FLEN/8, x4, x1, x2)
inst_14:
// rs1==f14, rd==f9,
/* opcode: fcvt.d.s ; op1:f14; dest:f9; op1val:0x0; valaddr_reg:x3;
val_offset:14*FLEN/8; correctval:??; testreg:x2;
fcsr_val: 0 */
TEST_FPSR_OP_NRM(fcvt.d.s, f9, f14, 0, 0, x3, 14*FLEN/8, x4, x1, x2)
inst_15:
// rs1==f26, rd==f31,
/* opcode: fcvt.d.s ; op1:f26; dest:f31; op1val:0x0; valaddr_reg:x3;
val_offset:15*FLEN/8; correctval:??; testreg:x2;
fcsr_val: 0 */
TEST_FPSR_OP_NRM(fcvt.d.s, f31, f26, 0, 0, x3, 15*FLEN/8, x4, x1, x2)
inst_16:
// rs1==f1, rd==f2,
/* opcode: fcvt.d.s ; op1:f1; dest:f2; op1val:0x0; valaddr_reg:x3;
val_offset:16*FLEN/8; correctval:??; testreg:x2;
fcsr_val: 0 */
TEST_FPSR_OP_NRM(fcvt.d.s, f2, f1, 0, 0, x3, 16*FLEN/8, x4, x1, x2)
inst_17:
// rs1==f11, rd==f25,
/* opcode: fcvt.d.s ; op1:f11; dest:f25; op1val:0x0; valaddr_reg:x3;
val_offset:17*FLEN/8; correctval:??; testreg:x2;
fcsr_val: 0 */
TEST_FPSR_OP_NRM(fcvt.d.s, f25, f11, 0, 0, x3, 17*FLEN/8, x4, x1, x2)
inst_18:
// rs1==f12, rd==f27,
/* opcode: fcvt.d.s ; op1:f12; dest:f27; op1val:0x0; valaddr_reg:x3;
val_offset:18*FLEN/8; correctval:??; testreg:x2;
fcsr_val: 0 */
TEST_FPSR_OP_NRM(fcvt.d.s, f27, f12, 0, 0, x3, 18*FLEN/8, x4, x1, x2)
inst_19:
// rs1==f31, rd==f1,
/* opcode: fcvt.d.s ; op1:f31; dest:f1; op1val:0x0; valaddr_reg:x3;
val_offset:19*FLEN/8; correctval:??; testreg:x2;
fcsr_val: 0 */
TEST_FPSR_OP_NRM(fcvt.d.s, f1, f31, 0, 0, x3, 19*FLEN/8, x4, x1, x2)
inst_20:
// rs1==f24, rd==f15,
/* opcode: fcvt.d.s ; op1:f24; dest:f15; op1val:0x0; valaddr_reg:x3;
val_offset:20*FLEN/8; correctval:??; testreg:x2;
fcsr_val: 0 */
TEST_FPSR_OP_NRM(fcvt.d.s, f15, f24, 0, 0, x3, 20*FLEN/8, x4, x1, x2)
inst_21:
// rs1==f2, rd==f4,
/* opcode: fcvt.d.s ; op1:f2; dest:f4; op1val:0x0; valaddr_reg:x3;
val_offset:21*FLEN/8; correctval:??; testreg:x2;
fcsr_val: 0 */
TEST_FPSR_OP_NRM(fcvt.d.s, f4, f2, 0, 0, x3, 21*FLEN/8, x4, x1, x2)
inst_22:
// rs1==f3, rd==f17,
/* opcode: fcvt.d.s ; op1:f3; dest:f17; op1val:0x0; valaddr_reg:x3;
val_offset:22*FLEN/8; correctval:??; testreg:x2;
fcsr_val: 0 */
TEST_FPSR_OP_NRM(fcvt.d.s, f17, f3, 0, 0, x3, 22*FLEN/8, x4, x1, x2)
inst_23:
// rs1==f13, rd==f12,
/* opcode: fcvt.d.s ; op1:f13; dest:f12; op1val:0x0; valaddr_reg:x3;
val_offset:23*FLEN/8; correctval:??; testreg:x2;
fcsr_val: 0 */
TEST_FPSR_OP_NRM(fcvt.d.s, f12, f13, 0, 0, x3, 23*FLEN/8, x4, x1, x2)
inst_24:
// rs1==f27, rd==f26,
/* opcode: fcvt.d.s ; op1:f27; dest:f26; op1val:0x0; valaddr_reg:x3;
val_offset:24*FLEN/8; correctval:??; testreg:x2;
fcsr_val: 0 */
TEST_FPSR_OP_NRM(fcvt.d.s, f26, f27, 0, 0, x3, 24*FLEN/8, x4, x1, x2)
inst_25:
// rs1==f15, rd==f21,
/* opcode: fcvt.d.s ; op1:f15; dest:f21; op1val:0x0; valaddr_reg:x3;
val_offset:25*FLEN/8; correctval:??; testreg:x2;
fcsr_val: 0 */
TEST_FPSR_OP_NRM(fcvt.d.s, f21, f15, 0, 0, x3, 25*FLEN/8, x4, x1, x2)
inst_26:
// rs1==f7, rd==f18,
/* opcode: fcvt.d.s ; op1:f7; dest:f18; op1val:0x0; valaddr_reg:x3;
val_offset:26*FLEN/8; correctval:??; testreg:x2;
fcsr_val: 0 */
TEST_FPSR_OP_NRM(fcvt.d.s, f18, f7, 0, 0, x3, 26*FLEN/8, x4, x1, x2)
inst_27:
// rs1==f4, rd==f6,
/* opcode: fcvt.d.s ; op1:f4; dest:f6; op1val:0x0; valaddr_reg:x3;
val_offset:27*FLEN/8; correctval:??; testreg:x2;
fcsr_val: 0 */
TEST_FPSR_OP_NRM(fcvt.d.s, f6, f4, 0, 0, x3, 27*FLEN/8, x4, x1, x2)
inst_28:
// rs1==f9, rd==f20,
/* opcode: fcvt.d.s ; op1:f9; dest:f20; op1val:0x0; valaddr_reg:x3;
val_offset:28*FLEN/8; correctval:??; testreg:x2;
fcsr_val: 0 */
TEST_FPSR_OP_NRM(fcvt.d.s, f20, f9, 0, 0, x3, 28*FLEN/8, x4, x1, x2)
inst_29:
// rs1==f28, rd==f23,
/* opcode: fcvt.d.s ; op1:f28; dest:f23; op1val:0x0; valaddr_reg:x3;
val_offset:29*FLEN/8; correctval:??; testreg:x2;
fcsr_val: 0 */
TEST_FPSR_OP_NRM(fcvt.d.s, f23, f28, 0, 0, x3, 29*FLEN/8, x4, x1, x2)
inst_30:
// rs1==f6, rd==f7,
/* opcode: fcvt.d.s ; op1:f6; dest:f7; op1val:0x0; valaddr_reg:x3;
val_offset:30*FLEN/8; correctval:??; testreg:x2;
fcsr_val: 0 */
TEST_FPSR_OP_NRM(fcvt.d.s, f7, f6, 0, 0, x3, 30*FLEN/8, x4, x1, x2)
inst_31:
// rs1==f20, rd==f14,
/* opcode: fcvt.d.s ; op1:f20; dest:f14; op1val:0x0; valaddr_reg:x3;
val_offset:31*FLEN/8; correctval:??; testreg:x2;
fcsr_val: 0 */
TEST_FPSR_OP_NRM(fcvt.d.s, f14, f20, 0, 0, x3, 31*FLEN/8, x4, x1, x2)
inst_32:
// fs1 == 0 and fe1 == 0xff and fm1 == 0x000001 and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffffffff
/* opcode: fcvt.d.s ; op1:f30; dest:f31; op1val:0xff0000000000001; valaddr_reg:x3;
val_offset:32*FLEN/8; correctval:??; testreg:x2;
fcsr_val: 0 */
TEST_FPSR_OP_NRM(fcvt.d.s, f31, f30, 0, 0, x3, 32*FLEN/8, x4, x1, x2)
#endif
RVTEST_CODE_END
RVMODEL_HALT
RVTEST_DATA_BEGIN
.align 4
rvtest_data:
.word 0xbabecafe
.word 0xabecafeb
.word 0xbecafeba
.word 0xecafebab
test_dataset_0:
NAN_BOXED(1148417904979476481,64,FLEN)
NAN_BOXED(1148417904982272682,64,FLEN)
NAN_BOXED(1148417904983670785,64,FLEN)
NAN_BOXED(1148417904984020309,64,FLEN)
NAN_BOXED(10371789941834252289,64,FLEN)
NAN_BOXED(10371789941837048490,64,FLEN)
NAN_BOXED(10371789941838446593,64,FLEN)
NAN_BOXED(10371789941838796117,64,FLEN)
NAN_BOXED(0,64,FLEN)
NAN_BOXED(0,64,FLEN)
NAN_BOXED(0,64,FLEN)
NAN_BOXED(0,64,FLEN)
NAN_BOXED(0,64,FLEN)
NAN_BOXED(0,64,FLEN)
NAN_BOXED(0,64,FLEN)
NAN_BOXED(0,64,FLEN)
NAN_BOXED(0,64,FLEN)
NAN_BOXED(0,64,FLEN)
NAN_BOXED(0,64,FLEN)
NAN_BOXED(0,64,FLEN)
NAN_BOXED(0,64,FLEN)
NAN_BOXED(0,64,FLEN)
NAN_BOXED(0,64,FLEN)
NAN_BOXED(0,64,FLEN)
NAN_BOXED(0,64,FLEN)
NAN_BOXED(0,64,FLEN)
NAN_BOXED(0,64,FLEN)
NAN_BOXED(0,64,FLEN)
NAN_BOXED(0,64,FLEN)
NAN_BOXED(0,64,FLEN)
NAN_BOXED(0,64,FLEN)
NAN_BOXED(0,64,FLEN)
NAN_BOXED(1148417904979476481,64,FLEN)
RVTEST_DATA_END
RVMODEL_DATA_BEGIN
rvtest_sig_begin:
sig_begin_canary:
CANARY;
signature_x1_0:
.fill 0*((SIGALIGN)/4),4,0xdeadbeef
signature_x1_1:
.fill 66*((SIGALIGN)/4),4,0xdeadbeef
#ifdef rvtest_mtrap_routine
tsig_begin_canary:
CANARY;
tsig_begin_canary:
CANARY;
mtrap_sigptr:
.fill 64*(XLEN/32),4,0xdeadbeef
tsig_end_canary:
CANARY;
tsig_end_canary:
CANARY;
#endif
#ifdef rvtest_gpr_save
gpr_save:
.fill 32*XLEN/32,4,0xdeadbeef
#endif
sig_end_canary:
CANARY;
rvtest_sig_end:
RVMODEL_DATA_END

356
vendor/riscv-arch-tests/riscv-test-suite/rv32i_m/D/src/fcvt.d.s_b28-01.S vendored
View file

@ -1,356 +0,0 @@
// -----------
// This file was generated by riscv_ctg (https://github.com/riscv-software-src/riscv-ctg)
// version : 0.7.1
// timestamp : Fri Jun 17 14:03:32 2022 GMT
// usage : riscv_ctg \
// -- cgf // --cgf /scratch/pawan/work/normalised/RV32D/fcvt.d.s.cgf \
\
// -- xlen 32 \
// --randomize \
// -----------
//
// -----------
// Copyright (c) 2020. RISC-V International. All rights reserved.
// SPDX-License-Identifier: BSD-3-Clause
// -----------
//
// This assembly file tests the fcvt.d.s instruction of the RISC-V RV32FD_Zicsr,RV64FD_Zicsr extension for the fcvt.d.s_b28 covergroup.
//
#include "model_test.h"
#include "arch_test.h"
RVTEST_ISA("RV32IFD_Zicsr,RV64IFD_Zicsr")
.section .text.init
.org 0x80
.globl rvtest_entry_point
rvtest_entry_point:
RVMODEL_BOOT
RVTEST_CODE_BEGIN
#ifdef TEST_CASE_1
RVTEST_CASE(0,"//check ISA:=regex(.*I.*D.*);def TEST_CASE_1=True;",fcvt.d.s_b28)
RVTEST_FP_ENABLE()
RVTEST_VALBASEUPD(x3,test_dataset_0)
RVTEST_SIGBASE(x1,signature_x1_1)
inst_0:
// rs1 == rd, rs1==f27, rd==f27,fs1 == 0 and fe1 == 0x00 and fm1 == 0x000000 and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffffffff
/* opcode: fcvt.d.s ; op1:f27; dest:f27; op1val:0x0; valaddr_reg:x3;
val_offset:0*FLEN/8; correctval:??; testreg:x2;
fcsr_val: 0 */
TEST_FPSR_OP_NRM(fcvt.d.s, f27, f27, 0, 0, x3, 0*FLEN/8, x4, x1, x2)
inst_1:
// rs1 != rd, rs1==f7, rd==f17,fs1 == 0 and fe1 == 0x7e and fm1 == 0x124770 and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffffffff
/* opcode: fcvt.d.s ; op1:f7; dest:f17; op1val:0x7e0000000124770; valaddr_reg:x3;
val_offset:1*FLEN/8; correctval:??; testreg:x2;
fcsr_val: 0 */
TEST_FPSR_OP_NRM(fcvt.d.s, f17, f7, 0, 0, x3, 1*FLEN/8, x4, x1, x2)
inst_2:
// rs1==f13, rd==f21,fs1 == 0 and fe1 == 0x7f and fm1 == 0x000000 and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffffffff
/* opcode: fcvt.d.s ; op1:f13; dest:f21; op1val:0x7f0000000000000; valaddr_reg:x3;
val_offset:2*FLEN/8; correctval:??; testreg:x2;
fcsr_val: 0 */
TEST_FPSR_OP_NRM(fcvt.d.s, f21, f13, 0, 0, x3, 2*FLEN/8, x4, x1, x2)
inst_3:
// rs1==f16, rd==f15,fs1 == 0 and fe1 == 0x7f and fm1 == 0x200000 and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffffffff
/* opcode: fcvt.d.s ; op1:f16; dest:f15; op1val:0x7f0000000200000; valaddr_reg:x3;
val_offset:3*FLEN/8; correctval:??; testreg:x2;
fcsr_val: 0 */
TEST_FPSR_OP_NRM(fcvt.d.s, f15, f16, 0, 0, x3, 3*FLEN/8, x4, x1, x2)
inst_4:
// rs1==f17, rd==f31,fs1 == 0 and fe1 == 0x7f and fm1 == 0x400000 and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffffffff
/* opcode: fcvt.d.s ; op1:f17; dest:f31; op1val:0x7f0000000400000; valaddr_reg:x3;
val_offset:4*FLEN/8; correctval:??; testreg:x2;
fcsr_val: 0 */
TEST_FPSR_OP_NRM(fcvt.d.s, f31, f17, 0, 0, x3, 4*FLEN/8, x4, x1, x2)
inst_5:
// rs1==f6, rd==f28,fs1 == 0 and fe1 == 0x7f and fm1 == 0x600000 and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffffffff
/* opcode: fcvt.d.s ; op1:f6; dest:f28; op1val:0x7f0000000600000; valaddr_reg:x3;
val_offset:5*FLEN/8; correctval:??; testreg:x2;
fcsr_val: 0 */
TEST_FPSR_OP_NRM(fcvt.d.s, f28, f6, 0, 0, x3, 5*FLEN/8, x4, x1, x2)
inst_6:
// rs1==f10, rd==f1,fs1 == 0 and fe1 == 0x80 and fm1 == 0x000000 and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffffffff
/* opcode: fcvt.d.s ; op1:f10; dest:f1; op1val:0x800000000000000; valaddr_reg:x3;
val_offset:6*FLEN/8; correctval:??; testreg:x2;
fcsr_val: 0 */
TEST_FPSR_OP_NRM(fcvt.d.s, f1, f10, 0, 0, x3, 6*FLEN/8, x4, x1, x2)
inst_7:
// rs1==f30, rd==f9,fs1 == 0 and fe1 == 0x80 and fm1 == 0x100000 and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffffffff
/* opcode: fcvt.d.s ; op1:f30; dest:f9; op1val:0x800000000100000; valaddr_reg:x3;
val_offset:7*FLEN/8; correctval:??; testreg:x2;
fcsr_val: 0 */
TEST_FPSR_OP_NRM(fcvt.d.s, f9, f30, 0, 0, x3, 7*FLEN/8, x4, x1, x2)
inst_8:
// rs1==f26, rd==f7,fs1 == 0 and fe1 == 0x80 and fm1 == 0x200000 and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffffffff
/* opcode: fcvt.d.s ; op1:f26; dest:f7; op1val:0x800000000200000; valaddr_reg:x3;
val_offset:8*FLEN/8; correctval:??; testreg:x2;
fcsr_val: 0 */
TEST_FPSR_OP_NRM(fcvt.d.s, f7, f26, 0, 0, x3, 8*FLEN/8, x4, x1, x2)
inst_9:
// rs1==f23, rd==f29,fs1 == 0 and fe1 == 0x80 and fm1 == 0x300000 and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffffffff
/* opcode: fcvt.d.s ; op1:f23; dest:f29; op1val:0x800000000300000; valaddr_reg:x3;
val_offset:9*FLEN/8; correctval:??; testreg:x2;
fcsr_val: 0 */
TEST_FPSR_OP_NRM(fcvt.d.s, f29, f23, 0, 0, x3, 9*FLEN/8, x4, x1, x2)
inst_10:
// rs1==f21, rd==f25,fs1 == 0 and fe1 == 0x9c and fm1 == 0x5b9758 and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffffffff
/* opcode: fcvt.d.s ; op1:f21; dest:f25; op1val:0x9c00000005b9758; valaddr_reg:x3;
val_offset:10*FLEN/8; correctval:??; testreg:x2;
fcsr_val: 0 */
TEST_FPSR_OP_NRM(fcvt.d.s, f25, f21, 0, 0, x3, 10*FLEN/8, x4, x1, x2)
inst_11:
// rs1==f22, rd==f20,fs1 == 0 and fe1 == 0x9d and fm1 == 0x7fffff and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffffffff
/* opcode: fcvt.d.s ; op1:f22; dest:f20; op1val:0x9d00000007fffff; valaddr_reg:x3;
val_offset:11*FLEN/8; correctval:??; testreg:x2;
fcsr_val: 0 */
TEST_FPSR_OP_NRM(fcvt.d.s, f20, f22, 0, 0, x3, 11*FLEN/8, x4, x1, x2)
inst_12:
// rs1==f4, rd==f10,fs1 == 0 and fe1 == 0xff and fm1 == 0x000000 and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffffffff
/* opcode: fcvt.d.s ; op1:f4; dest:f10; op1val:0xff0000000000000; valaddr_reg:x3;
val_offset:12*FLEN/8; correctval:??; testreg:x2;
fcsr_val: 0 */
TEST_FPSR_OP_NRM(fcvt.d.s, f10, f4, 0, 0, x3, 12*FLEN/8, x4, x1, x2)
inst_13:
// rs1==f8, rd==f14,fs1 == 0 and fe1 == 0xff and fm1 == 0x000001 and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffffffff
/* opcode: fcvt.d.s ; op1:f8; dest:f14; op1val:0xff0000000000001; valaddr_reg:x3;
val_offset:13*FLEN/8; correctval:??; testreg:x2;
fcsr_val: 0 */
TEST_FPSR_OP_NRM(fcvt.d.s, f14, f8, 0, 0, x3, 13*FLEN/8, x4, x1, x2)
inst_14:
// rs1==f11, rd==f24,fs1 == 0 and fe1 == 0xff and fm1 == 0x400001 and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffffffff
/* opcode: fcvt.d.s ; op1:f11; dest:f24; op1val:0xff0000000400001; valaddr_reg:x3;
val_offset:14*FLEN/8; correctval:??; testreg:x2;
fcsr_val: 0 */
TEST_FPSR_OP_NRM(fcvt.d.s, f24, f11, 0, 0, x3, 14*FLEN/8, x4, x1, x2)
inst_15:
// rs1==f1, rd==f11,fs1 == 1 and fe1 == 0x00 and fm1 == 0x000000 and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffffffff
/* opcode: fcvt.d.s ; op1:f1; dest:f11; op1val:0x8000000000000000; valaddr_reg:x3;
val_offset:15*FLEN/8; correctval:??; testreg:x2;
fcsr_val: 0 */
TEST_FPSR_OP_NRM(fcvt.d.s, f11, f1, 0, 0, x3, 15*FLEN/8, x4, x1, x2)
inst_16:
// rs1==f2, rd==f13,fs1 == 1 and fe1 == 0x7d and fm1 == 0x58046a and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffffffff
/* opcode: fcvt.d.s ; op1:f2; dest:f13; op1val:0x87d000000058046a; valaddr_reg:x3;
val_offset:16*FLEN/8; correctval:??; testreg:x2;
fcsr_val: 0 */
TEST_FPSR_OP_NRM(fcvt.d.s, f13, f2, 0, 0, x3, 16*FLEN/8, x4, x1, x2)
inst_17:
// rs1==f25, rd==f26,fs1 == 1 and fe1 == 0x7f and fm1 == 0x000000 and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffffffff
/* opcode: fcvt.d.s ; op1:f25; dest:f26; op1val:0x87f0000000000000; valaddr_reg:x3;
val_offset:17*FLEN/8; correctval:??; testreg:x2;
fcsr_val: 0 */
TEST_FPSR_OP_NRM(fcvt.d.s, f26, f25, 0, 0, x3, 17*FLEN/8, x4, x1, x2)
inst_18:
// rs1==f15, rd==f3,fs1 == 1 and fe1 == 0x7f and fm1 == 0x200000 and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffffffff
/* opcode: fcvt.d.s ; op1:f15; dest:f3; op1val:0x87f0000000200000; valaddr_reg:x3;
val_offset:18*FLEN/8; correctval:??; testreg:x2;
fcsr_val: 0 */
TEST_FPSR_OP_NRM(fcvt.d.s, f3, f15, 0, 0, x3, 18*FLEN/8, x4, x1, x2)
inst_19:
// rs1==f18, rd==f4,fs1 == 1 and fe1 == 0x7f and fm1 == 0x400000 and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffffffff
/* opcode: fcvt.d.s ; op1:f18; dest:f4; op1val:0x87f0000000400000; valaddr_reg:x3;
val_offset:19*FLEN/8; correctval:??; testreg:x2;
fcsr_val: 0 */
TEST_FPSR_OP_NRM(fcvt.d.s, f4, f18, 0, 0, x3, 19*FLEN/8, x4, x1, x2)
inst_20:
// rs1==f29, rd==f12,fs1 == 1 and fe1 == 0x7f and fm1 == 0x600000 and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffffffff
/* opcode: fcvt.d.s ; op1:f29; dest:f12; op1val:0x87f0000000600000; valaddr_reg:x3;
val_offset:20*FLEN/8; correctval:??; testreg:x2;
fcsr_val: 0 */
TEST_FPSR_OP_NRM(fcvt.d.s, f12, f29, 0, 0, x3, 20*FLEN/8, x4, x1, x2)
inst_21:
// rs1==f19, rd==f16,fs1 == 1 and fe1 == 0x80 and fm1 == 0x000000 and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffffffff
/* opcode: fcvt.d.s ; op1:f19; dest:f16; op1val:0x8800000000000000; valaddr_reg:x3;
val_offset:21*FLEN/8; correctval:??; testreg:x2;
fcsr_val: 0 */
TEST_FPSR_OP_NRM(fcvt.d.s, f16, f19, 0, 0, x3, 21*FLEN/8, x4, x1, x2)
inst_22:
// rs1==f3, rd==f5,fs1 == 1 and fe1 == 0x80 and fm1 == 0x100000 and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffffffff
/* opcode: fcvt.d.s ; op1:f3; dest:f5; op1val:0x8800000000100000; valaddr_reg:x3;
val_offset:22*FLEN/8; correctval:??; testreg:x2;
fcsr_val: 0 */
TEST_FPSR_OP_NRM(fcvt.d.s, f5, f3, 0, 0, x3, 22*FLEN/8, x4, x1, x2)
inst_23:
// rs1==f28, rd==f0,fs1 == 1 and fe1 == 0x80 and fm1 == 0x200000 and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffffffff
/* opcode: fcvt.d.s ; op1:f28; dest:f0; op1val:0x8800000000200000; valaddr_reg:x3;
val_offset:23*FLEN/8; correctval:??; testreg:x2;
fcsr_val: 0 */
TEST_FPSR_OP_NRM(fcvt.d.s, f0, f28, 0, 0, x3, 23*FLEN/8, x4, x1, x2)
inst_24:
// rs1==f0, rd==f6,fs1 == 1 and fe1 == 0x80 and fm1 == 0x300000 and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffffffff
/* opcode: fcvt.d.s ; op1:f0; dest:f6; op1val:0x8800000000300000; valaddr_reg:x3;
val_offset:24*FLEN/8; correctval:??; testreg:x2;
fcsr_val: 0 */
TEST_FPSR_OP_NRM(fcvt.d.s, f6, f0, 0, 0, x3, 24*FLEN/8, x4, x1, x2)
inst_25:
// rs1==f14, rd==f8,fs1 == 1 and fe1 == 0x9d and fm1 == 0x4b3d25 and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffffffff
/* opcode: fcvt.d.s ; op1:f14; dest:f8; op1val:0x89d00000004b3d25; valaddr_reg:x3;
val_offset:25*FLEN/8; correctval:??; testreg:x2;
fcsr_val: 0 */
TEST_FPSR_OP_NRM(fcvt.d.s, f8, f14, 0, 0, x3, 25*FLEN/8, x4, x1, x2)
inst_26:
// rs1==f24, rd==f30,fs1 == 1 and fe1 == 0x9e and fm1 == 0x000000 and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffffffff
/* opcode: fcvt.d.s ; op1:f24; dest:f30; op1val:0x89e0000000000000; valaddr_reg:x3;
val_offset:26*FLEN/8; correctval:??; testreg:x2;
fcsr_val: 0 */
TEST_FPSR_OP_NRM(fcvt.d.s, f30, f24, 0, 0, x3, 26*FLEN/8, x4, x1, x2)
inst_27:
// rs1==f5, rd==f22,fs1 == 1 and fe1 == 0xff and fm1 == 0x000000 and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffffffff
/* opcode: fcvt.d.s ; op1:f5; dest:f22; op1val:0x8ff0000000000000; valaddr_reg:x3;
val_offset:27*FLEN/8; correctval:??; testreg:x2;
fcsr_val: 0 */
TEST_FPSR_OP_NRM(fcvt.d.s, f22, f5, 0, 0, x3, 27*FLEN/8, x4, x1, x2)
inst_28:
// rs1==f9, rd==f2,
/* opcode: fcvt.d.s ; op1:f9; dest:f2; op1val:0x0; valaddr_reg:x3;
val_offset:28*FLEN/8; correctval:??; testreg:x2;
fcsr_val: 0 */
TEST_FPSR_OP_NRM(fcvt.d.s, f2, f9, 0, 0, x3, 28*FLEN/8, x4, x1, x2)
inst_29:
// rs1==f31, rd==f23,
/* opcode: fcvt.d.s ; op1:f31; dest:f23; op1val:0x0; valaddr_reg:x3;
val_offset:29*FLEN/8; correctval:??; testreg:x2;
fcsr_val: 0 */
TEST_FPSR_OP_NRM(fcvt.d.s, f23, f31, 0, 0, x3, 29*FLEN/8, x4, x1, x2)
inst_30:
// rs1==f20, rd==f19,
/* opcode: fcvt.d.s ; op1:f20; dest:f19; op1val:0x0; valaddr_reg:x3;
val_offset:30*FLEN/8; correctval:??; testreg:x2;
fcsr_val: 0 */
TEST_FPSR_OP_NRM(fcvt.d.s, f19, f20, 0, 0, x3, 30*FLEN/8, x4, x1, x2)
inst_31:
// rs1==f12, rd==f18,
/* opcode: fcvt.d.s ; op1:f12; dest:f18; op1val:0x0; valaddr_reg:x3;
val_offset:31*FLEN/8; correctval:??; testreg:x2;
fcsr_val: 0 */
TEST_FPSR_OP_NRM(fcvt.d.s, f18, f12, 0, 0, x3, 31*FLEN/8, x4, x1, x2)
inst_32:
// fs1 == 0 and fe1 == 0x00 and fm1 == 0x000000 and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffffffff
/* opcode: fcvt.d.s ; op1:f30; dest:f31; op1val:0x0; valaddr_reg:x3;
val_offset:32*FLEN/8; correctval:??; testreg:x2;
fcsr_val: 0 */
TEST_FPSR_OP_NRM(fcvt.d.s, f31, f30, 0, 0, x3, 32*FLEN/8, x4, x1, x2)
#endif
RVTEST_CODE_END
RVMODEL_HALT
RVTEST_DATA_BEGIN
.align 4
rvtest_data:
.word 0xbabecafe
.word 0xabecafeb
.word 0xbecafeba
.word 0xecafebab
test_dataset_0:
NAN_BOXED(0,64,FLEN)
NAN_BOXED(567453553049880432,64,FLEN)
NAN_BOXED(571957152676052992,64,FLEN)
NAN_BOXED(571957152678150144,64,FLEN)
NAN_BOXED(571957152680247296,64,FLEN)
NAN_BOXED(571957152682344448,64,FLEN)
NAN_BOXED(576460752303423488,64,FLEN)
NAN_BOXED(576460752304472064,64,FLEN)
NAN_BOXED(576460752305520640,64,FLEN)
NAN_BOXED(576460752306569216,64,FLEN)
NAN_BOXED(702561541875799896,64,FLEN)
NAN_BOXED(707065141505556479,64,FLEN)
NAN_BOXED(1148417904979476480,64,FLEN)
NAN_BOXED(1148417904979476481,64,FLEN)
NAN_BOXED(1148417904983670785,64,FLEN)
NAN_BOXED(9223372036854775808,64,FLEN)
NAN_BOXED(9786321990281856106,64,FLEN)
NAN_BOXED(9795329189530828800,64,FLEN)
NAN_BOXED(9795329189532925952,64,FLEN)
NAN_BOXED(9795329189535023104,64,FLEN)
NAN_BOXED(9795329189537120256,64,FLEN)
NAN_BOXED(9799832789158199296,64,FLEN)
NAN_BOXED(9799832789159247872,64,FLEN)
NAN_BOXED(9799832789160296448,64,FLEN)
NAN_BOXED(9799832789161345024,64,FLEN)
NAN_BOXED(9930437178356874533,64,FLEN)
NAN_BOXED(9934940777979314176,64,FLEN)
NAN_BOXED(10371789941834252288,64,FLEN)
NAN_BOXED(0,64,FLEN)
NAN_BOXED(0,64,FLEN)
NAN_BOXED(0,64,FLEN)
NAN_BOXED(0,64,FLEN)
NAN_BOXED(0,64,FLEN)
RVTEST_DATA_END
RVMODEL_DATA_BEGIN
rvtest_sig_begin:
sig_begin_canary:
CANARY;
signature_x1_0:
.fill 0*((SIGALIGN)/4),4,0xdeadbeef
signature_x1_1:
.fill 66*((SIGALIGN)/4),4,0xdeadbeef
#ifdef rvtest_mtrap_routine
tsig_begin_canary:
CANARY;
tsig_begin_canary:
CANARY;
mtrap_sigptr:
.fill 64*(XLEN/32),4,0xdeadbeef
tsig_end_canary:
CANARY;
tsig_end_canary:
CANARY;
#endif
#ifdef rvtest_gpr_save
gpr_save:
.fill 32*XLEN/32,4,0xdeadbeef
#endif
sig_end_canary:
CANARY;
rvtest_sig_end:
RVMODEL_DATA_END

356
vendor/riscv-arch-tests/riscv-test-suite/rv32i_m/D/src/fcvt.d.s_b29-01.S vendored
View file

@ -1,356 +0,0 @@
// -----------
// This file was generated by riscv_ctg (https://github.com/riscv-software-src/riscv-ctg)
// version : 0.7.1
// timestamp : Fri Jun 17 14:03:32 2022 GMT
// usage : riscv_ctg \
// -- cgf // --cgf /scratch/pawan/work/normalised/RV32D/fcvt.d.s.cgf \
\
// -- xlen 32 \
// --randomize \
// -----------
//
// -----------
// Copyright (c) 2020. RISC-V International. All rights reserved.
// SPDX-License-Identifier: BSD-3-Clause
// -----------
//
// This assembly file tests the fcvt.d.s instruction of the RISC-V RV32FD_Zicsr,RV64FD_Zicsr extension for the fcvt.d.s_b29 covergroup.
//
#include "model_test.h"
#include "arch_test.h"
RVTEST_ISA("RV32IFD_Zicsr,RV64IFD_Zicsr")
.section .text.init
.org 0x80
.globl rvtest_entry_point
rvtest_entry_point:
RVMODEL_BOOT
RVTEST_CODE_BEGIN
#ifdef TEST_CASE_1
RVTEST_CASE(0,"//check ISA:=regex(.*I.*D.*);def TEST_CASE_1=True;",fcvt.d.s_b29)
RVTEST_FP_ENABLE()
RVTEST_VALBASEUPD(x3,test_dataset_0)
RVTEST_SIGBASE(x1,signature_x1_1)
inst_0:
// rs1 == rd, rs1==f11, rd==f11,fs1 == 0 and fe1 == 0x7c and fm1 == 0x4923b8 and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffffffff
/* opcode: fcvt.d.s ; op1:f11; dest:f11; op1val:0x7c00000004923b8; valaddr_reg:x3;
val_offset:0*FLEN/8; correctval:??; testreg:x2;
fcsr_val: 0 */
TEST_FPSR_OP_NRM(fcvt.d.s, f11, f11, 0, 0, x3, 0*FLEN/8, x4, x1, x2)
inst_1:
// rs1 != rd, rs1==f30, rd==f4,fs1 == 0 and fe1 == 0x7c and fm1 == 0x4923b9 and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffffffff
/* opcode: fcvt.d.s ; op1:f30; dest:f4; op1val:0x7c00000004923b9; valaddr_reg:x3;
val_offset:1*FLEN/8; correctval:??; testreg:x2;
fcsr_val: 0 */
TEST_FPSR_OP_NRM(fcvt.d.s, f4, f30, 0, 0, x3, 1*FLEN/8, x4, x1, x2)
inst_2:
// rs1==f31, rd==f26,fs1 == 0 and fe1 == 0x7c and fm1 == 0x4923ba and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffffffff
/* opcode: fcvt.d.s ; op1:f31; dest:f26; op1val:0x7c00000004923ba; valaddr_reg:x3;
val_offset:2*FLEN/8; correctval:??; testreg:x2;
fcsr_val: 0 */
TEST_FPSR_OP_NRM(fcvt.d.s, f26, f31, 0, 0, x3, 2*FLEN/8, x4, x1, x2)
inst_3:
// rs1==f1, rd==f17,fs1 == 0 and fe1 == 0x7c and fm1 == 0x4923bb and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffffffff
/* opcode: fcvt.d.s ; op1:f1; dest:f17; op1val:0x7c00000004923bb; valaddr_reg:x3;
val_offset:3*FLEN/8; correctval:??; testreg:x2;
fcsr_val: 0 */
TEST_FPSR_OP_NRM(fcvt.d.s, f17, f1, 0, 0, x3, 3*FLEN/8, x4, x1, x2)
inst_4:
// rs1==f21, rd==f20,fs1 == 0 and fe1 == 0x7c and fm1 == 0x4923bc and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffffffff
/* opcode: fcvt.d.s ; op1:f21; dest:f20; op1val:0x7c00000004923bc; valaddr_reg:x3;
val_offset:4*FLEN/8; correctval:??; testreg:x2;
fcsr_val: 0 */
TEST_FPSR_OP_NRM(fcvt.d.s, f20, f21, 0, 0, x3, 4*FLEN/8, x4, x1, x2)
inst_5:
// rs1==f16, rd==f10,fs1 == 0 and fe1 == 0x7c and fm1 == 0x4923bd and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffffffff
/* opcode: fcvt.d.s ; op1:f16; dest:f10; op1val:0x7c00000004923bd; valaddr_reg:x3;
val_offset:5*FLEN/8; correctval:??; testreg:x2;
fcsr_val: 0 */
TEST_FPSR_OP_NRM(fcvt.d.s, f10, f16, 0, 0, x3, 5*FLEN/8, x4, x1, x2)
inst_6:
// rs1==f20, rd==f24,fs1 == 0 and fe1 == 0x7c and fm1 == 0x4923be and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffffffff
/* opcode: fcvt.d.s ; op1:f20; dest:f24; op1val:0x7c00000004923be; valaddr_reg:x3;
val_offset:6*FLEN/8; correctval:??; testreg:x2;
fcsr_val: 0 */
TEST_FPSR_OP_NRM(fcvt.d.s, f24, f20, 0, 0, x3, 6*FLEN/8, x4, x1, x2)
inst_7:
// rs1==f14, rd==f3,fs1 == 0 and fe1 == 0x7c and fm1 == 0x4923bf and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffffffff
/* opcode: fcvt.d.s ; op1:f14; dest:f3; op1val:0x7c00000004923bf; valaddr_reg:x3;
val_offset:7*FLEN/8; correctval:??; testreg:x2;
fcsr_val: 0 */
TEST_FPSR_OP_NRM(fcvt.d.s, f3, f14, 0, 0, x3, 7*FLEN/8, x4, x1, x2)
inst_8:
// rs1==f12, rd==f28,fs1 == 1 and fe1 == 0x7c and fm1 == 0x4923b8 and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffffffff
/* opcode: fcvt.d.s ; op1:f12; dest:f28; op1val:0x87c00000004923b8; valaddr_reg:x3;
val_offset:8*FLEN/8; correctval:??; testreg:x2;
fcsr_val: 0 */
TEST_FPSR_OP_NRM(fcvt.d.s, f28, f12, 0, 0, x3, 8*FLEN/8, x4, x1, x2)
inst_9:
// rs1==f7, rd==f2,fs1 == 1 and fe1 == 0x7c and fm1 == 0x4923b9 and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffffffff
/* opcode: fcvt.d.s ; op1:f7; dest:f2; op1val:0x87c00000004923b9; valaddr_reg:x3;
val_offset:9*FLEN/8; correctval:??; testreg:x2;
fcsr_val: 0 */
TEST_FPSR_OP_NRM(fcvt.d.s, f2, f7, 0, 0, x3, 9*FLEN/8, x4, x1, x2)
inst_10:
// rs1==f26, rd==f29,fs1 == 1 and fe1 == 0x7c and fm1 == 0x4923ba and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffffffff
/* opcode: fcvt.d.s ; op1:f26; dest:f29; op1val:0x87c00000004923ba; valaddr_reg:x3;
val_offset:10*FLEN/8; correctval:??; testreg:x2;
fcsr_val: 0 */
TEST_FPSR_OP_NRM(fcvt.d.s, f29, f26, 0, 0, x3, 10*FLEN/8, x4, x1, x2)
inst_11:
// rs1==f24, rd==f6,fs1 == 1 and fe1 == 0x7c and fm1 == 0x4923bb and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffffffff
/* opcode: fcvt.d.s ; op1:f24; dest:f6; op1val:0x87c00000004923bb; valaddr_reg:x3;
val_offset:11*FLEN/8; correctval:??; testreg:x2;
fcsr_val: 0 */
TEST_FPSR_OP_NRM(fcvt.d.s, f6, f24, 0, 0, x3, 11*FLEN/8, x4, x1, x2)
inst_12:
// rs1==f0, rd==f21,fs1 == 1 and fe1 == 0x7c and fm1 == 0x4923bc and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffffffff
/* opcode: fcvt.d.s ; op1:f0; dest:f21; op1val:0x87c00000004923bc; valaddr_reg:x3;
val_offset:12*FLEN/8; correctval:??; testreg:x2;
fcsr_val: 0 */
TEST_FPSR_OP_NRM(fcvt.d.s, f21, f0, 0, 0, x3, 12*FLEN/8, x4, x1, x2)
inst_13:
// rs1==f18, rd==f9,fs1 == 1 and fe1 == 0x7c and fm1 == 0x4923bd and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffffffff
/* opcode: fcvt.d.s ; op1:f18; dest:f9; op1val:0x87c00000004923bd; valaddr_reg:x3;
val_offset:13*FLEN/8; correctval:??; testreg:x2;
fcsr_val: 0 */
TEST_FPSR_OP_NRM(fcvt.d.s, f9, f18, 0, 0, x3, 13*FLEN/8, x4, x1, x2)
inst_14:
// rs1==f6, rd==f22,fs1 == 1 and fe1 == 0x7c and fm1 == 0x4923be and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffffffff
/* opcode: fcvt.d.s ; op1:f6; dest:f22; op1val:0x87c00000004923be; valaddr_reg:x3;
val_offset:14*FLEN/8; correctval:??; testreg:x2;
fcsr_val: 0 */
TEST_FPSR_OP_NRM(fcvt.d.s, f22, f6, 0, 0, x3, 14*FLEN/8, x4, x1, x2)
inst_15:
// rs1==f15, rd==f16,fs1 == 1 and fe1 == 0x7c and fm1 == 0x4923bf and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffffffff
/* opcode: fcvt.d.s ; op1:f15; dest:f16; op1val:0x87c00000004923bf; valaddr_reg:x3;
val_offset:15*FLEN/8; correctval:??; testreg:x2;
fcsr_val: 0 */
TEST_FPSR_OP_NRM(fcvt.d.s, f16, f15, 0, 0, x3, 15*FLEN/8, x4, x1, x2)
inst_16:
// rs1==f17, rd==f18,
/* opcode: fcvt.d.s ; op1:f17; dest:f18; op1val:0x0; valaddr_reg:x3;
val_offset:16*FLEN/8; correctval:??; testreg:x2;
fcsr_val: 0 */
TEST_FPSR_OP_NRM(fcvt.d.s, f18, f17, 0, 0, x3, 16*FLEN/8, x4, x1, x2)
inst_17:
// rs1==f23, rd==f27,
/* opcode: fcvt.d.s ; op1:f23; dest:f27; op1val:0x0; valaddr_reg:x3;
val_offset:17*FLEN/8; correctval:??; testreg:x2;
fcsr_val: 0 */
TEST_FPSR_OP_NRM(fcvt.d.s, f27, f23, 0, 0, x3, 17*FLEN/8, x4, x1, x2)
inst_18:
// rs1==f25, rd==f15,
/* opcode: fcvt.d.s ; op1:f25; dest:f15; op1val:0x0; valaddr_reg:x3;
val_offset:18*FLEN/8; correctval:??; testreg:x2;
fcsr_val: 0 */
TEST_FPSR_OP_NRM(fcvt.d.s, f15, f25, 0, 0, x3, 18*FLEN/8, x4, x1, x2)
inst_19:
// rs1==f9, rd==f23,
/* opcode: fcvt.d.s ; op1:f9; dest:f23; op1val:0x0; valaddr_reg:x3;
val_offset:19*FLEN/8; correctval:??; testreg:x2;
fcsr_val: 0 */
TEST_FPSR_OP_NRM(fcvt.d.s, f23, f9, 0, 0, x3, 19*FLEN/8, x4, x1, x2)
inst_20:
// rs1==f10, rd==f5,
/* opcode: fcvt.d.s ; op1:f10; dest:f5; op1val:0x0; valaddr_reg:x3;
val_offset:20*FLEN/8; correctval:??; testreg:x2;
fcsr_val: 0 */
TEST_FPSR_OP_NRM(fcvt.d.s, f5, f10, 0, 0, x3, 20*FLEN/8, x4, x1, x2)
inst_21:
// rs1==f28, rd==f1,
/* opcode: fcvt.d.s ; op1:f28; dest:f1; op1val:0x0; valaddr_reg:x3;
val_offset:21*FLEN/8; correctval:??; testreg:x2;
fcsr_val: 0 */
TEST_FPSR_OP_NRM(fcvt.d.s, f1, f28, 0, 0, x3, 21*FLEN/8, x4, x1, x2)
inst_22:
// rs1==f8, rd==f30,
/* opcode: fcvt.d.s ; op1:f8; dest:f30; op1val:0x0; valaddr_reg:x3;
val_offset:22*FLEN/8; correctval:??; testreg:x2;
fcsr_val: 0 */
TEST_FPSR_OP_NRM(fcvt.d.s, f30, f8, 0, 0, x3, 22*FLEN/8, x4, x1, x2)
inst_23:
// rs1==f22, rd==f0,
/* opcode: fcvt.d.s ; op1:f22; dest:f0; op1val:0x0; valaddr_reg:x3;
val_offset:23*FLEN/8; correctval:??; testreg:x2;
fcsr_val: 0 */
TEST_FPSR_OP_NRM(fcvt.d.s, f0, f22, 0, 0, x3, 23*FLEN/8, x4, x1, x2)
inst_24:
// rs1==f19, rd==f12,
/* opcode: fcvt.d.s ; op1:f19; dest:f12; op1val:0x0; valaddr_reg:x3;
val_offset:24*FLEN/8; correctval:??; testreg:x2;
fcsr_val: 0 */
TEST_FPSR_OP_NRM(fcvt.d.s, f12, f19, 0, 0, x3, 24*FLEN/8, x4, x1, x2)
inst_25:
// rs1==f5, rd==f25,
/* opcode: fcvt.d.s ; op1:f5; dest:f25; op1val:0x0; valaddr_reg:x3;
val_offset:25*FLEN/8; correctval:??; testreg:x2;
fcsr_val: 0 */
TEST_FPSR_OP_NRM(fcvt.d.s, f25, f5, 0, 0, x3, 25*FLEN/8, x4, x1, x2)
inst_26:
// rs1==f27, rd==f7,
/* opcode: fcvt.d.s ; op1:f27; dest:f7; op1val:0x0; valaddr_reg:x3;
val_offset:26*FLEN/8; correctval:??; testreg:x2;
fcsr_val: 0 */
TEST_FPSR_OP_NRM(fcvt.d.s, f7, f27, 0, 0, x3, 26*FLEN/8, x4, x1, x2)
inst_27:
// rs1==f3, rd==f8,
/* opcode: fcvt.d.s ; op1:f3; dest:f8; op1val:0x0; valaddr_reg:x3;
val_offset:27*FLEN/8; correctval:??; testreg:x2;
fcsr_val: 0 */
TEST_FPSR_OP_NRM(fcvt.d.s, f8, f3, 0, 0, x3, 27*FLEN/8, x4, x1, x2)
inst_28:
// rs1==f2, rd==f14,
/* opcode: fcvt.d.s ; op1:f2; dest:f14; op1val:0x0; valaddr_reg:x3;
val_offset:28*FLEN/8; correctval:??; testreg:x2;
fcsr_val: 0 */
TEST_FPSR_OP_NRM(fcvt.d.s, f14, f2, 0, 0, x3, 28*FLEN/8, x4, x1, x2)
inst_29:
// rs1==f29, rd==f13,
/* opcode: fcvt.d.s ; op1:f29; dest:f13; op1val:0x0; valaddr_reg:x3;
val_offset:29*FLEN/8; correctval:??; testreg:x2;
fcsr_val: 0 */
TEST_FPSR_OP_NRM(fcvt.d.s, f13, f29, 0, 0, x3, 29*FLEN/8, x4, x1, x2)
inst_30:
// rs1==f13, rd==f19,
/* opcode: fcvt.d.s ; op1:f13; dest:f19; op1val:0x0; valaddr_reg:x3;
val_offset:30*FLEN/8; correctval:??; testreg:x2;
fcsr_val: 0 */
TEST_FPSR_OP_NRM(fcvt.d.s, f19, f13, 0, 0, x3, 30*FLEN/8, x4, x1, x2)
inst_31:
// rs1==f4, rd==f31,
/* opcode: fcvt.d.s ; op1:f4; dest:f31; op1val:0x0; valaddr_reg:x3;
val_offset:31*FLEN/8; correctval:??; testreg:x2;
fcsr_val: 0 */
TEST_FPSR_OP_NRM(fcvt.d.s, f31, f4, 0, 0, x3, 31*FLEN/8, x4, x1, x2)
inst_32:
// fs1 == 0 and fe1 == 0x7c and fm1 == 0x4923b8 and fcsr == 0x0 and rm_val == 7 and rs1_nan_prefix == 0xffffffff
/* opcode: fcvt.d.s ; op1:f30; dest:f31; op1val:0x7c00000004923b8; valaddr_reg:x3;
val_offset:32*FLEN/8; correctval:??; testreg:x2;
fcsr_val: 0 */
TEST_FPSR_OP_NRM(fcvt.d.s, f31, f30, 0, 0, x3, 32*FLEN/8, x4, x1, x2)
#endif
RVTEST_CODE_END
RVMODEL_HALT
RVTEST_DATA_BEGIN
.align 4
rvtest_data:
.word 0xbabecafe
.word 0xabecafeb
.word 0xbecafeba
.word 0xecafebab
test_dataset_0:
NAN_BOXED(558446353798734776,64,FLEN)
NAN_BOXED(558446353798734777,64,FLEN)
NAN_BOXED(558446353798734778,64,FLEN)
NAN_BOXED(558446353798734779,64,FLEN)
NAN_BOXED(558446353798734780,64,FLEN)
NAN_BOXED(558446353798734781,64,FLEN)
NAN_BOXED(558446353798734782,64,FLEN)
NAN_BOXED(558446353798734783,64,FLEN)
NAN_BOXED(9781818390653510584,64,FLEN)
NAN_BOXED(9781818390653510585,64,FLEN)
NAN_BOXED(9781818390653510586,64,FLEN)
NAN_BOXED(9781818390653510587,64,FLEN)
NAN_BOXED(9781818390653510588,64,FLEN)
NAN_BOXED(9781818390653510589,64,FLEN)
NAN_BOXED(9781818390653510590,64,FLEN)
NAN_BOXED(9781818390653510591,64,FLEN)
NAN_BOXED(0,64,FLEN)
NAN_BOXED(0,64,FLEN)
NAN_BOXED(0,64,FLEN)
NAN_BOXED(0,64,FLEN)
NAN_BOXED(0,64,FLEN)
NAN_BOXED(0,64,FLEN)
NAN_BOXED(0,64,FLEN)
NAN_BOXED(0,64,FLEN)
NAN_BOXED(0,64,FLEN)
NAN_BOXED(0,64,FLEN)
NAN_BOXED(0,64,FLEN)
NAN_BOXED(0,64,FLEN)
NAN_BOXED(0,64,FLEN)
NAN_BOXED(0,64,FLEN)
NAN_BOXED(0,64,FLEN)
NAN_BOXED(0,64,FLEN)
NAN_BOXED(558446353798734776,64,FLEN)
RVTEST_DATA_END
RVMODEL_DATA_BEGIN
rvtest_sig_begin:
sig_begin_canary:
CANARY;
signature_x1_0:
.fill 0*((SIGALIGN)/4),4,0xdeadbeef
signature_x1_1:
.fill 66*((SIGALIGN)/4),4,0xdeadbeef
#ifdef rvtest_mtrap_routine
tsig_begin_canary:
CANARY;
tsig_begin_canary:
CANARY;
mtrap_sigptr:
.fill 64*(XLEN/32),4,0xdeadbeef
tsig_end_canary:
CANARY;
tsig_end_canary:
CANARY;
#endif
#ifdef rvtest_gpr_save
gpr_save:
.fill 32*XLEN/32,4,0xdeadbeef
#endif
sig_end_canary:
CANARY;
rvtest_sig_end:
RVMODEL_DATA_END

330
vendor/riscv-arch-tests/riscv-test-suite/rv32i_m/D/src/fcvt.d.w_b25-01.S vendored
View file

@ -1,330 +0,0 @@
// -----------
// This file was generated by riscv_ctg (https://github.com/riscv-software-src/riscv-ctg)
// version : 0.7.1
// timestamp : Tue Jun 28 05:47:56 2022 GMT
// usage : riscv_ctg \
// -- cgf // --cgf /scratch/pawan/work/normalised/RV32D/fcvt.d.w.cgf \
\
// -- xlen 32 \
// --randomize \
// -----------
//
// -----------
// Copyright (c) 2020. RISC-V International. All rights reserved.
// SPDX-License-Identifier: BSD-3-Clause
// -----------
//
// This assembly file tests the fcvt.d.w instruction of the RISC-V RV32FD_Zicsr,RV64FD_Zicsr extension for the fcvt.d.w_b25 covergroup.
//
#include "model_test.h"
#include "arch_test.h"
RVTEST_ISA("RV32IFD_Zicsr,RV64IFD_Zicsr")
.section .text.init
.org 0x80
.globl rvtest_entry_point
rvtest_entry_point:
RVMODEL_BOOT
RVTEST_CODE_BEGIN
#ifdef TEST_CASE_1
RVTEST_CASE(0,"//check ISA:=regex(.*I.*D.*);def TEST_CASE_1=True;",fcvt.d.w_b25)
RVTEST_FP_ENABLE()
RVTEST_VALBASEUPD(x11,test_dataset_0)
RVTEST_SIGBASE(x3,signature_x3_1)
inst_0:// rs1==x14, rd==f6,rs1_val == 0 and fcsr == 0 and rm_val == 7
/* opcode: fcvt.d.w ; op1:x14; dest:f6; op1val:0x0; valaddr_reg:x11;
val_offset:0*4; correctval:??; testreg:x13;
fcsr_val: 0*/
TEST_FPIO_OP_NRM(fcvt.d.w, f6, x14, 0, 0, x11, 0*4, x17, x3, x13,lw)
inst_1:// rs1==x26, rd==f24,rs1_val == 1 and fcsr == 0 and rm_val == 7
/* opcode: fcvt.d.w ; op1:x26; dest:f24; op1val:0x1; valaddr_reg:x11;
val_offset:1*4; correctval:??; testreg:x13;
fcsr_val: 0*/
TEST_FPIO_OP_NRM(fcvt.d.w, f24, x26, 0, 0, x11, 1*4, x17, x3, x13,lw)
inst_2:// rs1==x4, rd==f13,rs1_val == -1 and fcsr == 0 and rm_val == 7
/* opcode: fcvt.d.w ; op1:x4; dest:f13; op1val:-0x1; valaddr_reg:x11;
val_offset:2*4; correctval:??; testreg:x13;
fcsr_val: 0*/
TEST_FPIO_OP_NRM(fcvt.d.w, f13, x4, 0, 0, x11, 2*4, x17, x3, x13,lw)
inst_3:// rs1==x15, rd==f17,rs1_val == 2147483647 and fcsr == 0 and rm_val == 7
/* opcode: fcvt.d.w ; op1:x15; dest:f17; op1val:0x7fffffff; valaddr_reg:x11;
val_offset:3*4; correctval:??; testreg:x13;
fcsr_val: 0*/
TEST_FPIO_OP_NRM(fcvt.d.w, f17, x15, 0, 0, x11, 3*4, x17, x3, x13,lw)
inst_4:// rs1==x6, rd==f2,rs1_val == -2147483647 and fcsr == 0 and rm_val == 7
/* opcode: fcvt.d.w ; op1:x6; dest:f2; op1val:-0x7fffffff; valaddr_reg:x11;
val_offset:4*4; correctval:??; testreg:x13;
fcsr_val: 0*/
TEST_FPIO_OP_NRM(fcvt.d.w, f2, x6, 0, 0, x11, 4*4, x17, x3, x13,lw)
inst_5:// rs1==x18, rd==f5,rs1_val == 1227077728 and fcsr == 0 and rm_val == 7
/* opcode: fcvt.d.w ; op1:x18; dest:f5; op1val:0x4923b860; valaddr_reg:x11;
val_offset:5*4; correctval:??; testreg:x13;
fcsr_val: 0*/
TEST_FPIO_OP_NRM(fcvt.d.w, f5, x18, 0, 0, x11, 5*4, x17, x3, x13,lw)
inst_6:// rs1==x31, rd==f7,rs1_val == -1227077728 and fcsr == 0 and rm_val == 7
/* opcode: fcvt.d.w ; op1:x31; dest:f7; op1val:-0x4923b860; valaddr_reg:x11;
val_offset:6*4; correctval:??; testreg:x13;
fcsr_val: 0*/
TEST_FPIO_OP_NRM(fcvt.d.w, f7, x31, 0, 0, x11, 6*4, x17, x3, x13,lw)
inst_7:// rs1==x27, rd==f22,
/* opcode: fcvt.d.w ; op1:x27; dest:f22; op1val:0x0; valaddr_reg:x11;
val_offset:7*4; correctval:??; testreg:x13;
fcsr_val: 0*/
TEST_FPIO_OP_NRM(fcvt.d.w, f22, x27, 0, 0, x11, 7*4, x17, x3, x13,lw)
inst_8:// rs1==x28, rd==f10,
/* opcode: fcvt.d.w ; op1:x28; dest:f10; op1val:0x0; valaddr_reg:x11;
val_offset:8*4; correctval:??; testreg:x13;
fcsr_val: 0*/
TEST_FPIO_OP_NRM(fcvt.d.w, f10, x28, 0, 0, x11, 8*4, x17, x3, x13,lw)
inst_9:// rs1==x22, rd==f0,
/* opcode: fcvt.d.w ; op1:x22; dest:f0; op1val:0x0; valaddr_reg:x11;
val_offset:9*4; correctval:??; testreg:x13;
fcsr_val: 0*/
TEST_FPIO_OP_NRM(fcvt.d.w, f0, x22, 0, 0, x11, 9*4, x17, x3, x13,lw)
inst_10:// rs1==x19, rd==f8,
/* opcode: fcvt.d.w ; op1:x19; dest:f8; op1val:0x0; valaddr_reg:x11;
val_offset:10*4; correctval:??; testreg:x13;
fcsr_val: 0*/
TEST_FPIO_OP_NRM(fcvt.d.w, f8, x19, 0, 0, x11, 10*4, x17, x3, x13,lw)
inst_11:// rs1==x8, rd==f12,
/* opcode: fcvt.d.w ; op1:x8; dest:f12; op1val:0x0; valaddr_reg:x11;
val_offset:11*4; correctval:??; testreg:x13;
fcsr_val: 0*/
TEST_FPIO_OP_NRM(fcvt.d.w, f12, x8, 0, 0, x11, 11*4, x17, x3, x13,lw)
inst_12:// rs1==x7, rd==f23,
/* opcode: fcvt.d.w ; op1:x7; dest:f23; op1val:0x0; valaddr_reg:x11;
val_offset:12*4; correctval:??; testreg:x13;
fcsr_val: 0*/
TEST_FPIO_OP_NRM(fcvt.d.w, f23, x7, 0, 0, x11, 12*4, x17, x3, x13,lw)
inst_13:// rs1==x2, rd==f25,
/* opcode: fcvt.d.w ; op1:x2; dest:f25; op1val:0x0; valaddr_reg:x11;
val_offset:13*4; correctval:??; testreg:x13;
fcsr_val: 0*/
TEST_FPIO_OP_NRM(fcvt.d.w, f25, x2, 0, 0, x11, 13*4, x17, x3, x13,lw)
inst_14:// rs1==x12, rd==f20,
/* opcode: fcvt.d.w ; op1:x12; dest:f20; op1val:0x0; valaddr_reg:x11;
val_offset:14*4; correctval:??; testreg:x13;
fcsr_val: 0*/
TEST_FPIO_OP_NRM(fcvt.d.w, f20, x12, 0, 0, x11, 14*4, x17, x3, x13,lw)
inst_15:// rs1==x30, rd==f31,
/* opcode: fcvt.d.w ; op1:x30; dest:f31; op1val:0x0; valaddr_reg:x11;
val_offset:15*4; correctval:??; testreg:x13;
fcsr_val: 0*/
TEST_FPIO_OP_NRM(fcvt.d.w, f31, x30, 0, 0, x11, 15*4, x17, x3, x13,lw)
inst_16:// rs1==x24, rd==f16,
/* opcode: fcvt.d.w ; op1:x24; dest:f16; op1val:0x0; valaddr_reg:x11;
val_offset:16*4; correctval:??; testreg:x13;
fcsr_val: 0*/
TEST_FPIO_OP_NRM(fcvt.d.w, f16, x24, 0, 0, x11, 16*4, x17, x3, x13,lw)
inst_17:// rs1==x10, rd==f26,
/* opcode: fcvt.d.w ; op1:x10; dest:f26; op1val:0x0; valaddr_reg:x11;
val_offset:17*4; correctval:??; testreg:x13;
fcsr_val: 0*/
TEST_FPIO_OP_NRM(fcvt.d.w, f26, x10, 0, 0, x11, 17*4, x17, x3, x13,lw)
inst_18:// rs1==x16, rd==f21,
/* opcode: fcvt.d.w ; op1:x16; dest:f21; op1val:0x0; valaddr_reg:x11;
val_offset:18*4; correctval:??; testreg:x13;
fcsr_val: 0*/
TEST_FPIO_OP_NRM(fcvt.d.w, f21, x16, 0, 0, x11, 18*4, x17, x3, x13,lw)
inst_19:// rs1==x21, rd==f11,
/* opcode: fcvt.d.w ; op1:x21; dest:f11; op1val:0x0; valaddr_reg:x11;
val_offset:19*4; correctval:??; testreg:x13;
fcsr_val: 0*/
TEST_FPIO_OP_NRM(fcvt.d.w, f11, x21, 0, 0, x11, 19*4, x17, x3, x13,lw)
inst_20:// rs1==x9, rd==f1,
/* opcode: fcvt.d.w ; op1:x9; dest:f1; op1val:0x0; valaddr_reg:x11;
val_offset:20*4; correctval:??; testreg:x13;
fcsr_val: 0*/
TEST_FPIO_OP_NRM(fcvt.d.w, f1, x9, 0, 0, x11, 20*4, x17, x3, x13,lw)
inst_21:// rs1==x1, rd==f9,
/* opcode: fcvt.d.w ; op1:x1; dest:f9; op1val:0x0; valaddr_reg:x11;
val_offset:21*4; correctval:??; testreg:x13;
fcsr_val: 0*/
TEST_FPIO_OP_NRM(fcvt.d.w, f9, x1, 0, 0, x11, 21*4, x17, x3, x13,lw)
inst_22:// rs1==x29, rd==f27,
/* opcode: fcvt.d.w ; op1:x29; dest:f27; op1val:0x0; valaddr_reg:x11;
val_offset:22*4; correctval:??; testreg:x13;
fcsr_val: 0*/
TEST_FPIO_OP_NRM(fcvt.d.w, f27, x29, 0, 0, x11, 22*4, x17, x3, x13,lw)
inst_23:// rs1==x5, rd==f14,
/* opcode: fcvt.d.w ; op1:x5; dest:f14; op1val:0x0; valaddr_reg:x11;
val_offset:23*4; correctval:??; testreg:x13;
fcsr_val: 0*/
TEST_FPIO_OP_NRM(fcvt.d.w, f14, x5, 0, 0, x11, 23*4, x17, x3, x13,lw)
RVTEST_VALBASEUPD(x4,test_dataset_1)
inst_24:// rs1==x17, rd==f3,
/* opcode: fcvt.d.w ; op1:x17; dest:f3; op1val:0x0; valaddr_reg:x4;
val_offset:0*4; correctval:??; testreg:x13;
fcsr_val: 0*/
TEST_FPIO_OP_NRM(fcvt.d.w, f3, x17, 0, 0, x4, 0*4, x5, x3, x13,lw)
inst_25:// rs1==x11, rd==f30,
/* opcode: fcvt.d.w ; op1:x11; dest:f30; op1val:0x0; valaddr_reg:x4;
val_offset:1*4; correctval:??; testreg:x13;
fcsr_val: 0*/
TEST_FPIO_OP_NRM(fcvt.d.w, f30, x11, 0, 0, x4, 1*4, x5, x3, x13,lw)
inst_26:// rs1==x0, rd==f18,
/* opcode: fcvt.d.w ; op1:x0; dest:f18; op1val:0x0; valaddr_reg:x4;
val_offset:2*4; correctval:??; testreg:x2;
fcsr_val: 0*/
TEST_FPIO_OP_NRM(fcvt.d.w, f18, x0, 0, 0, x4, 2*4, x5, x3, x2,lw)
inst_27:// rs1==x25, rd==f29,
/* opcode: fcvt.d.w ; op1:x25; dest:f29; op1val:0x0; valaddr_reg:x4;
val_offset:3*4; correctval:??; testreg:x2;
fcsr_val: 0*/
TEST_FPIO_OP_NRM(fcvt.d.w, f29, x25, 0, 0, x4, 3*4, x5, x3, x2,lw)
RVTEST_SIGBASE(x1,signature_x1_0)
inst_28:// rs1==x23, rd==f15,
/* opcode: fcvt.d.w ; op1:x23; dest:f15; op1val:0x0; valaddr_reg:x4;
val_offset:4*4; correctval:??; testreg:x2;
fcsr_val: 0*/
TEST_FPIO_OP_NRM(fcvt.d.w, f15, x23, 0, 0, x4, 4*4, x5, x1, x2,lw)
inst_29:// rs1==x20, rd==f4,
/* opcode: fcvt.d.w ; op1:x20; dest:f4; op1val:0x0; valaddr_reg:x4;
val_offset:5*4; correctval:??; testreg:x2;
fcsr_val: 0*/
TEST_FPIO_OP_NRM(fcvt.d.w, f4, x20, 0, 0, x4, 5*4, x5, x1, x2,lw)
inst_30:// rs1==x13, rd==f19,
/* opcode: fcvt.d.w ; op1:x13; dest:f19; op1val:0x0; valaddr_reg:x4;
val_offset:6*4; correctval:??; testreg:x2;
fcsr_val: 0*/
TEST_FPIO_OP_NRM(fcvt.d.w, f19, x13, 0, 0, x4, 6*4, x5, x1, x2,lw)
inst_31:// rs1==x3, rd==f28,
/* opcode: fcvt.d.w ; op1:x3; dest:f28; op1val:0x0; valaddr_reg:x4;
val_offset:7*4; correctval:??; testreg:x2;
fcsr_val: 0*/
TEST_FPIO_OP_NRM(fcvt.d.w, f28, x3, 0, 0, x4, 7*4, x5, x1, x2,lw)
inst_32://
/* opcode: fcvt.d.w ; op1:x31; dest:f31; op1val:0x0; valaddr_reg:x4;
val_offset:8*4; correctval:??; testreg:x2;
fcsr_val: 0*/
TEST_FPIO_OP_NRM(fcvt.d.w, f31, x31, 0, 0, x4, 8*4, x5, x1, x2,lw)
#endif
RVTEST_CODE_END
RVMODEL_HALT
RVTEST_DATA_BEGIN
.align 4
rvtest_data:
.word 0xbabecafe
.word 0xabecafeb
.word 0xbecafeba
.word 0xecafebab
test_dataset_0:
.word 0;
.word 1;
.word -1;
.word 2147483647;
.word -2147483647;
.word 1227077728;
.word -1227077728;
.word 0;
.word 0;
.word 0;
.word 0;
.word 0;
.word 0;
.word 0;
.word 0;
.word 0;
.word 0;
.word 0;
.word 0;
.word 0;
.word 0;
.word 0;
.word 0;
.word 0;
test_dataset_1:
.word 0;
.word 0;
.word 0;
.word 0;
.word 0;
.word 0;
.word 0;
.word 0;
.word 0;
RVTEST_DATA_END
RVMODEL_DATA_BEGIN
rvtest_sig_begin:
sig_begin_canary:
CANARY;
signature_x3_0:
.fill 0*((SIGALIGN)/4),4,0xdeadbeef
signature_x3_1:
.fill 56*((SIGALIGN)/4),4,0xdeadbeef
signature_x1_0:
.fill 10*((SIGALIGN)/4),4,0xdeadbeef
#ifdef rvtest_mtrap_routine
tsig_begin_canary:
CANARY;
tsig_begin_canary:
CANARY;
mtrap_sigptr:
.fill 64*(XLEN/32),4,0xdeadbeef
tsig_end_canary:
CANARY;
tsig_end_canary:
CANARY;
#endif
#ifdef rvtest_gpr_save
gpr_save:
.fill 32*XLEN/32,4,0xdeadbeef
#endif
sig_end_canary:
CANARY;
rvtest_sig_end:
RVMODEL_DATA_END

330
vendor/riscv-arch-tests/riscv-test-suite/rv32i_m/D/src/fcvt.d.w_b26-01.S vendored
View file

@ -1,330 +0,0 @@
// -----------
// This file was generated by riscv_ctg (https://github.com/riscv-software-src/riscv-ctg)
// version : 0.7.1
// timestamp : Tue Jun 28 05:47:56 2022 GMT
// usage : riscv_ctg \
// -- cgf // --cgf /scratch/pawan/work/normalised/RV32D/fcvt.d.w.cgf \
\
// -- xlen 32 \
// --randomize \
// -----------
//
// -----------
// Copyright (c) 2020. RISC-V International. All rights reserved.
// SPDX-License-Identifier: BSD-3-Clause
// -----------
//
// This assembly file tests the fcvt.d.w instruction of the RISC-V RV32FD_Zicsr,RV64FD_Zicsr extension for the fcvt.d.w_b26 covergroup.
//
#include "model_test.h"
#include "arch_test.h"
RVTEST_ISA("RV32IFD_Zicsr,RV64IFD_Zicsr")
.section .text.init
.org 0x80
.globl rvtest_entry_point
rvtest_entry_point:
RVMODEL_BOOT
RVTEST_CODE_BEGIN
#ifdef TEST_CASE_1
RVTEST_CASE(0,"//check ISA:=regex(.*I.*D.*);def TEST_CASE_1=True;",fcvt.d.w_b26)
RVTEST_FP_ENABLE()
RVTEST_VALBASEUPD(x12,test_dataset_0)
RVTEST_SIGBASE(x7,signature_x7_1)
inst_0:// rs1==x28, rd==f5,rs1_val == 0 and fcsr == 0 and rm_val == 7
/* opcode: fcvt.d.w ; op1:x28; dest:f5; op1val:0x0; valaddr_reg:x12;
val_offset:0*4; correctval:??; testreg:x15;
fcsr_val: 0*/
TEST_FPIO_OP_NRM(fcvt.d.w, f5, x28, 0, 0, x12, 0*4, x18, x7, x15,lw)
inst_1:// rs1==x1, rd==f19,rs1_val == 1 and fcsr == 0 and rm_val == 7
/* opcode: fcvt.d.w ; op1:x1; dest:f19; op1val:0x1; valaddr_reg:x12;
val_offset:1*4; correctval:??; testreg:x15;
fcsr_val: 0*/
TEST_FPIO_OP_NRM(fcvt.d.w, f19, x1, 0, 0, x12, 1*4, x18, x7, x15,lw)
inst_2:// rs1==x19, rd==f28,rs1_val == 2 and fcsr == 0 and rm_val == 7
/* opcode: fcvt.d.w ; op1:x19; dest:f28; op1val:0x2; valaddr_reg:x12;
val_offset:2*4; correctval:??; testreg:x15;
fcsr_val: 0*/
TEST_FPIO_OP_NRM(fcvt.d.w, f28, x19, 0, 0, x12, 2*4, x18, x7, x15,lw)
inst_3:// rs1==x2, rd==f23,rs1_val == 7 and fcsr == 0 and rm_val == 7
/* opcode: fcvt.d.w ; op1:x2; dest:f23; op1val:0x7; valaddr_reg:x12;
val_offset:3*4; correctval:??; testreg:x15;
fcsr_val: 0*/
TEST_FPIO_OP_NRM(fcvt.d.w, f23, x2, 0, 0, x12, 3*4, x18, x7, x15,lw)
inst_4:// rs1==x27, rd==f3,rs1_val == 15 and fcsr == 0 and rm_val == 7
/* opcode: fcvt.d.w ; op1:x27; dest:f3; op1val:0xf; valaddr_reg:x12;
val_offset:4*4; correctval:??; testreg:x15;
fcsr_val: 0*/
TEST_FPIO_OP_NRM(fcvt.d.w, f3, x27, 0, 0, x12, 4*4, x18, x7, x15,lw)
inst_5:// rs1==x20, rd==f9,rs1_val == 16 and fcsr == 0 and rm_val == 7
/* opcode: fcvt.d.w ; op1:x20; dest:f9; op1val:0x10; valaddr_reg:x12;
val_offset:5*4; correctval:??; testreg:x15;
fcsr_val: 0*/
TEST_FPIO_OP_NRM(fcvt.d.w, f9, x20, 0, 0, x12, 5*4, x18, x7, x15,lw)
inst_6:// rs1==x6, rd==f30,rs1_val == 45 and fcsr == 0 and rm_val == 7
/* opcode: fcvt.d.w ; op1:x6; dest:f30; op1val:0x2d; valaddr_reg:x12;
val_offset:6*4; correctval:??; testreg:x15;
fcsr_val: 0*/
TEST_FPIO_OP_NRM(fcvt.d.w, f30, x6, 0, 0, x12, 6*4, x18, x7, x15,lw)
inst_7:// rs1==x10, rd==f0,rs1_val == 123 and fcsr == 0 and rm_val == 7
/* opcode: fcvt.d.w ; op1:x10; dest:f0; op1val:0x7b; valaddr_reg:x12;
val_offset:7*4; correctval:??; testreg:x15;
fcsr_val: 0*/
TEST_FPIO_OP_NRM(fcvt.d.w, f0, x10, 0, 0, x12, 7*4, x18, x7, x15,lw)
inst_8:// rs1==x24, rd==f14,rs1_val == 253 and fcsr == 0 and rm_val == 7
/* opcode: fcvt.d.w ; op1:x24; dest:f14; op1val:0xfd; valaddr_reg:x12;
val_offset:8*4; correctval:??; testreg:x15;
fcsr_val: 0*/
TEST_FPIO_OP_NRM(fcvt.d.w, f14, x24, 0, 0, x12, 8*4, x18, x7, x15,lw)
inst_9:// rs1==x22, rd==f21,rs1_val == 398 and fcsr == 0 and rm_val == 7
/* opcode: fcvt.d.w ; op1:x22; dest:f21; op1val:0x18e; valaddr_reg:x12;
val_offset:9*4; correctval:??; testreg:x15;
fcsr_val: 0*/
TEST_FPIO_OP_NRM(fcvt.d.w, f21, x22, 0, 0, x12, 9*4, x18, x7, x15,lw)
inst_10:// rs1==x17, rd==f8,rs1_val == 676 and fcsr == 0 and rm_val == 7
/* opcode: fcvt.d.w ; op1:x17; dest:f8; op1val:0x2a4; valaddr_reg:x12;
val_offset:10*4; correctval:??; testreg:x15;
fcsr_val: 0*/
TEST_FPIO_OP_NRM(fcvt.d.w, f8, x17, 0, 0, x12, 10*4, x18, x7, x15,lw)
inst_11:// rs1==x14, rd==f31,rs1_val == 1094 and fcsr == 0 and rm_val == 7
/* opcode: fcvt.d.w ; op1:x14; dest:f31; op1val:0x446; valaddr_reg:x12;
val_offset:11*4; correctval:??; testreg:x15;
fcsr_val: 0*/
TEST_FPIO_OP_NRM(fcvt.d.w, f31, x14, 0, 0, x12, 11*4, x18, x7, x15,lw)
inst_12:// rs1==x25, rd==f27,rs1_val == 4055 and fcsr == 0 and rm_val == 7
/* opcode: fcvt.d.w ; op1:x25; dest:f27; op1val:0xfd7; valaddr_reg:x12;
val_offset:12*4; correctval:??; testreg:x15;
fcsr_val: 0*/
TEST_FPIO_OP_NRM(fcvt.d.w, f27, x25, 0, 0, x12, 12*4, x18, x7, x15,lw)
inst_13:// rs1==x8, rd==f22,rs1_val == 6781 and fcsr == 0 and rm_val == 7
/* opcode: fcvt.d.w ; op1:x8; dest:f22; op1val:0x1a7d; valaddr_reg:x12;
val_offset:13*4; correctval:??; testreg:x15;
fcsr_val: 0*/
TEST_FPIO_OP_NRM(fcvt.d.w, f22, x8, 0, 0, x12, 13*4, x18, x7, x15,lw)
inst_14:// rs1==x0, rd==f15,rs1_val == 9438 and fcsr == 0 and rm_val == 7
/* opcode: fcvt.d.w ; op1:x0; dest:f15; op1val:0x0; valaddr_reg:x12;
val_offset:14*4; correctval:??; testreg:x15;
fcsr_val: 0*/
TEST_FPIO_OP_NRM(fcvt.d.w, f15, x0, 0, 0, x12, 14*4, x18, x7, x15,lw)
inst_15:// rs1==x21, rd==f10,rs1_val == 24575 and fcsr == 0 and rm_val == 7
/* opcode: fcvt.d.w ; op1:x21; dest:f10; op1val:0x5fff; valaddr_reg:x12;
val_offset:15*4; correctval:??; testreg:x15;
fcsr_val: 0*/
TEST_FPIO_OP_NRM(fcvt.d.w, f10, x21, 0, 0, x12, 15*4, x18, x7, x15,lw)
inst_16:// rs1==x5, rd==f26,rs1_val == 56436 and fcsr == 0 and rm_val == 7
/* opcode: fcvt.d.w ; op1:x5; dest:f26; op1val:0xdc74; valaddr_reg:x12;
val_offset:16*4; correctval:??; testreg:x15;
fcsr_val: 0*/
TEST_FPIO_OP_NRM(fcvt.d.w, f26, x5, 0, 0, x12, 16*4, x18, x7, x15,lw)
inst_17:// rs1==x23, rd==f29,rs1_val == 71376 and fcsr == 0 and rm_val == 7
/* opcode: fcvt.d.w ; op1:x23; dest:f29; op1val:0x116d0; valaddr_reg:x12;
val_offset:17*4; correctval:??; testreg:x15;
fcsr_val: 0*/
TEST_FPIO_OP_NRM(fcvt.d.w, f29, x23, 0, 0, x12, 17*4, x18, x7, x15,lw)
inst_18:// rs1==x11, rd==f18,rs1_val == 241276 and fcsr == 0 and rm_val == 7
/* opcode: fcvt.d.w ; op1:x11; dest:f18; op1val:0x3ae7c; valaddr_reg:x12;
val_offset:18*4; correctval:??; testreg:x15;
fcsr_val: 0*/
TEST_FPIO_OP_NRM(fcvt.d.w, f18, x11, 0, 0, x12, 18*4, x18, x7, x15,lw)
inst_19:// rs1==x29, rd==f1,rs1_val == 334857 and fcsr == 0 and rm_val == 7
/* opcode: fcvt.d.w ; op1:x29; dest:f1; op1val:0x51c09; valaddr_reg:x12;
val_offset:19*4; correctval:??; testreg:x15;
fcsr_val: 0*/
TEST_FPIO_OP_NRM(fcvt.d.w, f1, x29, 0, 0, x12, 19*4, x18, x7, x15,lw)
inst_20:// rs1==x3, rd==f16,rs1_val == 896618 and fcsr == 0 and rm_val == 7
/* opcode: fcvt.d.w ; op1:x3; dest:f16; op1val:0xdae6a; valaddr_reg:x12;
val_offset:20*4; correctval:??; testreg:x15;
fcsr_val: 0*/
TEST_FPIO_OP_NRM(fcvt.d.w, f16, x3, 0, 0, x12, 20*4, x18, x7, x15,lw)
inst_21:// rs1==x4, rd==f6,rs1_val == 1848861 and fcsr == 0 and rm_val == 7
/* opcode: fcvt.d.w ; op1:x4; dest:f6; op1val:0x1c361d; valaddr_reg:x12;
val_offset:21*4; correctval:??; testreg:x15;
fcsr_val: 0*/
TEST_FPIO_OP_NRM(fcvt.d.w, f6, x4, 0, 0, x12, 21*4, x18, x7, x15,lw)
inst_22:// rs1==x13, rd==f25,rs1_val == 3864061 and fcsr == 0 and rm_val == 7
/* opcode: fcvt.d.w ; op1:x13; dest:f25; op1val:0x3af5fd; valaddr_reg:x12;
val_offset:22*4; correctval:??; testreg:x15;
fcsr_val: 0*/
TEST_FPIO_OP_NRM(fcvt.d.w, f25, x13, 0, 0, x12, 22*4, x18, x7, x15,lw)
inst_23:// rs1==x9, rd==f4,rs1_val == 6573466 and fcsr == 0 and rm_val == 7
/* opcode: fcvt.d.w ; op1:x9; dest:f4; op1val:0x644d9a; valaddr_reg:x12;
val_offset:23*4; correctval:??; testreg:x15;
fcsr_val: 0*/
TEST_FPIO_OP_NRM(fcvt.d.w, f4, x9, 0, 0, x12, 23*4, x18, x7, x15,lw)
inst_24:// rs1==x16, rd==f7,rs1_val == 12789625 and fcsr == 0 and rm_val == 7
/* opcode: fcvt.d.w ; op1:x16; dest:f7; op1val:0xc32779; valaddr_reg:x12;
val_offset:24*4; correctval:??; testreg:x15;
fcsr_val: 0*/
TEST_FPIO_OP_NRM(fcvt.d.w, f7, x16, 0, 0, x12, 24*4, x18, x7, x15,lw)
RVTEST_VALBASEUPD(x3,test_dataset_1)
inst_25:// rs1==x30, rd==f24,rs1_val == 32105925 and fcsr == 0 and rm_val == 7
/* opcode: fcvt.d.w ; op1:x30; dest:f24; op1val:0x1e9e5c5; valaddr_reg:x3;
val_offset:0*4; correctval:??; testreg:x15;
fcsr_val: 0*/
TEST_FPIO_OP_NRM(fcvt.d.w, f24, x30, 0, 0, x3, 0*4, x4, x7, x15,lw)
inst_26:// rs1==x12, rd==f13,rs1_val == 45276376 and fcsr == 0 and rm_val == 7
/* opcode: fcvt.d.w ; op1:x12; dest:f13; op1val:0x2b2dcd8; valaddr_reg:x3;
val_offset:1*4; correctval:??; testreg:x15;
fcsr_val: 0*/
TEST_FPIO_OP_NRM(fcvt.d.w, f13, x12, 0, 0, x3, 1*4, x4, x7, x15,lw)
inst_27:// rs1==x31, rd==f20,rs1_val == 107790943 and fcsr == 0 and rm_val == 7
/* opcode: fcvt.d.w ; op1:x31; dest:f20; op1val:0x66cc25f; valaddr_reg:x3;
val_offset:2*4; correctval:??; testreg:x2;
fcsr_val: 0*/
TEST_FPIO_OP_NRM(fcvt.d.w, f20, x31, 0, 0, x3, 2*4, x4, x7, x2,lw)
RVTEST_SIGBASE(x1,signature_x1_0)
inst_28:// rs1==x26, rd==f12,rs1_val == 231549045 and fcsr == 0 and rm_val == 7
/* opcode: fcvt.d.w ; op1:x26; dest:f12; op1val:0xdcd2875; valaddr_reg:x3;
val_offset:3*4; correctval:??; testreg:x2;
fcsr_val: 0*/
TEST_FPIO_OP_NRM(fcvt.d.w, f12, x26, 0, 0, x3, 3*4, x4, x1, x2,lw)
inst_29:// rs1==x15, rd==f17,rs1_val == 339827553 and fcsr == 0 and rm_val == 7
/* opcode: fcvt.d.w ; op1:x15; dest:f17; op1val:0x14415b61; valaddr_reg:x3;
val_offset:4*4; correctval:??; testreg:x2;
fcsr_val: 0*/
TEST_FPIO_OP_NRM(fcvt.d.w, f17, x15, 0, 0, x3, 4*4, x4, x1, x2,lw)
inst_30:// rs1==x18, rd==f11,rs1_val == 1027494066 and fcsr == 0 and rm_val == 7
/* opcode: fcvt.d.w ; op1:x18; dest:f11; op1val:0x3d3e50b2; valaddr_reg:x3;
val_offset:5*4; correctval:??; testreg:x2;
fcsr_val: 0*/
TEST_FPIO_OP_NRM(fcvt.d.w, f11, x18, 0, 0, x3, 5*4, x4, x1, x2,lw)
inst_31:// rs1==x7, rd==f2,rs1_val == 1587807073 and fcsr == 0 and rm_val == 7
/* opcode: fcvt.d.w ; op1:x7; dest:f2; op1val:0x5ea40361; valaddr_reg:x3;
val_offset:6*4; correctval:??; testreg:x2;
fcsr_val: 0*/
TEST_FPIO_OP_NRM(fcvt.d.w, f2, x7, 0, 0, x3, 6*4, x4, x1, x2,lw)
inst_32:// rs1_val == 9438 and fcsr == 0 and rm_val == 7
/* opcode: fcvt.d.w ; op1:x31; dest:f31; op1val:0x24de; valaddr_reg:x3;
val_offset:7*4; correctval:??; testreg:x2;
fcsr_val: 0*/
TEST_FPIO_OP_NRM(fcvt.d.w, f31, x31, 0, 0, x3, 7*4, x4, x1, x2,lw)
#endif
RVTEST_CODE_END
RVMODEL_HALT
RVTEST_DATA_BEGIN
.align 4
rvtest_data:
.word 0xbabecafe
.word 0xabecafeb
.word 0xbecafeba
.word 0xecafebab
test_dataset_0:
.word 0;
.word 1;
.word 2;
.word 7;
.word 15;
.word 16;
.word 45;
.word 123;
.word 253;
.word 398;
.word 676;
.word 1094;
.word 4055;
.word 6781;
.word 0;
.word 24575;
.word 56436;
.word 71376;
.word 241276;
.word 334857;
.word 896618;
.word 1848861;
.word 3864061;
.word 6573466;
.word 12789625;
test_dataset_1:
.word 32105925;
.word 45276376;
.word 107790943;
.word 231549045;
.word 339827553;
.word 1027494066;
.word 1587807073;
.word 9438;
RVTEST_DATA_END
RVMODEL_DATA_BEGIN
rvtest_sig_begin:
sig_begin_canary:
CANARY;
signature_x7_0:
.fill 0*((SIGALIGN)/4),4,0xdeadbeef
signature_x7_1:
.fill 56*((SIGALIGN)/4),4,0xdeadbeef
signature_x1_0:
.fill 10*((SIGALIGN)/4),4,0xdeadbeef
#ifdef rvtest_mtrap_routine
tsig_begin_canary:
CANARY;
tsig_begin_canary:
CANARY;
mtrap_sigptr:
.fill 64*(XLEN/32),4,0xdeadbeef
tsig_end_canary:
CANARY;
tsig_end_canary:
CANARY;
#endif
#ifdef rvtest_gpr_save
gpr_save:
.fill 32*XLEN/32,4,0xdeadbeef
#endif
sig_end_canary:
CANARY;
rvtest_sig_end:
RVMODEL_DATA_END

330
vendor/riscv-arch-tests/riscv-test-suite/rv32i_m/D/src/fcvt.d.wu_b25-01.S vendored
View file

@ -1,330 +0,0 @@
// -----------
// This file was generated by riscv_ctg (https://github.com/riscv-software-src/riscv-ctg)
// version : 0.7.1
// timestamp : Fri Jun 17 14:03:39 2022 GMT
// usage : riscv_ctg \
// -- cgf // --cgf /scratch/pawan/work/normalised/RV32D/fcvt.d.wu.cgf \
\
// -- xlen 32 \
// --randomize \
// -----------
//
// -----------
// Copyright (c) 2020. RISC-V International. All rights reserved.
// SPDX-License-Identifier: BSD-3-Clause
// -----------
//
// This assembly file tests the fcvt.d.wu instruction of the RISC-V RV32FD_Zicsr,RV64FD_Zicsr extension for the fcvt.d.wu_b25 covergroup.
//
#include "model_test.h"
#include "arch_test.h"
RVTEST_ISA("RV32IFD_Zicsr,RV64IFD_Zicsr")
.section .text.init
.org 0x80
.globl rvtest_entry_point
rvtest_entry_point:
RVMODEL_BOOT
RVTEST_CODE_BEGIN
#ifdef TEST_CASE_1
RVTEST_CASE(0,"//check ISA:=regex(.*I.*D.*);def TEST_CASE_1=True;",fcvt.d.wu_b25)
RVTEST_FP_ENABLE()
RVTEST_VALBASEUPD(x11,test_dataset_0)
RVTEST_SIGBASE(x5,signature_x5_1)
inst_0:// rs1==x8, rd==f28,rs1_val == 0 and fcsr == 0 and rm_val == 7
/* opcode: fcvt.d.wu ; op1:x8; dest:f28; op1val:0x0; valaddr_reg:x11;
val_offset:0*4; correctval:??; testreg:x10;
fcsr_val: 0*/
TEST_FPIO_OP_NRM(fcvt.d.wu, f28, x8, 0, 0, x11, 0*4, x16, x5, x10,LREGWU)
inst_1:// rs1==x28, rd==f18,rs1_val == 1 and fcsr == 0 and rm_val == 7
/* opcode: fcvt.d.wu ; op1:x28; dest:f18; op1val:0x1; valaddr_reg:x11;
val_offset:1*4; correctval:??; testreg:x10;
fcsr_val: 0*/
TEST_FPIO_OP_NRM(fcvt.d.wu, f18, x28, 0, 0, x11, 1*4, x16, x5, x10,LREGWU)
inst_2:// rs1==x30, rd==f3,rs1_val == 2454155456 and fcsr == 0 and rm_val == 7
/* opcode: fcvt.d.wu ; op1:x30; dest:f3; op1val:0x924770c0; valaddr_reg:x11;
val_offset:2*4; correctval:??; testreg:x10;
fcsr_val: 0*/
TEST_FPIO_OP_NRM(fcvt.d.wu, f3, x30, 0, 0, x11, 2*4, x16, x5, x10,LREGWU)
inst_3:// rs1==x27, rd==f23,rs1_val == 4294967295 and fcsr == 0 and rm_val == 7
/* opcode: fcvt.d.wu ; op1:x27; dest:f23; op1val:0xffffffff; valaddr_reg:x11;
val_offset:3*4; correctval:??; testreg:x10;
fcsr_val: 0*/
TEST_FPIO_OP_NRM(fcvt.d.wu, f23, x27, 0, 0, x11, 3*4, x16, x5, x10,LREGWU)
inst_4:// rs1==x4, rd==f22,
/* opcode: fcvt.d.wu ; op1:x4; dest:f22; op1val:0x0; valaddr_reg:x11;
val_offset:4*4; correctval:??; testreg:x10;
fcsr_val: 0*/
TEST_FPIO_OP_NRM(fcvt.d.wu, f22, x4, 0, 0, x11, 4*4, x16, x5, x10,LREGWU)
inst_5:// rs1==x15, rd==f12,
/* opcode: fcvt.d.wu ; op1:x15; dest:f12; op1val:0x0; valaddr_reg:x11;
val_offset:5*4; correctval:??; testreg:x10;
fcsr_val: 0*/
TEST_FPIO_OP_NRM(fcvt.d.wu, f12, x15, 0, 0, x11, 5*4, x16, x5, x10,LREGWU)
inst_6:// rs1==x23, rd==f19,
/* opcode: fcvt.d.wu ; op1:x23; dest:f19; op1val:0x0; valaddr_reg:x11;
val_offset:6*4; correctval:??; testreg:x10;
fcsr_val: 0*/
TEST_FPIO_OP_NRM(fcvt.d.wu, f19, x23, 0, 0, x11, 6*4, x16, x5, x10,LREGWU)
inst_7:// rs1==x3, rd==f2,
/* opcode: fcvt.d.wu ; op1:x3; dest:f2; op1val:0x0; valaddr_reg:x11;
val_offset:7*4; correctval:??; testreg:x10;
fcsr_val: 0*/
TEST_FPIO_OP_NRM(fcvt.d.wu, f2, x3, 0, 0, x11, 7*4, x16, x5, x10,LREGWU)
inst_8:// rs1==x6, rd==f26,
/* opcode: fcvt.d.wu ; op1:x6; dest:f26; op1val:0x0; valaddr_reg:x11;
val_offset:8*4; correctval:??; testreg:x10;
fcsr_val: 0*/
TEST_FPIO_OP_NRM(fcvt.d.wu, f26, x6, 0, 0, x11, 8*4, x16, x5, x10,LREGWU)
inst_9:// rs1==x1, rd==f15,
/* opcode: fcvt.d.wu ; op1:x1; dest:f15; op1val:0x0; valaddr_reg:x11;
val_offset:9*4; correctval:??; testreg:x10;
fcsr_val: 0*/
TEST_FPIO_OP_NRM(fcvt.d.wu, f15, x1, 0, 0, x11, 9*4, x16, x5, x10,LREGWU)
inst_10:// rs1==x13, rd==f10,
/* opcode: fcvt.d.wu ; op1:x13; dest:f10; op1val:0x0; valaddr_reg:x11;
val_offset:10*4; correctval:??; testreg:x10;
fcsr_val: 0*/
TEST_FPIO_OP_NRM(fcvt.d.wu, f10, x13, 0, 0, x11, 10*4, x16, x5, x10,LREGWU)
inst_11:// rs1==x20, rd==f14,
/* opcode: fcvt.d.wu ; op1:x20; dest:f14; op1val:0x0; valaddr_reg:x11;
val_offset:11*4; correctval:??; testreg:x10;
fcsr_val: 0*/
TEST_FPIO_OP_NRM(fcvt.d.wu, f14, x20, 0, 0, x11, 11*4, x16, x5, x10,LREGWU)
inst_12:// rs1==x21, rd==f20,
/* opcode: fcvt.d.wu ; op1:x21; dest:f20; op1val:0x0; valaddr_reg:x11;
val_offset:12*4; correctval:??; testreg:x10;
fcsr_val: 0*/
TEST_FPIO_OP_NRM(fcvt.d.wu, f20, x21, 0, 0, x11, 12*4, x16, x5, x10,LREGWU)
inst_13:// rs1==x22, rd==f30,
/* opcode: fcvt.d.wu ; op1:x22; dest:f30; op1val:0x0; valaddr_reg:x11;
val_offset:13*4; correctval:??; testreg:x10;
fcsr_val: 0*/
TEST_FPIO_OP_NRM(fcvt.d.wu, f30, x22, 0, 0, x11, 13*4, x16, x5, x10,LREGWU)
inst_14:// rs1==x14, rd==f9,
/* opcode: fcvt.d.wu ; op1:x14; dest:f9; op1val:0x0; valaddr_reg:x11;
val_offset:14*4; correctval:??; testreg:x10;
fcsr_val: 0*/
TEST_FPIO_OP_NRM(fcvt.d.wu, f9, x14, 0, 0, x11, 14*4, x16, x5, x10,LREGWU)
inst_15:// rs1==x12, rd==f0,
/* opcode: fcvt.d.wu ; op1:x12; dest:f0; op1val:0x0; valaddr_reg:x11;
val_offset:15*4; correctval:??; testreg:x10;
fcsr_val: 0*/
TEST_FPIO_OP_NRM(fcvt.d.wu, f0, x12, 0, 0, x11, 15*4, x16, x5, x10,LREGWU)
inst_16:// rs1==x2, rd==f29,
/* opcode: fcvt.d.wu ; op1:x2; dest:f29; op1val:0x0; valaddr_reg:x11;
val_offset:16*4; correctval:??; testreg:x10;
fcsr_val: 0*/
TEST_FPIO_OP_NRM(fcvt.d.wu, f29, x2, 0, 0, x11, 16*4, x16, x5, x10,LREGWU)
inst_17:// rs1==x26, rd==f6,
/* opcode: fcvt.d.wu ; op1:x26; dest:f6; op1val:0x0; valaddr_reg:x11;
val_offset:17*4; correctval:??; testreg:x10;
fcsr_val: 0*/
TEST_FPIO_OP_NRM(fcvt.d.wu, f6, x26, 0, 0, x11, 17*4, x16, x5, x10,LREGWU)
inst_18:// rs1==x19, rd==f24,
/* opcode: fcvt.d.wu ; op1:x19; dest:f24; op1val:0x0; valaddr_reg:x11;
val_offset:18*4; correctval:??; testreg:x10;
fcsr_val: 0*/
TEST_FPIO_OP_NRM(fcvt.d.wu, f24, x19, 0, 0, x11, 18*4, x16, x5, x10,LREGWU)
inst_19:// rs1==x17, rd==f25,
/* opcode: fcvt.d.wu ; op1:x17; dest:f25; op1val:0x0; valaddr_reg:x11;
val_offset:19*4; correctval:??; testreg:x10;
fcsr_val: 0*/
TEST_FPIO_OP_NRM(fcvt.d.wu, f25, x17, 0, 0, x11, 19*4, x16, x5, x10,LREGWU)
inst_20:// rs1==x29, rd==f17,
/* opcode: fcvt.d.wu ; op1:x29; dest:f17; op1val:0x0; valaddr_reg:x11;
val_offset:20*4; correctval:??; testreg:x10;
fcsr_val: 0*/
TEST_FPIO_OP_NRM(fcvt.d.wu, f17, x29, 0, 0, x11, 20*4, x16, x5, x10,LREGWU)
inst_21:// rs1==x18, rd==f5,
/* opcode: fcvt.d.wu ; op1:x18; dest:f5; op1val:0x0; valaddr_reg:x11;
val_offset:21*4; correctval:??; testreg:x10;
fcsr_val: 0*/
TEST_FPIO_OP_NRM(fcvt.d.wu, f5, x18, 0, 0, x11, 21*4, x16, x5, x10,LREGWU)
inst_22:// rs1==x9, rd==f16,
/* opcode: fcvt.d.wu ; op1:x9; dest:f16; op1val:0x0; valaddr_reg:x11;
val_offset:22*4; correctval:??; testreg:x10;
fcsr_val: 0*/
TEST_FPIO_OP_NRM(fcvt.d.wu, f16, x9, 0, 0, x11, 22*4, x16, x5, x10,LREGWU)
inst_23:// rs1==x7, rd==f7,
/* opcode: fcvt.d.wu ; op1:x7; dest:f7; op1val:0x0; valaddr_reg:x11;
val_offset:23*4; correctval:??; testreg:x10;
fcsr_val: 0*/
TEST_FPIO_OP_NRM(fcvt.d.wu, f7, x7, 0, 0, x11, 23*4, x16, x5, x10,LREGWU)
RVTEST_VALBASEUPD(x3,test_dataset_1)
inst_24:// rs1==x31, rd==f1,
/* opcode: fcvt.d.wu ; op1:x31; dest:f1; op1val:0x0; valaddr_reg:x3;
val_offset:0*4; correctval:??; testreg:x10;
fcsr_val: 0*/
TEST_FPIO_OP_NRM(fcvt.d.wu, f1, x31, 0, 0, x3, 0*4, x4, x5, x10,LREGWU)
inst_25:// rs1==x11, rd==f21,
/* opcode: fcvt.d.wu ; op1:x11; dest:f21; op1val:0x0; valaddr_reg:x3;
val_offset:1*4; correctval:??; testreg:x10;
fcsr_val: 0*/
TEST_FPIO_OP_NRM(fcvt.d.wu, f21, x11, 0, 0, x3, 1*4, x4, x5, x10,LREGWU)
inst_26:// rs1==x16, rd==f31,
/* opcode: fcvt.d.wu ; op1:x16; dest:f31; op1val:0x0; valaddr_reg:x3;
val_offset:2*4; correctval:??; testreg:x2;
fcsr_val: 0*/
TEST_FPIO_OP_NRM(fcvt.d.wu, f31, x16, 0, 0, x3, 2*4, x4, x5, x2,LREGWU)
RVTEST_SIGBASE(x1,signature_x1_0)
inst_27:// rs1==x25, rd==f13,
/* opcode: fcvt.d.wu ; op1:x25; dest:f13; op1val:0x0; valaddr_reg:x3;
val_offset:3*4; correctval:??; testreg:x2;
fcsr_val: 0*/
TEST_FPIO_OP_NRM(fcvt.d.wu, f13, x25, 0, 0, x3, 3*4, x4, x1, x2,LREGWU)
inst_28:// rs1==x0, rd==f11,
/* opcode: fcvt.d.wu ; op1:x0; dest:f11; op1val:0x0; valaddr_reg:x3;
val_offset:4*4; correctval:??; testreg:x2;
fcsr_val: 0*/
TEST_FPIO_OP_NRM(fcvt.d.wu, f11, x0, 0, 0, x3, 4*4, x4, x1, x2,LREGWU)
inst_29:// rs1==x5, rd==f4,
/* opcode: fcvt.d.wu ; op1:x5; dest:f4; op1val:0x0; valaddr_reg:x3;
val_offset:5*4; correctval:??; testreg:x2;
fcsr_val: 0*/
TEST_FPIO_OP_NRM(fcvt.d.wu, f4, x5, 0, 0, x3, 5*4, x4, x1, x2,LREGWU)
inst_30:// rs1==x10, rd==f8,
/* opcode: fcvt.d.wu ; op1:x10; dest:f8; op1val:0x0; valaddr_reg:x3;
val_offset:6*4; correctval:??; testreg:x2;
fcsr_val: 0*/
TEST_FPIO_OP_NRM(fcvt.d.wu, f8, x10, 0, 0, x3, 6*4, x4, x1, x2,LREGWU)
inst_31:// rs1==x24, rd==f27,
/* opcode: fcvt.d.wu ; op1:x24; dest:f27; op1val:0x0; valaddr_reg:x3;
val_offset:7*4; correctval:??; testreg:x2;
fcsr_val: 0*/
TEST_FPIO_OP_NRM(fcvt.d.wu, f27, x24, 0, 0, x3, 7*4, x4, x1, x2,LREGWU)
inst_32://
/* opcode: fcvt.d.wu ; op1:x31; dest:f31; op1val:0x0; valaddr_reg:x3;
val_offset:8*4; correctval:??; testreg:x2;
fcsr_val: 0*/
TEST_FPIO_OP_NRM(fcvt.d.wu, f31, x31, 0, 0, x3, 8*4, x4, x1, x2,LREGWU)
#endif
RVTEST_CODE_END
RVMODEL_HALT
RVTEST_DATA_BEGIN
.align 4
rvtest_data:
.word 0xbabecafe
.word 0xabecafeb
.word 0xbecafeba
.word 0xecafebab
test_dataset_0:
.word 0;
.word 1;
.word 2454155456;
.word 4294967295;
.word 0;
.word 0;
.word 0;
.word 0;
.word 0;
.word 0;
.word 0;
.word 0;
.word 0;
.word 0;
.word 0;
.word 0;
.word 0;
.word 0;
.word 0;
.word 0;
.word 0;
.word 0;
.word 0;
.word 0;
test_dataset_1:
.word 0;
.word 0;
.word 0;
.word 0;
.word 0;
.word 0;
.word 0;
.word 0;
.word 0;
RVTEST_DATA_END
RVMODEL_DATA_BEGIN
rvtest_sig_begin:
sig_begin_canary:
CANARY;
signature_x5_0:
.fill 0*((SIGALIGN)/4),4,0xdeadbeef
signature_x5_1:
.fill 54*((SIGALIGN)/4),4,0xdeadbeef
signature_x1_0:
.fill 12*((SIGALIGN)/4),4,0xdeadbeef
#ifdef rvtest_mtrap_routine
tsig_begin_canary:
CANARY;
tsig_begin_canary:
CANARY;
mtrap_sigptr:
.fill 64*(XLEN/32),4,0xdeadbeef
tsig_end_canary:
CANARY;
tsig_end_canary:
CANARY;
#endif
#ifdef rvtest_gpr_save
gpr_save:
.fill 32*XLEN/32,4,0xdeadbeef
#endif
sig_end_canary:
CANARY;
rvtest_sig_end:
RVMODEL_DATA_END

330
vendor/riscv-arch-tests/riscv-test-suite/rv32i_m/D/src/fcvt.d.wu_b26-01.S vendored
View file

@ -1,330 +0,0 @@
// -----------
// This file was generated by riscv_ctg (https://github.com/riscv-software-src/riscv-ctg)
// version : 0.7.1
// timestamp : Fri Jun 17 14:03:39 2022 GMT
// usage : riscv_ctg \
// -- cgf // --cgf /scratch/pawan/work/normalised/RV32D/fcvt.d.wu.cgf \
\
// -- xlen 32 \
// --randomize \
// -----------
//
// -----------
// Copyright (c) 2020. RISC-V International. All rights reserved.
// SPDX-License-Identifier: BSD-3-Clause
// -----------
//
// This assembly file tests the fcvt.d.wu instruction of the RISC-V RV32FD_Zicsr,RV64FD_Zicsr extension for the fcvt.d.wu_b26 covergroup.
//
#include "model_test.h"
#include "arch_test.h"
RVTEST_ISA("RV32IFD_Zicsr,RV64IFD_Zicsr")
.section .text.init
.org 0x80
.globl rvtest_entry_point
rvtest_entry_point:
RVMODEL_BOOT
RVTEST_CODE_BEGIN
#ifdef TEST_CASE_1
RVTEST_CASE(0,"//check ISA:=regex(.*I.*D.*);def TEST_CASE_1=True;",fcvt.d.wu_b26)
RVTEST_FP_ENABLE()
RVTEST_VALBASEUPD(x13,test_dataset_0)
RVTEST_SIGBASE(x10,signature_x10_1)
inst_0:// rs1==x22, rd==f2,rs1_val == 0 and fcsr == 0 and rm_val == 7
/* opcode: fcvt.d.wu ; op1:x22; dest:f2; op1val:0x0; valaddr_reg:x13;
val_offset:0*4; correctval:??; testreg:x3;
fcsr_val: 0*/
TEST_FPIO_OP_NRM(fcvt.d.wu, f2, x22, 0, 0, x13, 0*4, x15, x10, x3,LREGWU)
inst_1:// rs1==x2, rd==f14,rs1_val == 1 and fcsr == 0 and rm_val == 7
/* opcode: fcvt.d.wu ; op1:x2; dest:f14; op1val:0x1; valaddr_reg:x13;
val_offset:1*4; correctval:??; testreg:x3;
fcsr_val: 0*/
TEST_FPIO_OP_NRM(fcvt.d.wu, f14, x2, 0, 0, x13, 1*4, x15, x10, x3,LREGWU)
inst_2:// rs1==x7, rd==f11,rs1_val == 1027494066 and fcsr == 0 and rm_val == 7
/* opcode: fcvt.d.wu ; op1:x7; dest:f11; op1val:0x3d3e50b2; valaddr_reg:x13;
val_offset:2*4; correctval:??; testreg:x3;
fcsr_val: 0*/
TEST_FPIO_OP_NRM(fcvt.d.wu, f11, x7, 0, 0, x13, 2*4, x15, x10, x3,LREGWU)
inst_3:// rs1==x16, rd==f5,rs1_val == 107790943 and fcsr == 0 and rm_val == 7
/* opcode: fcvt.d.wu ; op1:x16; dest:f5; op1val:0x66cc25f; valaddr_reg:x13;
val_offset:3*4; correctval:??; testreg:x3;
fcsr_val: 0*/
TEST_FPIO_OP_NRM(fcvt.d.wu, f5, x16, 0, 0, x13, 3*4, x15, x10, x3,LREGWU)
inst_4:// rs1==x28, rd==f7,rs1_val == 1094 and fcsr == 0 and rm_val == 7
/* opcode: fcvt.d.wu ; op1:x28; dest:f7; op1val:0x446; valaddr_reg:x13;
val_offset:4*4; correctval:??; testreg:x3;
fcsr_val: 0*/
TEST_FPIO_OP_NRM(fcvt.d.wu, f7, x28, 0, 0, x13, 4*4, x15, x10, x3,LREGWU)
inst_5:// rs1==x6, rd==f20,rs1_val == 123 and fcsr == 0 and rm_val == 7
/* opcode: fcvt.d.wu ; op1:x6; dest:f20; op1val:0x7b; valaddr_reg:x13;
val_offset:5*4; correctval:??; testreg:x3;
fcsr_val: 0*/
TEST_FPIO_OP_NRM(fcvt.d.wu, f20, x6, 0, 0, x13, 5*4, x15, x10, x3,LREGWU)
inst_6:// rs1==x11, rd==f15,rs1_val == 12789625 and fcsr == 0 and rm_val == 7
/* opcode: fcvt.d.wu ; op1:x11; dest:f15; op1val:0xc32779; valaddr_reg:x13;
val_offset:6*4; correctval:??; testreg:x3;
fcsr_val: 0*/
TEST_FPIO_OP_NRM(fcvt.d.wu, f15, x11, 0, 0, x13, 6*4, x15, x10, x3,LREGWU)
inst_7:// rs1==x30, rd==f10,rs1_val == 15 and fcsr == 0 and rm_val == 7
/* opcode: fcvt.d.wu ; op1:x30; dest:f10; op1val:0xf; valaddr_reg:x13;
val_offset:7*4; correctval:??; testreg:x3;
fcsr_val: 0*/
TEST_FPIO_OP_NRM(fcvt.d.wu, f10, x30, 0, 0, x13, 7*4, x15, x10, x3,LREGWU)
inst_8:// rs1==x27, rd==f3,rs1_val == 1587807073 and fcsr == 0 and rm_val == 7
/* opcode: fcvt.d.wu ; op1:x27; dest:f3; op1val:0x5ea40361; valaddr_reg:x13;
val_offset:8*4; correctval:??; testreg:x3;
fcsr_val: 0*/
TEST_FPIO_OP_NRM(fcvt.d.wu, f3, x27, 0, 0, x13, 8*4, x15, x10, x3,LREGWU)
inst_9:// rs1==x14, rd==f13,rs1_val == 16 and fcsr == 0 and rm_val == 7
/* opcode: fcvt.d.wu ; op1:x14; dest:f13; op1val:0x10; valaddr_reg:x13;
val_offset:9*4; correctval:??; testreg:x3;
fcsr_val: 0*/
TEST_FPIO_OP_NRM(fcvt.d.wu, f13, x14, 0, 0, x13, 9*4, x15, x10, x3,LREGWU)
inst_10:// rs1==x26, rd==f21,rs1_val == 1848861 and fcsr == 0 and rm_val == 7
/* opcode: fcvt.d.wu ; op1:x26; dest:f21; op1val:0x1c361d; valaddr_reg:x13;
val_offset:10*4; correctval:??; testreg:x3;
fcsr_val: 0*/
TEST_FPIO_OP_NRM(fcvt.d.wu, f21, x26, 0, 0, x13, 10*4, x15, x10, x3,LREGWU)
inst_11:// rs1==x17, rd==f26,rs1_val == 2 and fcsr == 0 and rm_val == 7
/* opcode: fcvt.d.wu ; op1:x17; dest:f26; op1val:0x2; valaddr_reg:x13;
val_offset:11*4; correctval:??; testreg:x3;
fcsr_val: 0*/
TEST_FPIO_OP_NRM(fcvt.d.wu, f26, x17, 0, 0, x13, 11*4, x15, x10, x3,LREGWU)
inst_12:// rs1==x5, rd==f4,rs1_val == 231549045 and fcsr == 0 and rm_val == 7
/* opcode: fcvt.d.wu ; op1:x5; dest:f4; op1val:0xdcd2875; valaddr_reg:x13;
val_offset:12*4; correctval:??; testreg:x3;
fcsr_val: 0*/
TEST_FPIO_OP_NRM(fcvt.d.wu, f4, x5, 0, 0, x13, 12*4, x15, x10, x3,LREGWU)
inst_13:// rs1==x12, rd==f22,rs1_val == 241276 and fcsr == 0 and rm_val == 7
/* opcode: fcvt.d.wu ; op1:x12; dest:f22; op1val:0x3ae7c; valaddr_reg:x13;
val_offset:13*4; correctval:??; testreg:x3;
fcsr_val: 0*/
TEST_FPIO_OP_NRM(fcvt.d.wu, f22, x12, 0, 0, x13, 13*4, x15, x10, x3,LREGWU)
inst_14:// rs1==x18, rd==f19,rs1_val == 24575 and fcsr == 0 and rm_val == 7
/* opcode: fcvt.d.wu ; op1:x18; dest:f19; op1val:0x5fff; valaddr_reg:x13;
val_offset:14*4; correctval:??; testreg:x3;
fcsr_val: 0*/
TEST_FPIO_OP_NRM(fcvt.d.wu, f19, x18, 0, 0, x13, 14*4, x15, x10, x3,LREGWU)
inst_15:// rs1==x4, rd==f0,rs1_val == 253 and fcsr == 0 and rm_val == 7
/* opcode: fcvt.d.wu ; op1:x4; dest:f0; op1val:0xfd; valaddr_reg:x13;
val_offset:15*4; correctval:??; testreg:x3;
fcsr_val: 0*/
TEST_FPIO_OP_NRM(fcvt.d.wu, f0, x4, 0, 0, x13, 15*4, x15, x10, x3,LREGWU)
inst_16:// rs1==x0, rd==f31,rs1_val == 32105925 and fcsr == 0 and rm_val == 7
/* opcode: fcvt.d.wu ; op1:x0; dest:f31; op1val:0x0; valaddr_reg:x13;
val_offset:16*4; correctval:??; testreg:x3;
fcsr_val: 0*/
TEST_FPIO_OP_NRM(fcvt.d.wu, f31, x0, 0, 0, x13, 16*4, x15, x10, x3,LREGWU)
inst_17:// rs1==x20, rd==f8,rs1_val == 334857 and fcsr == 0 and rm_val == 7
/* opcode: fcvt.d.wu ; op1:x20; dest:f8; op1val:0x51c09; valaddr_reg:x13;
val_offset:17*4; correctval:??; testreg:x3;
fcsr_val: 0*/
TEST_FPIO_OP_NRM(fcvt.d.wu, f8, x20, 0, 0, x13, 17*4, x15, x10, x3,LREGWU)
inst_18:// rs1==x24, rd==f24,rs1_val == 339827553 and fcsr == 0 and rm_val == 7
/* opcode: fcvt.d.wu ; op1:x24; dest:f24; op1val:0x14415b61; valaddr_reg:x13;
val_offset:18*4; correctval:??; testreg:x3;
fcsr_val: 0*/
TEST_FPIO_OP_NRM(fcvt.d.wu, f24, x24, 0, 0, x13, 18*4, x15, x10, x3,LREGWU)
inst_19:// rs1==x9, rd==f29,rs1_val == 3864061 and fcsr == 0 and rm_val == 7
/* opcode: fcvt.d.wu ; op1:x9; dest:f29; op1val:0x3af5fd; valaddr_reg:x13;
val_offset:19*4; correctval:??; testreg:x3;
fcsr_val: 0*/
TEST_FPIO_OP_NRM(fcvt.d.wu, f29, x9, 0, 0, x13, 19*4, x15, x10, x3,LREGWU)
inst_20:// rs1==x8, rd==f28,rs1_val == 398 and fcsr == 0 and rm_val == 7
/* opcode: fcvt.d.wu ; op1:x8; dest:f28; op1val:0x18e; valaddr_reg:x13;
val_offset:20*4; correctval:??; testreg:x3;
fcsr_val: 0*/
TEST_FPIO_OP_NRM(fcvt.d.wu, f28, x8, 0, 0, x13, 20*4, x15, x10, x3,LREGWU)
inst_21:// rs1==x29, rd==f25,rs1_val == 4055 and fcsr == 0 and rm_val == 7
/* opcode: fcvt.d.wu ; op1:x29; dest:f25; op1val:0xfd7; valaddr_reg:x13;
val_offset:21*4; correctval:??; testreg:x3;
fcsr_val: 0*/
TEST_FPIO_OP_NRM(fcvt.d.wu, f25, x29, 0, 0, x13, 21*4, x15, x10, x3,LREGWU)
inst_22:// rs1==x1, rd==f16,rs1_val == 45 and fcsr == 0 and rm_val == 7
/* opcode: fcvt.d.wu ; op1:x1; dest:f16; op1val:0x2d; valaddr_reg:x13;
val_offset:22*4; correctval:??; testreg:x3;
fcsr_val: 0*/
TEST_FPIO_OP_NRM(fcvt.d.wu, f16, x1, 0, 0, x13, 22*4, x15, x10, x3,LREGWU)
inst_23:// rs1==x23, rd==f18,rs1_val == 45276376 and fcsr == 0 and rm_val == 7
/* opcode: fcvt.d.wu ; op1:x23; dest:f18; op1val:0x2b2dcd8; valaddr_reg:x13;
val_offset:23*4; correctval:??; testreg:x3;
fcsr_val: 0*/
TEST_FPIO_OP_NRM(fcvt.d.wu, f18, x23, 0, 0, x13, 23*4, x15, x10, x3,LREGWU)
inst_24:// rs1==x21, rd==f1,rs1_val == 56436 and fcsr == 0 and rm_val == 7
/* opcode: fcvt.d.wu ; op1:x21; dest:f1; op1val:0xdc74; valaddr_reg:x13;
val_offset:24*4; correctval:??; testreg:x3;
fcsr_val: 0*/
TEST_FPIO_OP_NRM(fcvt.d.wu, f1, x21, 0, 0, x13, 24*4, x15, x10, x3,LREGWU)
RVTEST_VALBASEUPD(x4,test_dataset_1)
inst_25:// rs1==x25, rd==f23,rs1_val == 6573466 and fcsr == 0 and rm_val == 7
/* opcode: fcvt.d.wu ; op1:x25; dest:f23; op1val:0x644d9a; valaddr_reg:x4;
val_offset:0*4; correctval:??; testreg:x3;
fcsr_val: 0*/
TEST_FPIO_OP_NRM(fcvt.d.wu, f23, x25, 0, 0, x4, 0*4, x5, x10, x3,LREGWU)
inst_26:// rs1==x15, rd==f30,rs1_val == 676 and fcsr == 0 and rm_val == 7
/* opcode: fcvt.d.wu ; op1:x15; dest:f30; op1val:0x2a4; valaddr_reg:x4;
val_offset:1*4; correctval:??; testreg:x3;
fcsr_val: 0*/
TEST_FPIO_OP_NRM(fcvt.d.wu, f30, x15, 0, 0, x4, 1*4, x5, x10, x3,LREGWU)
inst_27:// rs1==x3, rd==f9,rs1_val == 6781 and fcsr == 0 and rm_val == 7
/* opcode: fcvt.d.wu ; op1:x3; dest:f9; op1val:0x1a7d; valaddr_reg:x4;
val_offset:2*4; correctval:??; testreg:x2;
fcsr_val: 0*/
TEST_FPIO_OP_NRM(fcvt.d.wu, f9, x3, 0, 0, x4, 2*4, x5, x10, x2,LREGWU)
RVTEST_SIGBASE(x1,signature_x1_0)
inst_28:// rs1==x19, rd==f12,rs1_val == 7 and fcsr == 0 and rm_val == 7
/* opcode: fcvt.d.wu ; op1:x19; dest:f12; op1val:0x7; valaddr_reg:x4;
val_offset:3*4; correctval:??; testreg:x2;
fcsr_val: 0*/
TEST_FPIO_OP_NRM(fcvt.d.wu, f12, x19, 0, 0, x4, 3*4, x5, x1, x2,LREGWU)
inst_29:// rs1==x31, rd==f27,rs1_val == 71376 and fcsr == 0 and rm_val == 7
/* opcode: fcvt.d.wu ; op1:x31; dest:f27; op1val:0x116d0; valaddr_reg:x4;
val_offset:4*4; correctval:??; testreg:x2;
fcsr_val: 0*/
TEST_FPIO_OP_NRM(fcvt.d.wu, f27, x31, 0, 0, x4, 4*4, x5, x1, x2,LREGWU)
inst_30:// rs1==x10, rd==f6,rs1_val == 896618 and fcsr == 0 and rm_val == 7
/* opcode: fcvt.d.wu ; op1:x10; dest:f6; op1val:0xdae6a; valaddr_reg:x4;
val_offset:5*4; correctval:??; testreg:x2;
fcsr_val: 0*/
TEST_FPIO_OP_NRM(fcvt.d.wu, f6, x10, 0, 0, x4, 5*4, x5, x1, x2,LREGWU)
inst_31:// rs1==x13, rd==f17,rs1_val == 9438 and fcsr == 0 and rm_val == 7
/* opcode: fcvt.d.wu ; op1:x13; dest:f17; op1val:0x24de; valaddr_reg:x4;
val_offset:6*4; correctval:??; testreg:x2;
fcsr_val: 0*/
TEST_FPIO_OP_NRM(fcvt.d.wu, f17, x13, 0, 0, x4, 6*4, x5, x1, x2,LREGWU)
inst_32:// rs1_val == 32105925 and fcsr == 0 and rm_val == 7
/* opcode: fcvt.d.wu ; op1:x31; dest:f31; op1val:0x1e9e5c5; valaddr_reg:x4;
val_offset:7*4; correctval:??; testreg:x2;
fcsr_val: 0*/
TEST_FPIO_OP_NRM(fcvt.d.wu, f31, x31, 0, 0, x4, 7*4, x5, x1, x2,LREGWU)
#endif
RVTEST_CODE_END
RVMODEL_HALT
RVTEST_DATA_BEGIN
.align 4
rvtest_data:
.word 0xbabecafe
.word 0xabecafeb
.word 0xbecafeba
.word 0xecafebab
test_dataset_0:
.word 0;
.word 1;
.word 1027494066;
.word 107790943;
.word 1094;
.word 123;
.word 12789625;
.word 15;
.word 1587807073;
.word 16;
.word 1848861;
.word 2;
.word 231549045;
.word 241276;
.word 24575;
.word 253;
.word 0;
.word 334857;
.word 339827553;
.word 3864061;
.word 398;
.word 4055;
.word 45;
.word 45276376;
.word 56436;
test_dataset_1:
.word 6573466;
.word 676;
.word 6781;
.word 7;
.word 71376;
.word 896618;
.word 9438;
.word 32105925;
RVTEST_DATA_END
RVMODEL_DATA_BEGIN
rvtest_sig_begin:
sig_begin_canary:
CANARY;
signature_x10_0:
.fill 0*((SIGALIGN)/4),4,0xdeadbeef
signature_x10_1:
.fill 56*((SIGALIGN)/4),4,0xdeadbeef
signature_x1_0:
.fill 10*((SIGALIGN)/4),4,0xdeadbeef
#ifdef rvtest_mtrap_routine
tsig_begin_canary:
CANARY;
tsig_begin_canary:
CANARY;
mtrap_sigptr:
.fill 64*(XLEN/32),4,0xdeadbeef
tsig_end_canary:
CANARY;
tsig_end_canary:
CANARY;
#endif
#ifdef rvtest_gpr_save
gpr_save:
.fill 32*XLEN/32,4,0xdeadbeef
#endif
sig_end_canary:
CANARY;
rvtest_sig_end:
RVMODEL_DATA_END

356
vendor/riscv-arch-tests/riscv-test-suite/rv32i_m/D/src/fcvt.s.d_b1-01.S vendored
View file

@ -1,356 +0,0 @@
// -----------
// This file was generated by riscv_ctg (https://github.com/riscv-software-src/riscv-ctg)
// version : 0.7.1
// timestamp : Fri Jun 17 14:03:33 2022 GMT
// usage : riscv_ctg \
// -- cgf // --cgf /scratch/pawan/work/normalised/RV32D/fcvt.s.d.cgf \
\
// -- xlen 32 \
// --randomize \
// -----------
//
// -----------
// Copyright (c) 2020. RISC-V International. All rights reserved.
// SPDX-License-Identifier: BSD-3-Clause
// -----------
//
// This assembly file tests the fcvt.s.d instruction of the RISC-V RV32FD_Zicsr,RV64FD_Zicsr extension for the fcvt.s.d_b1 covergroup.
//
#include "model_test.h"
#include "arch_test.h"
RVTEST_ISA("RV32IFD_Zicsr,RV64IFD_Zicsr")
.section .text.init
.org 0x80
.globl rvtest_entry_point
rvtest_entry_point:
RVMODEL_BOOT
RVTEST_CODE_BEGIN
#ifdef TEST_CASE_1
RVTEST_CASE(0,"//check ISA:=regex(.*I.*D.*);def TEST_CASE_1=True;",fcvt.s.d_b1)
RVTEST_FP_ENABLE()
RVTEST_VALBASEUPD(x3,test_dataset_0)
RVTEST_SIGBASE(x1,signature_x1_1)
inst_0:
// rs1 != rd, rs1==f7, rd==f8,fs1 == 0 and fe1 == 0x000 and fm1 == 0x0000000000000 and fcsr == 0x0 and rm_val == 7
/* opcode: fcvt.s.d ; op1:f7; dest:f8; op1val:0x0; valaddr_reg:x3;
val_offset:0*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
fcsr_val: 0 */
TEST_FPSR_OP(fcvt.s.d, f8, f7, dyn, 0, 0, x3, 0*FLEN/8, x4, x1, x2)
inst_1:
// rs1 == rd, rs1==f17, rd==f17,fs1 == 0 and fe1 == 0x000 and fm1 == 0x0000000000001 and fcsr == 0x0 and rm_val == 7
/* opcode: fcvt.s.d ; op1:f17; dest:f17; op1val:0x1; valaddr_reg:x3;
val_offset:1*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
fcsr_val: 0 */
TEST_FPSR_OP(fcvt.s.d, f17, f17, dyn, 0, 0, x3, 1*FLEN/8, x4, x1, x2)
inst_2:
// rs1==f16, rd==f9,fs1 == 0 and fe1 == 0x000 and fm1 == 0x0000000000002 and fcsr == 0x0 and rm_val == 7
/* opcode: fcvt.s.d ; op1:f16; dest:f9; op1val:0x2; valaddr_reg:x3;
val_offset:2*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
fcsr_val: 0 */
TEST_FPSR_OP(fcvt.s.d, f9, f16, dyn, 0, 0, x3, 2*FLEN/8, x4, x1, x2)
inst_3:
// rs1==f28, rd==f27,fs1 == 0 and fe1 == 0x000 and fm1 == 0xfffffffffffff and fcsr == 0x0 and rm_val == 7
/* opcode: fcvt.s.d ; op1:f28; dest:f27; op1val:0xfffffffffffff; valaddr_reg:x3;
val_offset:3*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
fcsr_val: 0 */
TEST_FPSR_OP(fcvt.s.d, f27, f28, dyn, 0, 0, x3, 3*FLEN/8, x4, x1, x2)
inst_4:
// rs1==f3, rd==f20,fs1 == 0 and fe1 == 0x001 and fm1 == 0x0000000000000 and fcsr == 0x0 and rm_val == 7
/* opcode: fcvt.s.d ; op1:f3; dest:f20; op1val:0x10000000000000; valaddr_reg:x3;
val_offset:4*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
fcsr_val: 0 */
TEST_FPSR_OP(fcvt.s.d, f20, f3, dyn, 0, 0, x3, 4*FLEN/8, x4, x1, x2)
inst_5:
// rs1==f11, rd==f23,fs1 == 0 and fe1 == 0x001 and fm1 == 0x0000000000002 and fcsr == 0x0 and rm_val == 7
/* opcode: fcvt.s.d ; op1:f11; dest:f23; op1val:0x10000000000002; valaddr_reg:x3;
val_offset:5*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
fcsr_val: 0 */
TEST_FPSR_OP(fcvt.s.d, f23, f11, dyn, 0, 0, x3, 5*FLEN/8, x4, x1, x2)
inst_6:
// rs1==f20, rd==f18,fs1 == 0 and fe1 == 0x3ff and fm1 == 0x0000000000000 and fcsr == 0x0 and rm_val == 7
/* opcode: fcvt.s.d ; op1:f20; dest:f18; op1val:0x3ff0000000000000; valaddr_reg:x3;
val_offset:6*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
fcsr_val: 0 */
TEST_FPSR_OP(fcvt.s.d, f18, f20, dyn, 0, 0, x3, 6*FLEN/8, x4, x1, x2)
inst_7:
// rs1==f1, rd==f5,fs1 == 0 and fe1 == 0x7fe and fm1 == 0xfffffffffffff and fcsr == 0x0 and rm_val == 7
/* opcode: fcvt.s.d ; op1:f1; dest:f5; op1val:0x7fefffffffffffff; valaddr_reg:x3;
val_offset:7*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
fcsr_val: 0 */
TEST_FPSR_OP(fcvt.s.d, f5, f1, dyn, 0, 0, x3, 7*FLEN/8, x4, x1, x2)
inst_8:
// rs1==f30, rd==f12,fs1 == 0 and fe1 == 0x7ff and fm1 == 0x0000000000000 and fcsr == 0x0 and rm_val == 7
/* opcode: fcvt.s.d ; op1:f30; dest:f12; op1val:0x7ff0000000000000; valaddr_reg:x3;
val_offset:8*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
fcsr_val: 0 */
TEST_FPSR_OP(fcvt.s.d, f12, f30, dyn, 0, 0, x3, 8*FLEN/8, x4, x1, x2)
inst_9:
// rs1==f29, rd==f4,fs1 == 0 and fe1 == 0x7ff and fm1 == 0x0000000000001 and fcsr == 0x0 and rm_val == 7
/* opcode: fcvt.s.d ; op1:f29; dest:f4; op1val:0x7ff0000000000001; valaddr_reg:x3;
val_offset:9*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
fcsr_val: 0 */
TEST_FPSR_OP(fcvt.s.d, f4, f29, dyn, 0, 0, x3, 9*FLEN/8, x4, x1, x2)
inst_10:
// rs1==f18, rd==f22,fs1 == 0 and fe1 == 0x7ff and fm1 == 0x8000000000000 and fcsr == 0x0 and rm_val == 7
/* opcode: fcvt.s.d ; op1:f18; dest:f22; op1val:0x7ff8000000000000; valaddr_reg:x3;
val_offset:10*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
fcsr_val: 0 */
TEST_FPSR_OP(fcvt.s.d, f22, f18, dyn, 0, 0, x3, 10*FLEN/8, x4, x1, x2)
inst_11:
// rs1==f0, rd==f28,fs1 == 0 and fe1 == 0x7ff and fm1 == 0x8000000000001 and fcsr == 0x0 and rm_val == 7
/* opcode: fcvt.s.d ; op1:f0; dest:f28; op1val:0x7ff8000000000001; valaddr_reg:x3;
val_offset:11*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
fcsr_val: 0 */
TEST_FPSR_OP(fcvt.s.d, f28, f0, dyn, 0, 0, x3, 11*FLEN/8, x4, x1, x2)
inst_12:
// rs1==f27, rd==f1,fs1 == 1 and fe1 == 0x000 and fm1 == 0x0000000000000 and fcsr == 0x0 and rm_val == 7
/* opcode: fcvt.s.d ; op1:f27; dest:f1; op1val:0x8000000000000000; valaddr_reg:x3;
val_offset:12*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
fcsr_val: 0 */
TEST_FPSR_OP(fcvt.s.d, f1, f27, dyn, 0, 0, x3, 12*FLEN/8, x4, x1, x2)
inst_13:
// rs1==f21, rd==f24,fs1 == 1 and fe1 == 0x000 and fm1 == 0x0000000000001 and fcsr == 0x0 and rm_val == 7
/* opcode: fcvt.s.d ; op1:f21; dest:f24; op1val:0x8000000000000001; valaddr_reg:x3;
val_offset:13*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
fcsr_val: 0 */
TEST_FPSR_OP(fcvt.s.d, f24, f21, dyn, 0, 0, x3, 13*FLEN/8, x4, x1, x2)
inst_14:
// rs1==f8, rd==f19,fs1 == 1 and fe1 == 0x000 and fm1 == 0x0000000000002 and fcsr == 0x0 and rm_val == 7
/* opcode: fcvt.s.d ; op1:f8; dest:f19; op1val:0x8000000000000002; valaddr_reg:x3;
val_offset:14*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
fcsr_val: 0 */
TEST_FPSR_OP(fcvt.s.d, f19, f8, dyn, 0, 0, x3, 14*FLEN/8, x4, x1, x2)
inst_15:
// rs1==f4, rd==f30,fs1 == 1 and fe1 == 0x000 and fm1 == 0xfffffffffffff and fcsr == 0x0 and rm_val == 7
/* opcode: fcvt.s.d ; op1:f4; dest:f30; op1val:0x800fffffffffffff; valaddr_reg:x3;
val_offset:15*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
fcsr_val: 0 */
TEST_FPSR_OP(fcvt.s.d, f30, f4, dyn, 0, 0, x3, 15*FLEN/8, x4, x1, x2)
inst_16:
// rs1==f25, rd==f13,fs1 == 1 and fe1 == 0x001 and fm1 == 0x0000000000000 and fcsr == 0x0 and rm_val == 7
/* opcode: fcvt.s.d ; op1:f25; dest:f13; op1val:0x8010000000000000; valaddr_reg:x3;
val_offset:16*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
fcsr_val: 0 */
TEST_FPSR_OP(fcvt.s.d, f13, f25, dyn, 0, 0, x3, 16*FLEN/8, x4, x1, x2)
inst_17:
// rs1==f9, rd==f6,fs1 == 1 and fe1 == 0x001 and fm1 == 0x0000000000002 and fcsr == 0x0 and rm_val == 7
/* opcode: fcvt.s.d ; op1:f9; dest:f6; op1val:0x8010000000000002; valaddr_reg:x3;
val_offset:17*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
fcsr_val: 0 */
TEST_FPSR_OP(fcvt.s.d, f6, f9, dyn, 0, 0, x3, 17*FLEN/8, x4, x1, x2)
inst_18:
// rs1==f2, rd==f14,fs1 == 1 and fe1 == 0x3f8 and fm1 == 0x0000000000000 and fcsr == 0x0 and rm_val == 7
/* opcode: fcvt.s.d ; op1:f2; dest:f14; op1val:0xbf80000000000000; valaddr_reg:x3;
val_offset:18*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
fcsr_val: 0 */
TEST_FPSR_OP(fcvt.s.d, f14, f2, dyn, 0, 0, x3, 18*FLEN/8, x4, x1, x2)
inst_19:
// rs1==f10, rd==f16,fs1 == 1 and fe1 == 0x7fe and fm1 == 0xfffffffffffff and fcsr == 0x0 and rm_val == 7
/* opcode: fcvt.s.d ; op1:f10; dest:f16; op1val:0xffefffffffffffff; valaddr_reg:x3;
val_offset:19*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
fcsr_val: 0 */
TEST_FPSR_OP(fcvt.s.d, f16, f10, dyn, 0, 0, x3, 19*FLEN/8, x4, x1, x2)
inst_20:
// rs1==f15, rd==f11,fs1 == 1 and fe1 == 0x7ff and fm1 == 0x0000000000000 and fcsr == 0x0 and rm_val == 7
/* opcode: fcvt.s.d ; op1:f15; dest:f11; op1val:0xfff0000000000000; valaddr_reg:x3;
val_offset:20*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
fcsr_val: 0 */
TEST_FPSR_OP(fcvt.s.d, f11, f15, dyn, 0, 0, x3, 20*FLEN/8, x4, x1, x2)
inst_21:
// rs1==f13, rd==f25,fs1 == 1 and fe1 == 0x7ff and fm1 == 0x0000000000001 and fcsr == 0x0 and rm_val == 7
/* opcode: fcvt.s.d ; op1:f13; dest:f25; op1val:0xfff0000000000001; valaddr_reg:x3;
val_offset:21*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
fcsr_val: 0 */
TEST_FPSR_OP(fcvt.s.d, f25, f13, dyn, 0, 0, x3, 21*FLEN/8, x4, x1, x2)
inst_22:
// rs1==f19, rd==f2,fs1 == 1 and fe1 == 0x7ff and fm1 == 0x8000000000000 and fcsr == 0x0 and rm_val == 7
/* opcode: fcvt.s.d ; op1:f19; dest:f2; op1val:0xfff8000000000000; valaddr_reg:x3;
val_offset:22*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
fcsr_val: 0 */
TEST_FPSR_OP(fcvt.s.d, f2, f19, dyn, 0, 0, x3, 22*FLEN/8, x4, x1, x2)
inst_23:
// rs1==f23, rd==f0,fs1 == 1 and fe1 == 0x7ff and fm1 == 0x8000000000001 and fcsr == 0x0 and rm_val == 7
/* opcode: fcvt.s.d ; op1:f23; dest:f0; op1val:0xfff8000000000001; valaddr_reg:x3;
val_offset:23*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
fcsr_val: 0 */
TEST_FPSR_OP(fcvt.s.d, f0, f23, dyn, 0, 0, x3, 23*FLEN/8, x4, x1, x2)
inst_24:
// rs1==f5, rd==f15,
/* opcode: fcvt.s.d ; op1:f5; dest:f15; op1val:0x0; valaddr_reg:x3;
val_offset:24*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
fcsr_val: 0 */
TEST_FPSR_OP(fcvt.s.d, f15, f5, dyn, 0, 0, x3, 24*FLEN/8, x4, x1, x2)
inst_25:
// rs1==f22, rd==f21,
/* opcode: fcvt.s.d ; op1:f22; dest:f21; op1val:0x0; valaddr_reg:x3;
val_offset:25*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
fcsr_val: 0 */
TEST_FPSR_OP(fcvt.s.d, f21, f22, dyn, 0, 0, x3, 25*FLEN/8, x4, x1, x2)
inst_26:
// rs1==f14, rd==f7,
/* opcode: fcvt.s.d ; op1:f14; dest:f7; op1val:0x0; valaddr_reg:x3;
val_offset:26*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
fcsr_val: 0 */
TEST_FPSR_OP(fcvt.s.d, f7, f14, dyn, 0, 0, x3, 26*FLEN/8, x4, x1, x2)
inst_27:
// rs1==f6, rd==f31,
/* opcode: fcvt.s.d ; op1:f6; dest:f31; op1val:0x0; valaddr_reg:x3;
val_offset:27*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
fcsr_val: 0 */
TEST_FPSR_OP(fcvt.s.d, f31, f6, dyn, 0, 0, x3, 27*FLEN/8, x4, x1, x2)
inst_28:
// rs1==f31, rd==f3,
/* opcode: fcvt.s.d ; op1:f31; dest:f3; op1val:0x0; valaddr_reg:x3;
val_offset:28*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
fcsr_val: 0 */
TEST_FPSR_OP(fcvt.s.d, f3, f31, dyn, 0, 0, x3, 28*FLEN/8, x4, x1, x2)
inst_29:
// rs1==f26, rd==f10,
/* opcode: fcvt.s.d ; op1:f26; dest:f10; op1val:0x0; valaddr_reg:x3;
val_offset:29*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
fcsr_val: 0 */
TEST_FPSR_OP(fcvt.s.d, f10, f26, dyn, 0, 0, x3, 29*FLEN/8, x4, x1, x2)
inst_30:
// rs1==f24, rd==f26,
/* opcode: fcvt.s.d ; op1:f24; dest:f26; op1val:0x0; valaddr_reg:x3;
val_offset:30*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
fcsr_val: 0 */
TEST_FPSR_OP(fcvt.s.d, f26, f24, dyn, 0, 0, x3, 30*FLEN/8, x4, x1, x2)
inst_31:
// rs1==f12, rd==f29,
/* opcode: fcvt.s.d ; op1:f12; dest:f29; op1val:0x0; valaddr_reg:x3;
val_offset:31*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
fcsr_val: 0 */
TEST_FPSR_OP(fcvt.s.d, f29, f12, dyn, 0, 0, x3, 31*FLEN/8, x4, x1, x2)
inst_32:
// fs1 == 0 and fe1 == 0x000 and fm1 == 0x0000000000001 and fcsr == 0x0 and rm_val == 7
/* opcode: fcvt.s.d ; op1:f30; dest:f31; op1val:0x1; valaddr_reg:x3;
val_offset:32*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
fcsr_val: 0 */
TEST_FPSR_OP(fcvt.s.d, f31, f30, dyn, 0, 0, x3, 32*FLEN/8, x4, x1, x2)
#endif
RVTEST_CODE_END
RVMODEL_HALT
RVTEST_DATA_BEGIN
.align 4
rvtest_data:
.word 0xbabecafe
.word 0xabecafeb
.word 0xbecafeba
.word 0xecafebab
test_dataset_0:
NAN_BOXED(0,64,FLEN)
NAN_BOXED(1,64,FLEN)
NAN_BOXED(2,64,FLEN)
NAN_BOXED(4503599627370495,64,FLEN)
NAN_BOXED(4503599627370496,64,FLEN)
NAN_BOXED(4503599627370498,64,FLEN)
NAN_BOXED(4607182418800017408,64,FLEN)
NAN_BOXED(9218868437227405311,64,FLEN)
NAN_BOXED(9218868437227405312,64,FLEN)
NAN_BOXED(9218868437227405313,64,FLEN)
NAN_BOXED(9221120237041090560,64,FLEN)
NAN_BOXED(9221120237041090561,64,FLEN)
NAN_BOXED(9223372036854775808,64,FLEN)
NAN_BOXED(9223372036854775809,64,FLEN)
NAN_BOXED(9223372036854775810,64,FLEN)
NAN_BOXED(9227875636482146303,64,FLEN)
NAN_BOXED(9227875636482146304,64,FLEN)
NAN_BOXED(9227875636482146306,64,FLEN)
NAN_BOXED(13799029258263199744,64,FLEN)
NAN_BOXED(18442240474082181119,64,FLEN)
NAN_BOXED(18442240474082181120,64,FLEN)
NAN_BOXED(18442240474082181121,64,FLEN)
NAN_BOXED(18444492273895866368,64,FLEN)
NAN_BOXED(18444492273895866369,64,FLEN)
NAN_BOXED(0,64,FLEN)
NAN_BOXED(0,64,FLEN)
NAN_BOXED(0,64,FLEN)
NAN_BOXED(0,64,FLEN)
NAN_BOXED(0,64,FLEN)
NAN_BOXED(0,64,FLEN)
NAN_BOXED(0,64,FLEN)
NAN_BOXED(0,64,FLEN)
NAN_BOXED(1,64,FLEN)
RVTEST_DATA_END
RVMODEL_DATA_BEGIN
rvtest_sig_begin:
sig_begin_canary:
CANARY;
signature_x1_0:
.fill 0*((SIGALIGN)/4),4,0xdeadbeef
signature_x1_1:
.fill 66*((SIGALIGN)/4),4,0xdeadbeef
#ifdef rvtest_mtrap_routine
tsig_begin_canary:
CANARY;
tsig_begin_canary:
CANARY;
mtrap_sigptr:
.fill 64*(XLEN/32),4,0xdeadbeef
tsig_end_canary:
CANARY;
tsig_end_canary:
CANARY;
#endif
#ifdef rvtest_gpr_save
gpr_save:
.fill 32*XLEN/32,4,0xdeadbeef
#endif
sig_end_canary:
CANARY;
rvtest_sig_end:
RVMODEL_DATA_END

356
vendor/riscv-arch-tests/riscv-test-suite/rv32i_m/D/src/fcvt.s.d_b22-01.S vendored
View file

@ -1,356 +0,0 @@
// -----------
// This file was generated by riscv_ctg (https://github.com/riscv-software-src/riscv-ctg)
// version : 0.7.1
// timestamp : Fri Jun 17 14:03:33 2022 GMT
// usage : riscv_ctg \
// -- cgf // --cgf /scratch/pawan/work/normalised/RV32D/fcvt.s.d.cgf \
\
// -- xlen 32 \
// --randomize \
// -----------
//
// -----------
// Copyright (c) 2020. RISC-V International. All rights reserved.
// SPDX-License-Identifier: BSD-3-Clause
// -----------
//
// This assembly file tests the fcvt.s.d instruction of the RISC-V RV32FD_Zicsr,RV64FD_Zicsr extension for the fcvt.s.d_b22 covergroup.
//
#include "model_test.h"
#include "arch_test.h"
RVTEST_ISA("RV32IFD_Zicsr,RV64IFD_Zicsr")
.section .text.init
.org 0x80
.globl rvtest_entry_point
rvtest_entry_point:
RVMODEL_BOOT
RVTEST_CODE_BEGIN
#ifdef TEST_CASE_1
RVTEST_CASE(0,"//check ISA:=regex(.*I.*D.*);def TEST_CASE_1=True;",fcvt.s.d_b22)
RVTEST_FP_ENABLE()
RVTEST_VALBASEUPD(x3,test_dataset_0)
RVTEST_SIGBASE(x1,signature_x1_1)
inst_0:
// rs1 != rd, rs1==f6, rd==f22,fs1 == 0 and fe1 == 0x3fc and fm1 == 0x08577924770d3 and fcsr == 0x0 and rm_val == 7
/* opcode: fcvt.s.d ; op1:f6; dest:f22; op1val:0x3fc08577924770d3; valaddr_reg:x3;
val_offset:0*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
fcsr_val: 0 */
TEST_FPSR_OP(fcvt.s.d, f22, f6, dyn, 0, 0, x3, 0*FLEN/8, x4, x1, x2)
inst_1:
// rs1 == rd, rs1==f3, rd==f3,fs1 == 0 and fe1 == 0x3fd and fm1 == 0x93fdc7b89296c and fcsr == 0x0 and rm_val == 7
/* opcode: fcvt.s.d ; op1:f3; dest:f3; op1val:0x3fd93fdc7b89296c; valaddr_reg:x3;
val_offset:1*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
fcsr_val: 0 */
TEST_FPSR_OP(fcvt.s.d, f3, f3, dyn, 0, 0, x3, 1*FLEN/8, x4, x1, x2)
inst_2:
// rs1==f1, rd==f30,fs1 == 0 and fe1 == 0x3ff and fm1 == 0xd2d6b7dc59a3a and fcsr == 0x0 and rm_val == 7
/* opcode: fcvt.s.d ; op1:f1; dest:f30; op1val:0x3ffd2d6b7dc59a3a; valaddr_reg:x3;
val_offset:2*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
fcsr_val: 0 */
TEST_FPSR_OP(fcvt.s.d, f30, f1, dyn, 0, 0, x3, 2*FLEN/8, x4, x1, x2)
inst_3:
// rs1==f20, rd==f21,fs1 == 0 and fe1 == 0x400 and fm1 == 0xcf84ba749f9c5 and fcsr == 0x0 and rm_val == 7
/* opcode: fcvt.s.d ; op1:f20; dest:f21; op1val:0x400cf84ba749f9c5; valaddr_reg:x3;
val_offset:3*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
fcsr_val: 0 */
TEST_FPSR_OP(fcvt.s.d, f21, f20, dyn, 0, 0, x3, 3*FLEN/8, x4, x1, x2)
inst_4:
// rs1==f16, rd==f8,fs1 == 0 and fe1 == 0x401 and fm1 == 0x854a908ceac39 and fcsr == 0x0 and rm_val == 7
/* opcode: fcvt.s.d ; op1:f16; dest:f8; op1val:0x401854a908ceac39; valaddr_reg:x3;
val_offset:4*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
fcsr_val: 0 */
TEST_FPSR_OP(fcvt.s.d, f8, f16, dyn, 0, 0, x3, 4*FLEN/8, x4, x1, x2)
inst_5:
// rs1==f8, rd==f18,fs1 == 0 and fe1 == 0x7fe and fm1 == 0xbedc2f3ebcf12 and fcsr == 0x0 and rm_val == 7
/* opcode: fcvt.s.d ; op1:f8; dest:f18; op1val:0x7febedc2f3ebcf12; valaddr_reg:x3;
val_offset:5*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
fcsr_val: 0 */
TEST_FPSR_OP(fcvt.s.d, f18, f8, dyn, 0, 0, x3, 5*FLEN/8, x4, x1, x2)
inst_6:
// rs1==f11, rd==f0,fs1 == 1 and fe1 == 0x0ff and fm1 == 0x137a953e8eb43 and fcsr == 0x0 and rm_val == 7
/* opcode: fcvt.s.d ; op1:f11; dest:f0; op1val:0x8ff137a953e8eb43; valaddr_reg:x3;
val_offset:6*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
fcsr_val: 0 */
TEST_FPSR_OP(fcvt.s.d, f0, f11, dyn, 0, 0, x3, 6*FLEN/8, x4, x1, x2)
inst_7:
// rs1==f2, rd==f19,fs1 == 1 and fe1 == 0x3fe and fm1 == 0x766ba34c2da80 and fcsr == 0x0 and rm_val == 7
/* opcode: fcvt.s.d ; op1:f2; dest:f19; op1val:0xbfe766ba34c2da80; valaddr_reg:x3;
val_offset:7*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
fcsr_val: 0 */
TEST_FPSR_OP(fcvt.s.d, f19, f2, dyn, 0, 0, x3, 7*FLEN/8, x4, x1, x2)
inst_8:
// rs1==f23, rd==f5,
/* opcode: fcvt.s.d ; op1:f23; dest:f5; op1val:0x0; valaddr_reg:x3;
val_offset:8*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
fcsr_val: 0 */
TEST_FPSR_OP(fcvt.s.d, f5, f23, dyn, 0, 0, x3, 8*FLEN/8, x4, x1, x2)
inst_9:
// rs1==f19, rd==f28,
/* opcode: fcvt.s.d ; op1:f19; dest:f28; op1val:0x0; valaddr_reg:x3;
val_offset:9*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
fcsr_val: 0 */
TEST_FPSR_OP(fcvt.s.d, f28, f19, dyn, 0, 0, x3, 9*FLEN/8, x4, x1, x2)
inst_10:
// rs1==f28, rd==f27,
/* opcode: fcvt.s.d ; op1:f28; dest:f27; op1val:0x0; valaddr_reg:x3;
val_offset:10*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
fcsr_val: 0 */
TEST_FPSR_OP(fcvt.s.d, f27, f28, dyn, 0, 0, x3, 10*FLEN/8, x4, x1, x2)
inst_11:
// rs1==f15, rd==f25,
/* opcode: fcvt.s.d ; op1:f15; dest:f25; op1val:0x0; valaddr_reg:x3;
val_offset:11*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
fcsr_val: 0 */
TEST_FPSR_OP(fcvt.s.d, f25, f15, dyn, 0, 0, x3, 11*FLEN/8, x4, x1, x2)
inst_12:
// rs1==f5, rd==f13,
/* opcode: fcvt.s.d ; op1:f5; dest:f13; op1val:0x0; valaddr_reg:x3;
val_offset:12*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
fcsr_val: 0 */
TEST_FPSR_OP(fcvt.s.d, f13, f5, dyn, 0, 0, x3, 12*FLEN/8, x4, x1, x2)
inst_13:
// rs1==f7, rd==f23,
/* opcode: fcvt.s.d ; op1:f7; dest:f23; op1val:0x0; valaddr_reg:x3;
val_offset:13*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
fcsr_val: 0 */
TEST_FPSR_OP(fcvt.s.d, f23, f7, dyn, 0, 0, x3, 13*FLEN/8, x4, x1, x2)
inst_14:
// rs1==f9, rd==f17,
/* opcode: fcvt.s.d ; op1:f9; dest:f17; op1val:0x0; valaddr_reg:x3;
val_offset:14*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
fcsr_val: 0 */
TEST_FPSR_OP(fcvt.s.d, f17, f9, dyn, 0, 0, x3, 14*FLEN/8, x4, x1, x2)
inst_15:
// rs1==f26, rd==f1,
/* opcode: fcvt.s.d ; op1:f26; dest:f1; op1val:0x0; valaddr_reg:x3;
val_offset:15*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
fcsr_val: 0 */
TEST_FPSR_OP(fcvt.s.d, f1, f26, dyn, 0, 0, x3, 15*FLEN/8, x4, x1, x2)
inst_16:
// rs1==f29, rd==f7,
/* opcode: fcvt.s.d ; op1:f29; dest:f7; op1val:0x0; valaddr_reg:x3;
val_offset:16*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
fcsr_val: 0 */
TEST_FPSR_OP(fcvt.s.d, f7, f29, dyn, 0, 0, x3, 16*FLEN/8, x4, x1, x2)
inst_17:
// rs1==f22, rd==f29,
/* opcode: fcvt.s.d ; op1:f22; dest:f29; op1val:0x0; valaddr_reg:x3;
val_offset:17*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
fcsr_val: 0 */
TEST_FPSR_OP(fcvt.s.d, f29, f22, dyn, 0, 0, x3, 17*FLEN/8, x4, x1, x2)
inst_18:
// rs1==f25, rd==f9,
/* opcode: fcvt.s.d ; op1:f25; dest:f9; op1val:0x0; valaddr_reg:x3;
val_offset:18*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
fcsr_val: 0 */
TEST_FPSR_OP(fcvt.s.d, f9, f25, dyn, 0, 0, x3, 18*FLEN/8, x4, x1, x2)
inst_19:
// rs1==f30, rd==f15,
/* opcode: fcvt.s.d ; op1:f30; dest:f15; op1val:0x0; valaddr_reg:x3;
val_offset:19*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
fcsr_val: 0 */
TEST_FPSR_OP(fcvt.s.d, f15, f30, dyn, 0, 0, x3, 19*FLEN/8, x4, x1, x2)
inst_20:
// rs1==f17, rd==f4,
/* opcode: fcvt.s.d ; op1:f17; dest:f4; op1val:0x0; valaddr_reg:x3;
val_offset:20*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
fcsr_val: 0 */
TEST_FPSR_OP(fcvt.s.d, f4, f17, dyn, 0, 0, x3, 20*FLEN/8, x4, x1, x2)
inst_21:
// rs1==f13, rd==f20,
/* opcode: fcvt.s.d ; op1:f13; dest:f20; op1val:0x0; valaddr_reg:x3;
val_offset:21*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
fcsr_val: 0 */
TEST_FPSR_OP(fcvt.s.d, f20, f13, dyn, 0, 0, x3, 21*FLEN/8, x4, x1, x2)
inst_22:
// rs1==f12, rd==f11,
/* opcode: fcvt.s.d ; op1:f12; dest:f11; op1val:0x0; valaddr_reg:x3;
val_offset:22*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
fcsr_val: 0 */
TEST_FPSR_OP(fcvt.s.d, f11, f12, dyn, 0, 0, x3, 22*FLEN/8, x4, x1, x2)
inst_23:
// rs1==f0, rd==f14,
/* opcode: fcvt.s.d ; op1:f0; dest:f14; op1val:0x0; valaddr_reg:x3;
val_offset:23*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
fcsr_val: 0 */
TEST_FPSR_OP(fcvt.s.d, f14, f0, dyn, 0, 0, x3, 23*FLEN/8, x4, x1, x2)
inst_24:
// rs1==f21, rd==f24,
/* opcode: fcvt.s.d ; op1:f21; dest:f24; op1val:0x0; valaddr_reg:x3;
val_offset:24*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
fcsr_val: 0 */
TEST_FPSR_OP(fcvt.s.d, f24, f21, dyn, 0, 0, x3, 24*FLEN/8, x4, x1, x2)
inst_25:
// rs1==f10, rd==f26,
/* opcode: fcvt.s.d ; op1:f10; dest:f26; op1val:0x0; valaddr_reg:x3;
val_offset:25*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
fcsr_val: 0 */
TEST_FPSR_OP(fcvt.s.d, f26, f10, dyn, 0, 0, x3, 25*FLEN/8, x4, x1, x2)
inst_26:
// rs1==f24, rd==f6,
/* opcode: fcvt.s.d ; op1:f24; dest:f6; op1val:0x0; valaddr_reg:x3;
val_offset:26*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
fcsr_val: 0 */
TEST_FPSR_OP(fcvt.s.d, f6, f24, dyn, 0, 0, x3, 26*FLEN/8, x4, x1, x2)
inst_27:
// rs1==f4, rd==f10,
/* opcode: fcvt.s.d ; op1:f4; dest:f10; op1val:0x0; valaddr_reg:x3;
val_offset:27*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
fcsr_val: 0 */
TEST_FPSR_OP(fcvt.s.d, f10, f4, dyn, 0, 0, x3, 27*FLEN/8, x4, x1, x2)
inst_28:
// rs1==f27, rd==f2,
/* opcode: fcvt.s.d ; op1:f27; dest:f2; op1val:0x0; valaddr_reg:x3;
val_offset:28*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
fcsr_val: 0 */
TEST_FPSR_OP(fcvt.s.d, f2, f27, dyn, 0, 0, x3, 28*FLEN/8, x4, x1, x2)
inst_29:
// rs1==f18, rd==f16,
/* opcode: fcvt.s.d ; op1:f18; dest:f16; op1val:0x0; valaddr_reg:x3;
val_offset:29*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
fcsr_val: 0 */
TEST_FPSR_OP(fcvt.s.d, f16, f18, dyn, 0, 0, x3, 29*FLEN/8, x4, x1, x2)
inst_30:
// rs1==f31, rd==f12,
/* opcode: fcvt.s.d ; op1:f31; dest:f12; op1val:0x0; valaddr_reg:x3;
val_offset:30*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
fcsr_val: 0 */
TEST_FPSR_OP(fcvt.s.d, f12, f31, dyn, 0, 0, x3, 30*FLEN/8, x4, x1, x2)
inst_31:
// rs1==f14, rd==f31,
/* opcode: fcvt.s.d ; op1:f14; dest:f31; op1val:0x0; valaddr_reg:x3;
val_offset:31*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
fcsr_val: 0 */
TEST_FPSR_OP(fcvt.s.d, f31, f14, dyn, 0, 0, x3, 31*FLEN/8, x4, x1, x2)
inst_32:
// fs1 == 0 and fe1 == 0x3fd and fm1 == 0x93fdc7b89296c and fcsr == 0x0 and rm_val == 7
/* opcode: fcvt.s.d ; op1:f30; dest:f31; op1val:0x3fd93fdc7b89296c; valaddr_reg:x3;
val_offset:32*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
fcsr_val: 0 */
TEST_FPSR_OP(fcvt.s.d, f31, f30, dyn, 0, 0, x3, 32*FLEN/8, x4, x1, x2)
#endif
RVTEST_CODE_END
RVMODEL_HALT
RVTEST_DATA_BEGIN
.align 4
rvtest_data:
.word 0xbabecafe
.word 0xabecafeb
.word 0xbecafeba
.word 0xecafebab
test_dataset_0:
NAN_BOXED(4593818368519663827,64,FLEN)
NAN_BOXED(4600778710533613932,64,FLEN)
NAN_BOXED(4610891533192108602,64,FLEN)
NAN_BOXED(4615336721960794565,64,FLEN)
NAN_BOXED(4618534502842412089,64,FLEN)
NAN_BOXED(9217722483915607826,64,FLEN)
NAN_BOXED(10372132617207737155,64,FLEN)
NAN_BOXED(13828134130799532672,64,FLEN)
NAN_BOXED(0,64,FLEN)
NAN_BOXED(0,64,FLEN)
NAN_BOXED(0,64,FLEN)
NAN_BOXED(0,64,FLEN)
NAN_BOXED(0,64,FLEN)
NAN_BOXED(0,64,FLEN)
NAN_BOXED(0,64,FLEN)
NAN_BOXED(0,64,FLEN)
NAN_BOXED(0,64,FLEN)
NAN_BOXED(0,64,FLEN)
NAN_BOXED(0,64,FLEN)
NAN_BOXED(0,64,FLEN)
NAN_BOXED(0,64,FLEN)
NAN_BOXED(0,64,FLEN)
NAN_BOXED(0,64,FLEN)
NAN_BOXED(0,64,FLEN)
NAN_BOXED(0,64,FLEN)
NAN_BOXED(0,64,FLEN)
NAN_BOXED(0,64,FLEN)
NAN_BOXED(0,64,FLEN)
NAN_BOXED(0,64,FLEN)
NAN_BOXED(0,64,FLEN)
NAN_BOXED(0,64,FLEN)
NAN_BOXED(0,64,FLEN)
NAN_BOXED(4600778710533613932,64,FLEN)
RVTEST_DATA_END
RVMODEL_DATA_BEGIN
rvtest_sig_begin:
sig_begin_canary:
CANARY;
signature_x1_0:
.fill 0*((SIGALIGN)/4),4,0xdeadbeef
signature_x1_1:
.fill 66*((SIGALIGN)/4),4,0xdeadbeef
#ifdef rvtest_mtrap_routine
tsig_begin_canary:
CANARY;
tsig_begin_canary:
CANARY;
mtrap_sigptr:
.fill 64*(XLEN/32),4,0xdeadbeef
tsig_end_canary:
CANARY;
tsig_end_canary:
CANARY;
#endif
#ifdef rvtest_gpr_save
gpr_save:
.fill 32*XLEN/32,4,0xdeadbeef
#endif
sig_end_canary:
CANARY;
rvtest_sig_end:
RVMODEL_DATA_END

460
vendor/riscv-arch-tests/riscv-test-suite/rv32i_m/D/src/fcvt.s.d_b23-01.S vendored
View file

@ -1,460 +0,0 @@
// -----------
// This file was generated by riscv_ctg (https://github.com/riscv-software-src/riscv-ctg)
// version : 0.7.1
// timestamp : Fri Jun 17 14:03:33 2022 GMT
// usage : riscv_ctg \
// -- cgf // --cgf /scratch/pawan/work/normalised/RV32D/fcvt.s.d.cgf \
\
// -- xlen 32 \
// --randomize \
// -----------
//
// -----------
// Copyright (c) 2020. RISC-V International. All rights reserved.
// SPDX-License-Identifier: BSD-3-Clause
// -----------
//
// This assembly file tests the fcvt.s.d instruction of the RISC-V RV32FD_Zicsr,RV64FD_Zicsr extension for the fcvt.s.d_b23 covergroup.
//
#include "model_test.h"
#include "arch_test.h"
RVTEST_ISA("RV32IFD_Zicsr,RV64IFD_Zicsr")
.section .text.init
.org 0x80
.globl rvtest_entry_point
rvtest_entry_point:
RVMODEL_BOOT
RVTEST_CODE_BEGIN
#ifdef TEST_CASE_1
RVTEST_CASE(0,"//check ISA:=regex(.*I.*D.*);def TEST_CASE_1=True;",fcvt.s.d_b23)
RVTEST_FP_ENABLE()
RVTEST_VALBASEUPD(x3,test_dataset_0)
RVTEST_SIGBASE(x1,signature_x1_1)
inst_0:
// rs1 != rd, rs1==f18, rd==f3,fs1 == 0 and fe1 == 0x43d and fm1 == 0xffffffffffffc and fcsr == 0x0 and rm_val == 7
/* opcode: fcvt.s.d ; op1:f18; dest:f3; op1val:0x43dffffffffffffc; valaddr_reg:x3;
val_offset:0*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
fcsr_val: 0 */
TEST_FPSR_OP(fcvt.s.d, f3, f18, dyn, 0, 0, x3, 0*FLEN/8, x4, x1, x2)
inst_1:
// rs1 == rd, rs1==f28, rd==f28,fs1 == 0 and fe1 == 0x43d and fm1 == 0xffffffffffffc and fcsr == 0x20 and rm_val == 7
/* opcode: fcvt.s.d ; op1:f28; dest:f28; op1val:0x43dffffffffffffc; valaddr_reg:x3;
val_offset:1*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
fcsr_val: 32 */
TEST_FPSR_OP(fcvt.s.d, f28, f28, dyn, 32, 0, x3, 1*FLEN/8, x4, x1, x2)
inst_2:
// rs1==f15, rd==f1,fs1 == 0 and fe1 == 0x43d and fm1 == 0xffffffffffffc and fcsr == 0x40 and rm_val == 7
/* opcode: fcvt.s.d ; op1:f15; dest:f1; op1val:0x43dffffffffffffc; valaddr_reg:x3;
val_offset:2*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
fcsr_val: 64 */
TEST_FPSR_OP(fcvt.s.d, f1, f15, dyn, 64, 0, x3, 2*FLEN/8, x4, x1, x2)
inst_3:
// rs1==f6, rd==f8,fs1 == 0 and fe1 == 0x43d and fm1 == 0xffffffffffffc and fcsr == 0x60 and rm_val == 7
/* opcode: fcvt.s.d ; op1:f6; dest:f8; op1val:0x43dffffffffffffc; valaddr_reg:x3;
val_offset:3*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
fcsr_val: 96 */
TEST_FPSR_OP(fcvt.s.d, f8, f6, dyn, 96, 0, x3, 3*FLEN/8, x4, x1, x2)
inst_4:
// rs1==f30, rd==f18,fs1 == 0 and fe1 == 0x43d and fm1 == 0xffffffffffffc and fcsr == 0x80 and rm_val == 7
/* opcode: fcvt.s.d ; op1:f30; dest:f18; op1val:0x43dffffffffffffc; valaddr_reg:x3;
val_offset:4*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
fcsr_val: 128 */
TEST_FPSR_OP(fcvt.s.d, f18, f30, dyn, 128, 0, x3, 4*FLEN/8, x4, x1, x2)
inst_5:
// rs1==f3, rd==f24,fs1 == 0 and fe1 == 0x43d and fm1 == 0xffffffffffffd and fcsr == 0x0 and rm_val == 7
/* opcode: fcvt.s.d ; op1:f3; dest:f24; op1val:0x43dffffffffffffd; valaddr_reg:x3;
val_offset:5*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
fcsr_val: 0 */
TEST_FPSR_OP(fcvt.s.d, f24, f3, dyn, 0, 0, x3, 5*FLEN/8, x4, x1, x2)
inst_6:
// rs1==f29, rd==f7,fs1 == 0 and fe1 == 0x43d and fm1 == 0xffffffffffffd and fcsr == 0x20 and rm_val == 7
/* opcode: fcvt.s.d ; op1:f29; dest:f7; op1val:0x43dffffffffffffd; valaddr_reg:x3;
val_offset:6*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
fcsr_val: 32 */
TEST_FPSR_OP(fcvt.s.d, f7, f29, dyn, 32, 0, x3, 6*FLEN/8, x4, x1, x2)
inst_7:
// rs1==f2, rd==f11,fs1 == 0 and fe1 == 0x43d and fm1 == 0xffffffffffffd and fcsr == 0x40 and rm_val == 7
/* opcode: fcvt.s.d ; op1:f2; dest:f11; op1val:0x43dffffffffffffd; valaddr_reg:x3;
val_offset:7*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
fcsr_val: 64 */
TEST_FPSR_OP(fcvt.s.d, f11, f2, dyn, 64, 0, x3, 7*FLEN/8, x4, x1, x2)
inst_8:
// rs1==f22, rd==f23,fs1 == 0 and fe1 == 0x43d and fm1 == 0xffffffffffffd and fcsr == 0x60 and rm_val == 7
/* opcode: fcvt.s.d ; op1:f22; dest:f23; op1val:0x43dffffffffffffd; valaddr_reg:x3;
val_offset:8*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
fcsr_val: 96 */
TEST_FPSR_OP(fcvt.s.d, f23, f22, dyn, 96, 0, x3, 8*FLEN/8, x4, x1, x2)
inst_9:
// rs1==f31, rd==f14,fs1 == 0 and fe1 == 0x43d and fm1 == 0xffffffffffffd and fcsr == 0x80 and rm_val == 7
/* opcode: fcvt.s.d ; op1:f31; dest:f14; op1val:0x43dffffffffffffd; valaddr_reg:x3;
val_offset:9*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
fcsr_val: 128 */
TEST_FPSR_OP(fcvt.s.d, f14, f31, dyn, 128, 0, x3, 9*FLEN/8, x4, x1, x2)
inst_10:
// rs1==f25, rd==f12,fs1 == 0 and fe1 == 0x43d and fm1 == 0xffffffffffffe and fcsr == 0x0 and rm_val == 7
/* opcode: fcvt.s.d ; op1:f25; dest:f12; op1val:0x43dffffffffffffe; valaddr_reg:x3;
val_offset:10*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
fcsr_val: 0 */
TEST_FPSR_OP(fcvt.s.d, f12, f25, dyn, 0, 0, x3, 10*FLEN/8, x4, x1, x2)
inst_11:
// rs1==f14, rd==f10,fs1 == 0 and fe1 == 0x43d and fm1 == 0xffffffffffffe and fcsr == 0x20 and rm_val == 7
/* opcode: fcvt.s.d ; op1:f14; dest:f10; op1val:0x43dffffffffffffe; valaddr_reg:x3;
val_offset:11*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
fcsr_val: 32 */
TEST_FPSR_OP(fcvt.s.d, f10, f14, dyn, 32, 0, x3, 11*FLEN/8, x4, x1, x2)
inst_12:
// rs1==f16, rd==f4,fs1 == 0 and fe1 == 0x43d and fm1 == 0xffffffffffffe and fcsr == 0x40 and rm_val == 7
/* opcode: fcvt.s.d ; op1:f16; dest:f4; op1val:0x43dffffffffffffe; valaddr_reg:x3;
val_offset:12*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
fcsr_val: 64 */
TEST_FPSR_OP(fcvt.s.d, f4, f16, dyn, 64, 0, x3, 12*FLEN/8, x4, x1, x2)
inst_13:
// rs1==f23, rd==f6,fs1 == 0 and fe1 == 0x43d and fm1 == 0xffffffffffffe and fcsr == 0x60 and rm_val == 7
/* opcode: fcvt.s.d ; op1:f23; dest:f6; op1val:0x43dffffffffffffe; valaddr_reg:x3;
val_offset:13*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
fcsr_val: 96 */
TEST_FPSR_OP(fcvt.s.d, f6, f23, dyn, 96, 0, x3, 13*FLEN/8, x4, x1, x2)
inst_14:
// rs1==f5, rd==f27,fs1 == 0 and fe1 == 0x43d and fm1 == 0xffffffffffffe and fcsr == 0x80 and rm_val == 7
/* opcode: fcvt.s.d ; op1:f5; dest:f27; op1val:0x43dffffffffffffe; valaddr_reg:x3;
val_offset:14*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
fcsr_val: 128 */
TEST_FPSR_OP(fcvt.s.d, f27, f5, dyn, 128, 0, x3, 14*FLEN/8, x4, x1, x2)
inst_15:
// rs1==f1, rd==f22,fs1 == 0 and fe1 == 0x43d and fm1 == 0xfffffffffffff and fcsr == 0x0 and rm_val == 7
/* opcode: fcvt.s.d ; op1:f1; dest:f22; op1val:0x43dfffffffffffff; valaddr_reg:x3;
val_offset:15*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
fcsr_val: 0 */
TEST_FPSR_OP(fcvt.s.d, f22, f1, dyn, 0, 0, x3, 15*FLEN/8, x4, x1, x2)
inst_16:
// rs1==f12, rd==f17,fs1 == 0 and fe1 == 0x43d and fm1 == 0xfffffffffffff and fcsr == 0x20 and rm_val == 7
/* opcode: fcvt.s.d ; op1:f12; dest:f17; op1val:0x43dfffffffffffff; valaddr_reg:x3;
val_offset:16*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
fcsr_val: 32 */
TEST_FPSR_OP(fcvt.s.d, f17, f12, dyn, 32, 0, x3, 16*FLEN/8, x4, x1, x2)
inst_17:
// rs1==f8, rd==f26,fs1 == 0 and fe1 == 0x43d and fm1 == 0xfffffffffffff and fcsr == 0x40 and rm_val == 7
/* opcode: fcvt.s.d ; op1:f8; dest:f26; op1val:0x43dfffffffffffff; valaddr_reg:x3;
val_offset:17*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
fcsr_val: 64 */
TEST_FPSR_OP(fcvt.s.d, f26, f8, dyn, 64, 0, x3, 17*FLEN/8, x4, x1, x2)
inst_18:
// rs1==f0, rd==f9,fs1 == 0 and fe1 == 0x43d and fm1 == 0xfffffffffffff and fcsr == 0x60 and rm_val == 7
/* opcode: fcvt.s.d ; op1:f0; dest:f9; op1val:0x43dfffffffffffff; valaddr_reg:x3;
val_offset:18*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
fcsr_val: 96 */
TEST_FPSR_OP(fcvt.s.d, f9, f0, dyn, 96, 0, x3, 18*FLEN/8, x4, x1, x2)
inst_19:
// rs1==f19, rd==f25,fs1 == 0 and fe1 == 0x43d and fm1 == 0xfffffffffffff and fcsr == 0x80 and rm_val == 7
/* opcode: fcvt.s.d ; op1:f19; dest:f25; op1val:0x43dfffffffffffff; valaddr_reg:x3;
val_offset:19*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
fcsr_val: 128 */
TEST_FPSR_OP(fcvt.s.d, f25, f19, dyn, 128, 0, x3, 19*FLEN/8, x4, x1, x2)
inst_20:
// rs1==f21, rd==f15,fs1 == 0 and fe1 == 0x43e and fm1 == 0x0000000000000 and fcsr == 0x0 and rm_val == 7
/* opcode: fcvt.s.d ; op1:f21; dest:f15; op1val:0x43e0000000000000; valaddr_reg:x3;
val_offset:20*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
fcsr_val: 0 */
TEST_FPSR_OP(fcvt.s.d, f15, f21, dyn, 0, 0, x3, 20*FLEN/8, x4, x1, x2)
inst_21:
// rs1==f24, rd==f30,fs1 == 0 and fe1 == 0x43e and fm1 == 0x0000000000000 and fcsr == 0x20 and rm_val == 7
/* opcode: fcvt.s.d ; op1:f24; dest:f30; op1val:0x43e0000000000000; valaddr_reg:x3;
val_offset:21*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
fcsr_val: 32 */
TEST_FPSR_OP(fcvt.s.d, f30, f24, dyn, 32, 0, x3, 21*FLEN/8, x4, x1, x2)
inst_22:
// rs1==f11, rd==f16,fs1 == 0 and fe1 == 0x43e and fm1 == 0x0000000000000 and fcsr == 0x40 and rm_val == 7
/* opcode: fcvt.s.d ; op1:f11; dest:f16; op1val:0x43e0000000000000; valaddr_reg:x3;
val_offset:22*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
fcsr_val: 64 */
TEST_FPSR_OP(fcvt.s.d, f16, f11, dyn, 64, 0, x3, 22*FLEN/8, x4, x1, x2)
inst_23:
// rs1==f17, rd==f20,fs1 == 0 and fe1 == 0x43e and fm1 == 0x0000000000000 and fcsr == 0x60 and rm_val == 7
/* opcode: fcvt.s.d ; op1:f17; dest:f20; op1val:0x43e0000000000000; valaddr_reg:x3;
val_offset:23*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
fcsr_val: 96 */
TEST_FPSR_OP(fcvt.s.d, f20, f17, dyn, 96, 0, x3, 23*FLEN/8, x4, x1, x2)
inst_24:
// rs1==f9, rd==f21,fs1 == 0 and fe1 == 0x43e and fm1 == 0x0000000000000 and fcsr == 0x80 and rm_val == 7
/* opcode: fcvt.s.d ; op1:f9; dest:f21; op1val:0x43e0000000000000; valaddr_reg:x3;
val_offset:24*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
fcsr_val: 128 */
TEST_FPSR_OP(fcvt.s.d, f21, f9, dyn, 128, 0, x3, 24*FLEN/8, x4, x1, x2)
inst_25:
// rs1==f7, rd==f5,fs1 == 0 and fe1 == 0x43e and fm1 == 0x0000000000001 and fcsr == 0x0 and rm_val == 7
/* opcode: fcvt.s.d ; op1:f7; dest:f5; op1val:0x43e0000000000001; valaddr_reg:x3;
val_offset:25*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
fcsr_val: 0 */
TEST_FPSR_OP(fcvt.s.d, f5, f7, dyn, 0, 0, x3, 25*FLEN/8, x4, x1, x2)
inst_26:
// rs1==f10, rd==f29,fs1 == 0 and fe1 == 0x43e and fm1 == 0x0000000000001 and fcsr == 0x20 and rm_val == 7
/* opcode: fcvt.s.d ; op1:f10; dest:f29; op1val:0x43e0000000000001; valaddr_reg:x3;
val_offset:26*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
fcsr_val: 32 */
TEST_FPSR_OP(fcvt.s.d, f29, f10, dyn, 32, 0, x3, 26*FLEN/8, x4, x1, x2)
inst_27:
// rs1==f4, rd==f31,fs1 == 0 and fe1 == 0x43e and fm1 == 0x0000000000001 and fcsr == 0x40 and rm_val == 7
/* opcode: fcvt.s.d ; op1:f4; dest:f31; op1val:0x43e0000000000001; valaddr_reg:x3;
val_offset:27*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
fcsr_val: 64 */
TEST_FPSR_OP(fcvt.s.d, f31, f4, dyn, 64, 0, x3, 27*FLEN/8, x4, x1, x2)
inst_28:
// rs1==f26, rd==f2,fs1 == 0 and fe1 == 0x43e and fm1 == 0x0000000000001 and fcsr == 0x60 and rm_val == 7
/* opcode: fcvt.s.d ; op1:f26; dest:f2; op1val:0x43e0000000000001; valaddr_reg:x3;
val_offset:28*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
fcsr_val: 96 */
TEST_FPSR_OP(fcvt.s.d, f2, f26, dyn, 96, 0, x3, 28*FLEN/8, x4, x1, x2)
inst_29:
// rs1==f20, rd==f19,fs1 == 0 and fe1 == 0x43e and fm1 == 0x0000000000001 and fcsr == 0x80 and rm_val == 7
/* opcode: fcvt.s.d ; op1:f20; dest:f19; op1val:0x43e0000000000001; valaddr_reg:x3;
val_offset:29*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
fcsr_val: 128 */
TEST_FPSR_OP(fcvt.s.d, f19, f20, dyn, 128, 0, x3, 29*FLEN/8, x4, x1, x2)
inst_30:
// rs1==f27, rd==f0,fs1 == 0 and fe1 == 0x43e and fm1 == 0x0000000000002 and fcsr == 0x0 and rm_val == 7
/* opcode: fcvt.s.d ; op1:f27; dest:f0; op1val:0x43e0000000000002; valaddr_reg:x3;
val_offset:30*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
fcsr_val: 0 */
TEST_FPSR_OP(fcvt.s.d, f0, f27, dyn, 0, 0, x3, 30*FLEN/8, x4, x1, x2)
inst_31:
// rs1==f13,fs1 == 0 and fe1 == 0x43e and fm1 == 0x0000000000002 and fcsr == 0x20 and rm_val == 7
/* opcode: fcvt.s.d ; op1:f13; dest:f31; op1val:0x43e0000000000002; valaddr_reg:x3;
val_offset:31*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
fcsr_val: 32 */
TEST_FPSR_OP(fcvt.s.d, f31, f13, dyn, 32, 0, x3, 31*FLEN/8, x4, x1, x2)
inst_32:
// rd==f13,fs1 == 0 and fe1 == 0x43e and fm1 == 0x0000000000002 and fcsr == 0x40 and rm_val == 7
/* opcode: fcvt.s.d ; op1:f26; dest:f13; op1val:0x43e0000000000002; valaddr_reg:x3;
val_offset:32*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
fcsr_val: 64 */
TEST_FPSR_OP(fcvt.s.d, f13, f26, dyn, 64, 0, x3, 32*FLEN/8, x4, x1, x2)
inst_33:
// fs1 == 0 and fe1 == 0x43e and fm1 == 0x0000000000002 and fcsr == 0x60 and rm_val == 7
/* opcode: fcvt.s.d ; op1:f30; dest:f31; op1val:0x43e0000000000002; valaddr_reg:x3;
val_offset:33*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
fcsr_val: 96 */
TEST_FPSR_OP(fcvt.s.d, f31, f30, dyn, 96, 0, x3, 33*FLEN/8, x4, x1, x2)
inst_34:
// fs1 == 0 and fe1 == 0x43e and fm1 == 0x0000000000002 and fcsr == 0x80 and rm_val == 7
/* opcode: fcvt.s.d ; op1:f30; dest:f31; op1val:0x43e0000000000002; valaddr_reg:x3;
val_offset:34*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
fcsr_val: 128 */
TEST_FPSR_OP(fcvt.s.d, f31, f30, dyn, 128, 0, x3, 34*FLEN/8, x4, x1, x2)
inst_35:
// fs1 == 0 and fe1 == 0x43e and fm1 == 0x0000000000003 and fcsr == 0x0 and rm_val == 7
/* opcode: fcvt.s.d ; op1:f30; dest:f31; op1val:0x43e0000000000003; valaddr_reg:x3;
val_offset:35*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
fcsr_val: 0 */
TEST_FPSR_OP(fcvt.s.d, f31, f30, dyn, 0, 0, x3, 35*FLEN/8, x4, x1, x2)
inst_36:
// fs1 == 0 and fe1 == 0x43e and fm1 == 0x0000000000003 and fcsr == 0x20 and rm_val == 7
/* opcode: fcvt.s.d ; op1:f30; dest:f31; op1val:0x43e0000000000003; valaddr_reg:x3;
val_offset:36*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
fcsr_val: 32 */
TEST_FPSR_OP(fcvt.s.d, f31, f30, dyn, 32, 0, x3, 36*FLEN/8, x4, x1, x2)
inst_37:
// fs1 == 0 and fe1 == 0x43e and fm1 == 0x0000000000003 and fcsr == 0x40 and rm_val == 7
/* opcode: fcvt.s.d ; op1:f30; dest:f31; op1val:0x43e0000000000003; valaddr_reg:x3;
val_offset:37*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
fcsr_val: 64 */
TEST_FPSR_OP(fcvt.s.d, f31, f30, dyn, 64, 0, x3, 37*FLEN/8, x4, x1, x2)
inst_38:
// fs1 == 0 and fe1 == 0x43e and fm1 == 0x0000000000003 and fcsr == 0x60 and rm_val == 7
/* opcode: fcvt.s.d ; op1:f30; dest:f31; op1val:0x43e0000000000003; valaddr_reg:x3;
val_offset:38*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
fcsr_val: 96 */
TEST_FPSR_OP(fcvt.s.d, f31, f30, dyn, 96, 0, x3, 38*FLEN/8, x4, x1, x2)
inst_39:
// fs1 == 0 and fe1 == 0x43e and fm1 == 0x0000000000003 and fcsr == 0x80 and rm_val == 7
/* opcode: fcvt.s.d ; op1:f30; dest:f31; op1val:0x43e0000000000003; valaddr_reg:x3;
val_offset:39*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
fcsr_val: 128 */
TEST_FPSR_OP(fcvt.s.d, f31, f30, dyn, 128, 0, x3, 39*FLEN/8, x4, x1, x2)
inst_40:
// fs1 == 0 and fe1 == 0x43e and fm1 == 0x0000000000004 and fcsr == 0x0 and rm_val == 7
/* opcode: fcvt.s.d ; op1:f30; dest:f31; op1val:0x43e0000000000004; valaddr_reg:x3;
val_offset:40*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
fcsr_val: 0 */
TEST_FPSR_OP(fcvt.s.d, f31, f30, dyn, 0, 0, x3, 40*FLEN/8, x4, x1, x2)
inst_41:
// fs1 == 0 and fe1 == 0x43e and fm1 == 0x0000000000004 and fcsr == 0x20 and rm_val == 7
/* opcode: fcvt.s.d ; op1:f30; dest:f31; op1val:0x43e0000000000004; valaddr_reg:x3;
val_offset:41*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
fcsr_val: 32 */
TEST_FPSR_OP(fcvt.s.d, f31, f30, dyn, 32, 0, x3, 41*FLEN/8, x4, x1, x2)
inst_42:
// fs1 == 0 and fe1 == 0x43e and fm1 == 0x0000000000004 and fcsr == 0x40 and rm_val == 7
/* opcode: fcvt.s.d ; op1:f30; dest:f31; op1val:0x43e0000000000004; valaddr_reg:x3;
val_offset:42*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
fcsr_val: 64 */
TEST_FPSR_OP(fcvt.s.d, f31, f30, dyn, 64, 0, x3, 42*FLEN/8, x4, x1, x2)
inst_43:
// fs1 == 0 and fe1 == 0x43e and fm1 == 0x0000000000004 and fcsr == 0x60 and rm_val == 7
/* opcode: fcvt.s.d ; op1:f30; dest:f31; op1val:0x43e0000000000004; valaddr_reg:x3;
val_offset:43*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
fcsr_val: 96 */
TEST_FPSR_OP(fcvt.s.d, f31, f30, dyn, 96, 0, x3, 43*FLEN/8, x4, x1, x2)
inst_44:
// fs1 == 0 and fe1 == 0x43e and fm1 == 0x0000000000004 and fcsr == 0x80 and rm_val == 7
/* opcode: fcvt.s.d ; op1:f30; dest:f31; op1val:0x43e0000000000004; valaddr_reg:x3;
val_offset:44*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
fcsr_val: 128 */
TEST_FPSR_OP(fcvt.s.d, f31, f30, dyn, 128, 0, x3, 44*FLEN/8, x4, x1, x2)
inst_45:
// fs1 == 0 and fe1 == 0x43d and fm1 == 0xffffffffffffc and fcsr == 0x20 and rm_val == 7
/* opcode: fcvt.s.d ; op1:f30; dest:f31; op1val:0x43dffffffffffffc; valaddr_reg:x3;
val_offset:45*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
fcsr_val: 32 */
TEST_FPSR_OP(fcvt.s.d, f31, f30, dyn, 32, 0, x3, 45*FLEN/8, x4, x1, x2)
#endif
RVTEST_CODE_END
RVMODEL_HALT
RVTEST_DATA_BEGIN
.align 4
rvtest_data:
.word 0xbabecafe
.word 0xabecafeb
.word 0xbecafeba
.word 0xecafebab
test_dataset_0:
NAN_BOXED(4890909195324358652,64,FLEN)
NAN_BOXED(4890909195324358652,64,FLEN)
NAN_BOXED(4890909195324358652,64,FLEN)
NAN_BOXED(4890909195324358652,64,FLEN)
NAN_BOXED(4890909195324358652,64,FLEN)
NAN_BOXED(4890909195324358653,64,FLEN)
NAN_BOXED(4890909195324358653,64,FLEN)
NAN_BOXED(4890909195324358653,64,FLEN)
NAN_BOXED(4890909195324358653,64,FLEN)
NAN_BOXED(4890909195324358653,64,FLEN)
NAN_BOXED(4890909195324358654,64,FLEN)
NAN_BOXED(4890909195324358654,64,FLEN)
NAN_BOXED(4890909195324358654,64,FLEN)
NAN_BOXED(4890909195324358654,64,FLEN)
NAN_BOXED(4890909195324358654,64,FLEN)
NAN_BOXED(4890909195324358655,64,FLEN)
NAN_BOXED(4890909195324358655,64,FLEN)
NAN_BOXED(4890909195324358655,64,FLEN)
NAN_BOXED(4890909195324358655,64,FLEN)
NAN_BOXED(4890909195324358655,64,FLEN)
NAN_BOXED(4890909195324358656,64,FLEN)
NAN_BOXED(4890909195324358656,64,FLEN)
NAN_BOXED(4890909195324358656,64,FLEN)
NAN_BOXED(4890909195324358656,64,FLEN)
NAN_BOXED(4890909195324358656,64,FLEN)
NAN_BOXED(4890909195324358657,64,FLEN)
NAN_BOXED(4890909195324358657,64,FLEN)
NAN_BOXED(4890909195324358657,64,FLEN)
NAN_BOXED(4890909195324358657,64,FLEN)
NAN_BOXED(4890909195324358657,64,FLEN)
NAN_BOXED(4890909195324358658,64,FLEN)
NAN_BOXED(4890909195324358658,64,FLEN)
NAN_BOXED(4890909195324358658,64,FLEN)
NAN_BOXED(4890909195324358658,64,FLEN)
NAN_BOXED(4890909195324358658,64,FLEN)
NAN_BOXED(4890909195324358659,64,FLEN)
NAN_BOXED(4890909195324358659,64,FLEN)
NAN_BOXED(4890909195324358659,64,FLEN)
NAN_BOXED(4890909195324358659,64,FLEN)
NAN_BOXED(4890909195324358659,64,FLEN)
NAN_BOXED(4890909195324358660,64,FLEN)
NAN_BOXED(4890909195324358660,64,FLEN)
NAN_BOXED(4890909195324358660,64,FLEN)
NAN_BOXED(4890909195324358660,64,FLEN)
NAN_BOXED(4890909195324358660,64,FLEN)
NAN_BOXED(4890909195324358652,64,FLEN)
RVTEST_DATA_END
RVMODEL_DATA_BEGIN
rvtest_sig_begin:
sig_begin_canary:
CANARY;
signature_x1_0:
.fill 0*((SIGALIGN)/4),4,0xdeadbeef
signature_x1_1:
.fill 92*((SIGALIGN)/4),4,0xdeadbeef
#ifdef rvtest_mtrap_routine
tsig_begin_canary:
CANARY;
tsig_begin_canary:
CANARY;
mtrap_sigptr:
.fill 64*(XLEN/32),4,0xdeadbeef
tsig_end_canary:
CANARY;
tsig_end_canary:
CANARY;
#endif
#ifdef rvtest_gpr_save
gpr_save:
.fill 32*XLEN/32,4,0xdeadbeef
#endif
sig_end_canary:
CANARY;
rvtest_sig_end:
RVMODEL_DATA_END

940
vendor/riscv-arch-tests/riscv-test-suite/rv32i_m/D/src/fcvt.s.d_b24-01.S vendored
View file

@ -1,940 +0,0 @@
// -----------
// This file was generated by riscv_ctg (https://github.com/riscv-software-src/riscv-ctg)
// version : 0.7.1
// timestamp : Fri Jun 17 14:03:33 2022 GMT
// usage : riscv_ctg \
// -- cgf // --cgf /scratch/pawan/work/normalised/RV32D/fcvt.s.d.cgf \
\
// -- xlen 32 \
// --randomize \
// -----------
//
// -----------
// Copyright (c) 2020. RISC-V International. All rights reserved.
// SPDX-License-Identifier: BSD-3-Clause
// -----------
//
// This assembly file tests the fcvt.s.d instruction of the RISC-V RV32FD_Zicsr,RV64FD_Zicsr extension for the fcvt.s.d_b24 covergroup.
//
#include "model_test.h"
#include "arch_test.h"
RVTEST_ISA("RV32IFD_Zicsr,RV64IFD_Zicsr")
.section .text.init
.org 0x80
.globl rvtest_entry_point
rvtest_entry_point:
RVMODEL_BOOT
RVTEST_CODE_BEGIN
#ifdef TEST_CASE_1
RVTEST_CASE(0,"//check ISA:=regex(.*I.*D.*);def TEST_CASE_1=True;",fcvt.s.d_b24)
RVTEST_FP_ENABLE()
RVTEST_VALBASEUPD(x3,test_dataset_0)
RVTEST_SIGBASE(x1,signature_x1_1)
inst_0:
// rs1 != rd, rs1==f3, rd==f13,fs1 == 0 and fe1 == 0x000 and fm1 == 0x0000000000000 and fcsr == 0x0 and rm_val == 7
/* opcode: fcvt.s.d ; op1:f3; dest:f13; op1val:0x0; valaddr_reg:x3;
val_offset:0*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
fcsr_val: 0 */
TEST_FPSR_OP(fcvt.s.d, f13, f3, dyn, 0, 0, x3, 0*FLEN/8, x4, x1, x2)
inst_1:
// rs1 == rd, rs1==f0, rd==f0,fs1 == 0 and fe1 == 0x000 and fm1 == 0x0000000000000 and fcsr == 0x20 and rm_val == 7
/* opcode: fcvt.s.d ; op1:f0; dest:f0; op1val:0x0; valaddr_reg:x3;
val_offset:1*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
fcsr_val: 32 */
TEST_FPSR_OP(fcvt.s.d, f0, f0, dyn, 32, 0, x3, 1*FLEN/8, x4, x1, x2)
inst_2:
// rs1==f23, rd==f7,fs1 == 0 and fe1 == 0x000 and fm1 == 0x0000000000000 and fcsr == 0x40 and rm_val == 7
/* opcode: fcvt.s.d ; op1:f23; dest:f7; op1val:0x0; valaddr_reg:x3;
val_offset:2*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
fcsr_val: 64 */
TEST_FPSR_OP(fcvt.s.d, f7, f23, dyn, 64, 0, x3, 2*FLEN/8, x4, x1, x2)
inst_3:
// rs1==f31, rd==f29,fs1 == 0 and fe1 == 0x000 and fm1 == 0x0000000000000 and fcsr == 0x60 and rm_val == 7
/* opcode: fcvt.s.d ; op1:f31; dest:f29; op1val:0x0; valaddr_reg:x3;
val_offset:3*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
fcsr_val: 96 */
TEST_FPSR_OP(fcvt.s.d, f29, f31, dyn, 96, 0, x3, 3*FLEN/8, x4, x1, x2)
inst_4:
// rs1==f28, rd==f24,fs1 == 0 and fe1 == 0x000 and fm1 == 0x0000000000000 and fcsr == 0x80 and rm_val == 7
/* opcode: fcvt.s.d ; op1:f28; dest:f24; op1val:0x0; valaddr_reg:x3;
val_offset:4*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
fcsr_val: 128 */
TEST_FPSR_OP(fcvt.s.d, f24, f28, dyn, 128, 0, x3, 4*FLEN/8, x4, x1, x2)
inst_5:
// rs1==f4, rd==f15,fs1 == 0 and fe1 == 0x3f8 and fm1 == 0x47ae147ae147b and fcsr == 0x0 and rm_val == 7
/* opcode: fcvt.s.d ; op1:f4; dest:f15; op1val:0x3f847ae147ae147b; valaddr_reg:x3;
val_offset:5*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
fcsr_val: 0 */
TEST_FPSR_OP(fcvt.s.d, f15, f4, dyn, 0, 0, x3, 5*FLEN/8, x4, x1, x2)
inst_6:
// rs1==f29, rd==f14,fs1 == 0 and fe1 == 0x3f8 and fm1 == 0x47ae147ae147b and fcsr == 0x20 and rm_val == 7
/* opcode: fcvt.s.d ; op1:f29; dest:f14; op1val:0x3f847ae147ae147b; valaddr_reg:x3;
val_offset:6*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
fcsr_val: 32 */
TEST_FPSR_OP(fcvt.s.d, f14, f29, dyn, 32, 0, x3, 6*FLEN/8, x4, x1, x2)
inst_7:
// rs1==f26, rd==f17,fs1 == 0 and fe1 == 0x3f8 and fm1 == 0x47ae147ae147b and fcsr == 0x40 and rm_val == 7
/* opcode: fcvt.s.d ; op1:f26; dest:f17; op1val:0x3f847ae147ae147b; valaddr_reg:x3;
val_offset:7*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
fcsr_val: 64 */
TEST_FPSR_OP(fcvt.s.d, f17, f26, dyn, 64, 0, x3, 7*FLEN/8, x4, x1, x2)
inst_8:
// rs1==f19, rd==f18,fs1 == 0 and fe1 == 0x3f8 and fm1 == 0x47ae147ae147b and fcsr == 0x60 and rm_val == 7
/* opcode: fcvt.s.d ; op1:f19; dest:f18; op1val:0x3f847ae147ae147b; valaddr_reg:x3;
val_offset:8*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
fcsr_val: 96 */
TEST_FPSR_OP(fcvt.s.d, f18, f19, dyn, 96, 0, x3, 8*FLEN/8, x4, x1, x2)
inst_9:
// rs1==f14, rd==f5,fs1 == 0 and fe1 == 0x3f8 and fm1 == 0x47ae147ae147b and fcsr == 0x80 and rm_val == 7
/* opcode: fcvt.s.d ; op1:f14; dest:f5; op1val:0x3f847ae147ae147b; valaddr_reg:x3;
val_offset:9*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
fcsr_val: 128 */
TEST_FPSR_OP(fcvt.s.d, f5, f14, dyn, 128, 0, x3, 9*FLEN/8, x4, x1, x2)
inst_10:
// rs1==f16, rd==f10,fs1 == 0 and fe1 == 0x3fb and fm1 == 0x999999999999a and fcsr == 0x0 and rm_val == 7
/* opcode: fcvt.s.d ; op1:f16; dest:f10; op1val:0x3fb999999999999a; valaddr_reg:x3;
val_offset:10*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
fcsr_val: 0 */
TEST_FPSR_OP(fcvt.s.d, f10, f16, dyn, 0, 0, x3, 10*FLEN/8, x4, x1, x2)
inst_11:
// rs1==f24, rd==f9,fs1 == 0 and fe1 == 0x3fb and fm1 == 0x999999999999a and fcsr == 0x20 and rm_val == 7
/* opcode: fcvt.s.d ; op1:f24; dest:f9; op1val:0x3fb999999999999a; valaddr_reg:x3;
val_offset:11*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
fcsr_val: 32 */
TEST_FPSR_OP(fcvt.s.d, f9, f24, dyn, 32, 0, x3, 11*FLEN/8, x4, x1, x2)
inst_12:
// rs1==f15, rd==f27,fs1 == 0 and fe1 == 0x3fb and fm1 == 0x999999999999a and fcsr == 0x40 and rm_val == 7
/* opcode: fcvt.s.d ; op1:f15; dest:f27; op1val:0x3fb999999999999a; valaddr_reg:x3;
val_offset:12*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
fcsr_val: 64 */
TEST_FPSR_OP(fcvt.s.d, f27, f15, dyn, 64, 0, x3, 12*FLEN/8, x4, x1, x2)
inst_13:
// rs1==f8, rd==f25,fs1 == 0 and fe1 == 0x3fb and fm1 == 0x999999999999a and fcsr == 0x60 and rm_val == 7
/* opcode: fcvt.s.d ; op1:f8; dest:f25; op1val:0x3fb999999999999a; valaddr_reg:x3;
val_offset:13*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
fcsr_val: 96 */
TEST_FPSR_OP(fcvt.s.d, f25, f8, dyn, 96, 0, x3, 13*FLEN/8, x4, x1, x2)
inst_14:
// rs1==f30, rd==f23,fs1 == 0 and fe1 == 0x3fb and fm1 == 0x999999999999a and fcsr == 0x80 and rm_val == 7
/* opcode: fcvt.s.d ; op1:f30; dest:f23; op1val:0x3fb999999999999a; valaddr_reg:x3;
val_offset:14*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
fcsr_val: 128 */
TEST_FPSR_OP(fcvt.s.d, f23, f30, dyn, 128, 0, x3, 14*FLEN/8, x4, x1, x2)
inst_15:
// rs1==f11, rd==f6,fs1 == 0 and fe1 == 0x3fb and fm1 == 0xc28f5c28f5c29 and fcsr == 0x0 and rm_val == 7
/* opcode: fcvt.s.d ; op1:f11; dest:f6; op1val:0x3fbc28f5c28f5c29; valaddr_reg:x3;
val_offset:15*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
fcsr_val: 0 */
TEST_FPSR_OP(fcvt.s.d, f6, f11, dyn, 0, 0, x3, 15*FLEN/8, x4, x1, x2)
inst_16:
// rs1==f17, rd==f26,fs1 == 0 and fe1 == 0x3fb and fm1 == 0xc28f5c28f5c29 and fcsr == 0x20 and rm_val == 7
/* opcode: fcvt.s.d ; op1:f17; dest:f26; op1val:0x3fbc28f5c28f5c29; valaddr_reg:x3;
val_offset:16*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
fcsr_val: 32 */
TEST_FPSR_OP(fcvt.s.d, f26, f17, dyn, 32, 0, x3, 16*FLEN/8, x4, x1, x2)
inst_17:
// rs1==f5, rd==f3,fs1 == 0 and fe1 == 0x3fb and fm1 == 0xc28f5c28f5c29 and fcsr == 0x40 and rm_val == 7
/* opcode: fcvt.s.d ; op1:f5; dest:f3; op1val:0x3fbc28f5c28f5c29; valaddr_reg:x3;
val_offset:17*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
fcsr_val: 64 */
TEST_FPSR_OP(fcvt.s.d, f3, f5, dyn, 64, 0, x3, 17*FLEN/8, x4, x1, x2)
inst_18:
// rs1==f22, rd==f28,fs1 == 0 and fe1 == 0x3fb and fm1 == 0xc28f5c28f5c29 and fcsr == 0x60 and rm_val == 7
/* opcode: fcvt.s.d ; op1:f22; dest:f28; op1val:0x3fbc28f5c28f5c29; valaddr_reg:x3;
val_offset:18*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
fcsr_val: 96 */
TEST_FPSR_OP(fcvt.s.d, f28, f22, dyn, 96, 0, x3, 18*FLEN/8, x4, x1, x2)
inst_19:
// rs1==f18, rd==f20,fs1 == 0 and fe1 == 0x3fb and fm1 == 0xc28f5c28f5c29 and fcsr == 0x80 and rm_val == 7
/* opcode: fcvt.s.d ; op1:f18; dest:f20; op1val:0x3fbc28f5c28f5c29; valaddr_reg:x3;
val_offset:19*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
fcsr_val: 128 */
TEST_FPSR_OP(fcvt.s.d, f20, f18, dyn, 128, 0, x3, 19*FLEN/8, x4, x1, x2)
inst_20:
// rs1==f2, rd==f21,fs1 == 0 and fe1 == 0x3fe and fm1 == 0xc7ae147ae147b and fcsr == 0x0 and rm_val == 7
/* opcode: fcvt.s.d ; op1:f2; dest:f21; op1val:0x3fec7ae147ae147b; valaddr_reg:x3;
val_offset:20*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
fcsr_val: 0 */
TEST_FPSR_OP(fcvt.s.d, f21, f2, dyn, 0, 0, x3, 20*FLEN/8, x4, x1, x2)
inst_21:
// rs1==f9, rd==f8,fs1 == 0 and fe1 == 0x3fe and fm1 == 0xc7ae147ae147b and fcsr == 0x20 and rm_val == 7
/* opcode: fcvt.s.d ; op1:f9; dest:f8; op1val:0x3fec7ae147ae147b; valaddr_reg:x3;
val_offset:21*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
fcsr_val: 32 */
TEST_FPSR_OP(fcvt.s.d, f8, f9, dyn, 32, 0, x3, 21*FLEN/8, x4, x1, x2)
inst_22:
// rs1==f6, rd==f30,fs1 == 0 and fe1 == 0x3fe and fm1 == 0xc7ae147ae147b and fcsr == 0x40 and rm_val == 7
/* opcode: fcvt.s.d ; op1:f6; dest:f30; op1val:0x3fec7ae147ae147b; valaddr_reg:x3;
val_offset:22*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
fcsr_val: 64 */
TEST_FPSR_OP(fcvt.s.d, f30, f6, dyn, 64, 0, x3, 22*FLEN/8, x4, x1, x2)
inst_23:
// rs1==f25, rd==f4,fs1 == 0 and fe1 == 0x3fe and fm1 == 0xc7ae147ae147b and fcsr == 0x60 and rm_val == 7
/* opcode: fcvt.s.d ; op1:f25; dest:f4; op1val:0x3fec7ae147ae147b; valaddr_reg:x3;
val_offset:23*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
fcsr_val: 96 */
TEST_FPSR_OP(fcvt.s.d, f4, f25, dyn, 96, 0, x3, 23*FLEN/8, x4, x1, x2)
inst_24:
// rs1==f13, rd==f1,fs1 == 0 and fe1 == 0x3fe and fm1 == 0xc7ae147ae147b and fcsr == 0x80 and rm_val == 7
/* opcode: fcvt.s.d ; op1:f13; dest:f1; op1val:0x3fec7ae147ae147b; valaddr_reg:x3;
val_offset:24*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
fcsr_val: 128 */
TEST_FPSR_OP(fcvt.s.d, f1, f13, dyn, 128, 0, x3, 24*FLEN/8, x4, x1, x2)
inst_25:
// rs1==f10, rd==f19,fs1 == 0 and fe1 == 0x3fe and fm1 == 0xccccccccccccd and fcsr == 0x0 and rm_val == 7
/* opcode: fcvt.s.d ; op1:f10; dest:f19; op1val:0x3feccccccccccccd; valaddr_reg:x3;
val_offset:25*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
fcsr_val: 0 */
TEST_FPSR_OP(fcvt.s.d, f19, f10, dyn, 0, 0, x3, 25*FLEN/8, x4, x1, x2)
inst_26:
// rs1==f1, rd==f31,fs1 == 0 and fe1 == 0x3fe and fm1 == 0xccccccccccccd and fcsr == 0x20 and rm_val == 7
/* opcode: fcvt.s.d ; op1:f1; dest:f31; op1val:0x3feccccccccccccd; valaddr_reg:x3;
val_offset:26*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
fcsr_val: 32 */
TEST_FPSR_OP(fcvt.s.d, f31, f1, dyn, 32, 0, x3, 26*FLEN/8, x4, x1, x2)
inst_27:
// rs1==f7, rd==f12,fs1 == 0 and fe1 == 0x3fe and fm1 == 0xccccccccccccd and fcsr == 0x40 and rm_val == 7
/* opcode: fcvt.s.d ; op1:f7; dest:f12; op1val:0x3feccccccccccccd; valaddr_reg:x3;
val_offset:27*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
fcsr_val: 64 */
TEST_FPSR_OP(fcvt.s.d, f12, f7, dyn, 64, 0, x3, 27*FLEN/8, x4, x1, x2)
inst_28:
// rs1==f21, rd==f2,fs1 == 0 and fe1 == 0x3fe and fm1 == 0xccccccccccccd and fcsr == 0x60 and rm_val == 7
/* opcode: fcvt.s.d ; op1:f21; dest:f2; op1val:0x3feccccccccccccd; valaddr_reg:x3;
val_offset:28*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
fcsr_val: 96 */
TEST_FPSR_OP(fcvt.s.d, f2, f21, dyn, 96, 0, x3, 28*FLEN/8, x4, x1, x2)
inst_29:
// rs1==f20, rd==f11,fs1 == 0 and fe1 == 0x3fe and fm1 == 0xccccccccccccd and fcsr == 0x80 and rm_val == 7
/* opcode: fcvt.s.d ; op1:f20; dest:f11; op1val:0x3feccccccccccccd; valaddr_reg:x3;
val_offset:29*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
fcsr_val: 128 */
TEST_FPSR_OP(fcvt.s.d, f11, f20, dyn, 128, 0, x3, 29*FLEN/8, x4, x1, x2)
inst_30:
// rs1==f27, rd==f16,fs1 == 0 and fe1 == 0x3fe and fm1 == 0xfae147ae147ae and fcsr == 0x0 and rm_val == 7
/* opcode: fcvt.s.d ; op1:f27; dest:f16; op1val:0x3fefae147ae147ae; valaddr_reg:x3;
val_offset:30*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
fcsr_val: 0 */
TEST_FPSR_OP(fcvt.s.d, f16, f27, dyn, 0, 0, x3, 30*FLEN/8, x4, x1, x2)
inst_31:
// rs1==f12, rd==f22,fs1 == 0 and fe1 == 0x3fe and fm1 == 0xfae147ae147ae and fcsr == 0x20 and rm_val == 7
/* opcode: fcvt.s.d ; op1:f12; dest:f22; op1val:0x3fefae147ae147ae; valaddr_reg:x3;
val_offset:31*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
fcsr_val: 32 */
TEST_FPSR_OP(fcvt.s.d, f22, f12, dyn, 32, 0, x3, 31*FLEN/8, x4, x1, x2)
inst_32:
// fs1 == 0 and fe1 == 0x3fe and fm1 == 0xfae147ae147ae and fcsr == 0x40 and rm_val == 7
/* opcode: fcvt.s.d ; op1:f30; dest:f31; op1val:0x3fefae147ae147ae; valaddr_reg:x3;
val_offset:32*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
fcsr_val: 64 */
TEST_FPSR_OP(fcvt.s.d, f31, f30, dyn, 64, 0, x3, 32*FLEN/8, x4, x1, x2)
inst_33:
// fs1 == 0 and fe1 == 0x3fe and fm1 == 0xfae147ae147ae and fcsr == 0x60 and rm_val == 7
/* opcode: fcvt.s.d ; op1:f30; dest:f31; op1val:0x3fefae147ae147ae; valaddr_reg:x3;
val_offset:33*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
fcsr_val: 96 */
TEST_FPSR_OP(fcvt.s.d, f31, f30, dyn, 96, 0, x3, 33*FLEN/8, x4, x1, x2)
inst_34:
// fs1 == 0 and fe1 == 0x3fe and fm1 == 0xfae147ae147ae and fcsr == 0x80 and rm_val == 7
/* opcode: fcvt.s.d ; op1:f30; dest:f31; op1val:0x3fefae147ae147ae; valaddr_reg:x3;
val_offset:34*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
fcsr_val: 128 */
TEST_FPSR_OP(fcvt.s.d, f31, f30, dyn, 128, 0, x3, 34*FLEN/8, x4, x1, x2)
inst_35:
// fs1 == 0 and fe1 == 0x3ff and fm1 == 0x0000000000000 and fcsr == 0x0 and rm_val == 7
/* opcode: fcvt.s.d ; op1:f30; dest:f31; op1val:0x3ff0000000000000; valaddr_reg:x3;
val_offset:35*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
fcsr_val: 0 */
TEST_FPSR_OP(fcvt.s.d, f31, f30, dyn, 0, 0, x3, 35*FLEN/8, x4, x1, x2)
inst_36:
// fs1 == 0 and fe1 == 0x3ff and fm1 == 0x0000000000000 and fcsr == 0x20 and rm_val == 7
/* opcode: fcvt.s.d ; op1:f30; dest:f31; op1val:0x3ff0000000000000; valaddr_reg:x3;
val_offset:36*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
fcsr_val: 32 */
TEST_FPSR_OP(fcvt.s.d, f31, f30, dyn, 32, 0, x3, 36*FLEN/8, x4, x1, x2)
inst_37:
// fs1 == 0 and fe1 == 0x3ff and fm1 == 0x0000000000000 and fcsr == 0x40 and rm_val == 7
/* opcode: fcvt.s.d ; op1:f30; dest:f31; op1val:0x3ff0000000000000; valaddr_reg:x3;
val_offset:37*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
fcsr_val: 64 */
TEST_FPSR_OP(fcvt.s.d, f31, f30, dyn, 64, 0, x3, 37*FLEN/8, x4, x1, x2)
inst_38:
// fs1 == 0 and fe1 == 0x3ff and fm1 == 0x0000000000000 and fcsr == 0x60 and rm_val == 7
/* opcode: fcvt.s.d ; op1:f30; dest:f31; op1val:0x3ff0000000000000; valaddr_reg:x3;
val_offset:38*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
fcsr_val: 96 */
TEST_FPSR_OP(fcvt.s.d, f31, f30, dyn, 96, 0, x3, 38*FLEN/8, x4, x1, x2)
inst_39:
// fs1 == 0 and fe1 == 0x3ff and fm1 == 0x0000000000000 and fcsr == 0x80 and rm_val == 7
/* opcode: fcvt.s.d ; op1:f30; dest:f31; op1val:0x3ff0000000000000; valaddr_reg:x3;
val_offset:39*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
fcsr_val: 128 */
TEST_FPSR_OP(fcvt.s.d, f31, f30, dyn, 128, 0, x3, 39*FLEN/8, x4, x1, x2)
inst_40:
// fs1 == 0 and fe1 == 0x3ff and fm1 == 0x028f5c28f5c29 and fcsr == 0x0 and rm_val == 7
/* opcode: fcvt.s.d ; op1:f30; dest:f31; op1val:0x3ff028f5c28f5c29; valaddr_reg:x3;
val_offset:40*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
fcsr_val: 0 */
TEST_FPSR_OP(fcvt.s.d, f31, f30, dyn, 0, 0, x3, 40*FLEN/8, x4, x1, x2)
inst_41:
// fs1 == 0 and fe1 == 0x3ff and fm1 == 0x028f5c28f5c29 and fcsr == 0x20 and rm_val == 7
/* opcode: fcvt.s.d ; op1:f30; dest:f31; op1val:0x3ff028f5c28f5c29; valaddr_reg:x3;
val_offset:41*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
fcsr_val: 32 */
TEST_FPSR_OP(fcvt.s.d, f31, f30, dyn, 32, 0, x3, 41*FLEN/8, x4, x1, x2)
inst_42:
// fs1 == 0 and fe1 == 0x3ff and fm1 == 0x028f5c28f5c29 and fcsr == 0x40 and rm_val == 7
/* opcode: fcvt.s.d ; op1:f30; dest:f31; op1val:0x3ff028f5c28f5c29; valaddr_reg:x3;
val_offset:42*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
fcsr_val: 64 */
TEST_FPSR_OP(fcvt.s.d, f31, f30, dyn, 64, 0, x3, 42*FLEN/8, x4, x1, x2)
inst_43:
// fs1 == 0 and fe1 == 0x3ff and fm1 == 0x028f5c28f5c29 and fcsr == 0x60 and rm_val == 7
/* opcode: fcvt.s.d ; op1:f30; dest:f31; op1val:0x3ff028f5c28f5c29; valaddr_reg:x3;
val_offset:43*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
fcsr_val: 96 */
TEST_FPSR_OP(fcvt.s.d, f31, f30, dyn, 96, 0, x3, 43*FLEN/8, x4, x1, x2)
inst_44:
// fs1 == 0 and fe1 == 0x3ff and fm1 == 0x028f5c28f5c29 and fcsr == 0x80 and rm_val == 7
/* opcode: fcvt.s.d ; op1:f30; dest:f31; op1val:0x3ff028f5c28f5c29; valaddr_reg:x3;
val_offset:44*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
fcsr_val: 128 */
TEST_FPSR_OP(fcvt.s.d, f31, f30, dyn, 128, 0, x3, 44*FLEN/8, x4, x1, x2)
inst_45:
// fs1 == 0 and fe1 == 0x3ff and fm1 == 0x199999999999a and fcsr == 0x0 and rm_val == 7
/* opcode: fcvt.s.d ; op1:f30; dest:f31; op1val:0x3ff199999999999a; valaddr_reg:x3;
val_offset:45*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
fcsr_val: 0 */
TEST_FPSR_OP(fcvt.s.d, f31, f30, dyn, 0, 0, x3, 45*FLEN/8, x4, x1, x2)
inst_46:
// fs1 == 0 and fe1 == 0x3ff and fm1 == 0x199999999999a and fcsr == 0x20 and rm_val == 7
/* opcode: fcvt.s.d ; op1:f30; dest:f31; op1val:0x3ff199999999999a; valaddr_reg:x3;
val_offset:46*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
fcsr_val: 32 */
TEST_FPSR_OP(fcvt.s.d, f31, f30, dyn, 32, 0, x3, 46*FLEN/8, x4, x1, x2)
inst_47:
// fs1 == 0 and fe1 == 0x3ff and fm1 == 0x199999999999a and fcsr == 0x40 and rm_val == 7
/* opcode: fcvt.s.d ; op1:f30; dest:f31; op1val:0x3ff199999999999a; valaddr_reg:x3;
val_offset:47*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
fcsr_val: 64 */
TEST_FPSR_OP(fcvt.s.d, f31, f30, dyn, 64, 0, x3, 47*FLEN/8, x4, x1, x2)
inst_48:
// fs1 == 0 and fe1 == 0x3ff and fm1 == 0x199999999999a and fcsr == 0x60 and rm_val == 7
/* opcode: fcvt.s.d ; op1:f30; dest:f31; op1val:0x3ff199999999999a; valaddr_reg:x3;
val_offset:48*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
fcsr_val: 96 */
TEST_FPSR_OP(fcvt.s.d, f31, f30, dyn, 96, 0, x3, 48*FLEN/8, x4, x1, x2)
inst_49:
// fs1 == 0 and fe1 == 0x3ff and fm1 == 0x199999999999a and fcsr == 0x80 and rm_val == 7
/* opcode: fcvt.s.d ; op1:f30; dest:f31; op1val:0x3ff199999999999a; valaddr_reg:x3;
val_offset:49*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
fcsr_val: 128 */
TEST_FPSR_OP(fcvt.s.d, f31, f30, dyn, 128, 0, x3, 49*FLEN/8, x4, x1, x2)
inst_50:
// fs1 == 0 and fe1 == 0x3ff and fm1 == 0x1c28f5c28f5c3 and fcsr == 0x0 and rm_val == 7
/* opcode: fcvt.s.d ; op1:f30; dest:f31; op1val:0x3ff1c28f5c28f5c3; valaddr_reg:x3;
val_offset:50*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
fcsr_val: 0 */
TEST_FPSR_OP(fcvt.s.d, f31, f30, dyn, 0, 0, x3, 50*FLEN/8, x4, x1, x2)
inst_51:
// fs1 == 0 and fe1 == 0x3ff and fm1 == 0x1c28f5c28f5c3 and fcsr == 0x20 and rm_val == 7
/* opcode: fcvt.s.d ; op1:f30; dest:f31; op1val:0x3ff1c28f5c28f5c3; valaddr_reg:x3;
val_offset:51*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
fcsr_val: 32 */
TEST_FPSR_OP(fcvt.s.d, f31, f30, dyn, 32, 0, x3, 51*FLEN/8, x4, x1, x2)
inst_52:
// fs1 == 0 and fe1 == 0x3ff and fm1 == 0x1c28f5c28f5c3 and fcsr == 0x40 and rm_val == 7
/* opcode: fcvt.s.d ; op1:f30; dest:f31; op1val:0x3ff1c28f5c28f5c3; valaddr_reg:x3;
val_offset:52*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
fcsr_val: 64 */
TEST_FPSR_OP(fcvt.s.d, f31, f30, dyn, 64, 0, x3, 52*FLEN/8, x4, x1, x2)
inst_53:
// fs1 == 0 and fe1 == 0x3ff and fm1 == 0x1c28f5c28f5c3 and fcsr == 0x60 and rm_val == 7
/* opcode: fcvt.s.d ; op1:f30; dest:f31; op1val:0x3ff1c28f5c28f5c3; valaddr_reg:x3;
val_offset:53*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
fcsr_val: 96 */
TEST_FPSR_OP(fcvt.s.d, f31, f30, dyn, 96, 0, x3, 53*FLEN/8, x4, x1, x2)
inst_54:
// fs1 == 0 and fe1 == 0x3ff and fm1 == 0x1c28f5c28f5c3 and fcsr == 0x80 and rm_val == 7
/* opcode: fcvt.s.d ; op1:f30; dest:f31; op1val:0x3ff1c28f5c28f5c3; valaddr_reg:x3;
val_offset:54*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
fcsr_val: 128 */
TEST_FPSR_OP(fcvt.s.d, f31, f30, dyn, 128, 0, x3, 54*FLEN/8, x4, x1, x2)
inst_55:
// fs1 == 1 and fe1 == 0x3f8 and fm1 == 0x47ae147ae147b and fcsr == 0x0 and rm_val == 7
/* opcode: fcvt.s.d ; op1:f30; dest:f31; op1val:0xbf847ae147ae147b; valaddr_reg:x3;
val_offset:55*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
fcsr_val: 0 */
TEST_FPSR_OP(fcvt.s.d, f31, f30, dyn, 0, 0, x3, 55*FLEN/8, x4, x1, x2)
inst_56:
// fs1 == 1 and fe1 == 0x3f8 and fm1 == 0x47ae147ae147b and fcsr == 0x20 and rm_val == 7
/* opcode: fcvt.s.d ; op1:f30; dest:f31; op1val:0xbf847ae147ae147b; valaddr_reg:x3;
val_offset:56*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
fcsr_val: 32 */
TEST_FPSR_OP(fcvt.s.d, f31, f30, dyn, 32, 0, x3, 56*FLEN/8, x4, x1, x2)
inst_57:
// fs1 == 1 and fe1 == 0x3f8 and fm1 == 0x47ae147ae147b and fcsr == 0x40 and rm_val == 7
/* opcode: fcvt.s.d ; op1:f30; dest:f31; op1val:0xbf847ae147ae147b; valaddr_reg:x3;
val_offset:57*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
fcsr_val: 64 */
TEST_FPSR_OP(fcvt.s.d, f31, f30, dyn, 64, 0, x3, 57*FLEN/8, x4, x1, x2)
inst_58:
// fs1 == 1 and fe1 == 0x3f8 and fm1 == 0x47ae147ae147b and fcsr == 0x60 and rm_val == 7
/* opcode: fcvt.s.d ; op1:f30; dest:f31; op1val:0xbf847ae147ae147b; valaddr_reg:x3;
val_offset:58*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
fcsr_val: 96 */
TEST_FPSR_OP(fcvt.s.d, f31, f30, dyn, 96, 0, x3, 58*FLEN/8, x4, x1, x2)
inst_59:
// fs1 == 1 and fe1 == 0x3f8 and fm1 == 0x47ae147ae147b and fcsr == 0x80 and rm_val == 7
/* opcode: fcvt.s.d ; op1:f30; dest:f31; op1val:0xbf847ae147ae147b; valaddr_reg:x3;
val_offset:59*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
fcsr_val: 128 */
TEST_FPSR_OP(fcvt.s.d, f31, f30, dyn, 128, 0, x3, 59*FLEN/8, x4, x1, x2)
inst_60:
// fs1 == 1 and fe1 == 0x3fb and fm1 == 0x999999999999a and fcsr == 0x0 and rm_val == 7
/* opcode: fcvt.s.d ; op1:f30; dest:f31; op1val:0xbfb999999999999a; valaddr_reg:x3;
val_offset:60*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
fcsr_val: 0 */
TEST_FPSR_OP(fcvt.s.d, f31, f30, dyn, 0, 0, x3, 60*FLEN/8, x4, x1, x2)
inst_61:
// fs1 == 1 and fe1 == 0x3fb and fm1 == 0x999999999999a and fcsr == 0x20 and rm_val == 7
/* opcode: fcvt.s.d ; op1:f30; dest:f31; op1val:0xbfb999999999999a; valaddr_reg:x3;
val_offset:61*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
fcsr_val: 32 */
TEST_FPSR_OP(fcvt.s.d, f31, f30, dyn, 32, 0, x3, 61*FLEN/8, x4, x1, x2)
inst_62:
// fs1 == 1 and fe1 == 0x3fb and fm1 == 0x999999999999a and fcsr == 0x40 and rm_val == 7
/* opcode: fcvt.s.d ; op1:f30; dest:f31; op1val:0xbfb999999999999a; valaddr_reg:x3;
val_offset:62*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
fcsr_val: 64 */
TEST_FPSR_OP(fcvt.s.d, f31, f30, dyn, 64, 0, x3, 62*FLEN/8, x4, x1, x2)
inst_63:
// fs1 == 1 and fe1 == 0x3fb and fm1 == 0x999999999999a and fcsr == 0x60 and rm_val == 7
/* opcode: fcvt.s.d ; op1:f30; dest:f31; op1val:0xbfb999999999999a; valaddr_reg:x3;
val_offset:63*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
fcsr_val: 96 */
TEST_FPSR_OP(fcvt.s.d, f31, f30, dyn, 96, 0, x3, 63*FLEN/8, x4, x1, x2)
inst_64:
// fs1 == 1 and fe1 == 0x3fb and fm1 == 0x999999999999a and fcsr == 0x80 and rm_val == 7
/* opcode: fcvt.s.d ; op1:f30; dest:f31; op1val:0xbfb999999999999a; valaddr_reg:x3;
val_offset:64*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
fcsr_val: 128 */
TEST_FPSR_OP(fcvt.s.d, f31, f30, dyn, 128, 0, x3, 64*FLEN/8, x4, x1, x2)
inst_65:
// fs1 == 1 and fe1 == 0x3fb and fm1 == 0xc28f5c28f5c29 and fcsr == 0x0 and rm_val == 7
/* opcode: fcvt.s.d ; op1:f30; dest:f31; op1val:0xbfbc28f5c28f5c29; valaddr_reg:x3;
val_offset:65*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
fcsr_val: 0 */
TEST_FPSR_OP(fcvt.s.d, f31, f30, dyn, 0, 0, x3, 65*FLEN/8, x4, x1, x2)
inst_66:
// fs1 == 1 and fe1 == 0x3fb and fm1 == 0xc28f5c28f5c29 and fcsr == 0x20 and rm_val == 7
/* opcode: fcvt.s.d ; op1:f30; dest:f31; op1val:0xbfbc28f5c28f5c29; valaddr_reg:x3;
val_offset:66*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
fcsr_val: 32 */
TEST_FPSR_OP(fcvt.s.d, f31, f30, dyn, 32, 0, x3, 66*FLEN/8, x4, x1, x2)
inst_67:
// fs1 == 1 and fe1 == 0x3fb and fm1 == 0xc28f5c28f5c29 and fcsr == 0x40 and rm_val == 7
/* opcode: fcvt.s.d ; op1:f30; dest:f31; op1val:0xbfbc28f5c28f5c29; valaddr_reg:x3;
val_offset:67*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
fcsr_val: 64 */
TEST_FPSR_OP(fcvt.s.d, f31, f30, dyn, 64, 0, x3, 67*FLEN/8, x4, x1, x2)
inst_68:
// fs1 == 1 and fe1 == 0x3fb and fm1 == 0xc28f5c28f5c29 and fcsr == 0x60 and rm_val == 7
/* opcode: fcvt.s.d ; op1:f30; dest:f31; op1val:0xbfbc28f5c28f5c29; valaddr_reg:x3;
val_offset:68*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
fcsr_val: 96 */
TEST_FPSR_OP(fcvt.s.d, f31, f30, dyn, 96, 0, x3, 68*FLEN/8, x4, x1, x2)
inst_69:
// fs1 == 1 and fe1 == 0x3fb and fm1 == 0xc28f5c28f5c29 and fcsr == 0x80 and rm_val == 7
/* opcode: fcvt.s.d ; op1:f30; dest:f31; op1val:0xbfbc28f5c28f5c29; valaddr_reg:x3;
val_offset:69*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
fcsr_val: 128 */
TEST_FPSR_OP(fcvt.s.d, f31, f30, dyn, 128, 0, x3, 69*FLEN/8, x4, x1, x2)
inst_70:
// fs1 == 1 and fe1 == 0x3fe and fm1 == 0xc7ae147ae147b and fcsr == 0x0 and rm_val == 7
/* opcode: fcvt.s.d ; op1:f30; dest:f31; op1val:0xbfec7ae147ae147b; valaddr_reg:x3;
val_offset:70*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
fcsr_val: 0 */
TEST_FPSR_OP(fcvt.s.d, f31, f30, dyn, 0, 0, x3, 70*FLEN/8, x4, x1, x2)
inst_71:
// fs1 == 1 and fe1 == 0x3fe and fm1 == 0xc7ae147ae147b and fcsr == 0x20 and rm_val == 7
/* opcode: fcvt.s.d ; op1:f30; dest:f31; op1val:0xbfec7ae147ae147b; valaddr_reg:x3;
val_offset:71*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
fcsr_val: 32 */
TEST_FPSR_OP(fcvt.s.d, f31, f30, dyn, 32, 0, x3, 71*FLEN/8, x4, x1, x2)
inst_72:
// fs1 == 1 and fe1 == 0x3fe and fm1 == 0xc7ae147ae147b and fcsr == 0x40 and rm_val == 7
/* opcode: fcvt.s.d ; op1:f30; dest:f31; op1val:0xbfec7ae147ae147b; valaddr_reg:x3;
val_offset:72*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
fcsr_val: 64 */
TEST_FPSR_OP(fcvt.s.d, f31, f30, dyn, 64, 0, x3, 72*FLEN/8, x4, x1, x2)
inst_73:
// fs1 == 1 and fe1 == 0x3fe and fm1 == 0xc7ae147ae147b and fcsr == 0x60 and rm_val == 7
/* opcode: fcvt.s.d ; op1:f30; dest:f31; op1val:0xbfec7ae147ae147b; valaddr_reg:x3;
val_offset:73*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
fcsr_val: 96 */
TEST_FPSR_OP(fcvt.s.d, f31, f30, dyn, 96, 0, x3, 73*FLEN/8, x4, x1, x2)
inst_74:
// fs1 == 1 and fe1 == 0x3fe and fm1 == 0xc7ae147ae147b and fcsr == 0x80 and rm_val == 7
/* opcode: fcvt.s.d ; op1:f30; dest:f31; op1val:0xbfec7ae147ae147b; valaddr_reg:x3;
val_offset:74*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
fcsr_val: 128 */
TEST_FPSR_OP(fcvt.s.d, f31, f30, dyn, 128, 0, x3, 74*FLEN/8, x4, x1, x2)
inst_75:
// fs1 == 1 and fe1 == 0x3fe and fm1 == 0xccccccccccccd and fcsr == 0x0 and rm_val == 7
/* opcode: fcvt.s.d ; op1:f30; dest:f31; op1val:0xbfeccccccccccccd; valaddr_reg:x3;
val_offset:75*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
fcsr_val: 0 */
TEST_FPSR_OP(fcvt.s.d, f31, f30, dyn, 0, 0, x3, 75*FLEN/8, x4, x1, x2)
inst_76:
// fs1 == 1 and fe1 == 0x3fe and fm1 == 0xccccccccccccd and fcsr == 0x20 and rm_val == 7
/* opcode: fcvt.s.d ; op1:f30; dest:f31; op1val:0xbfeccccccccccccd; valaddr_reg:x3;
val_offset:76*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
fcsr_val: 32 */
TEST_FPSR_OP(fcvt.s.d, f31, f30, dyn, 32, 0, x3, 76*FLEN/8, x4, x1, x2)
inst_77:
// fs1 == 1 and fe1 == 0x3fe and fm1 == 0xccccccccccccd and fcsr == 0x40 and rm_val == 7
/* opcode: fcvt.s.d ; op1:f30; dest:f31; op1val:0xbfeccccccccccccd; valaddr_reg:x3;
val_offset:77*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
fcsr_val: 64 */
TEST_FPSR_OP(fcvt.s.d, f31, f30, dyn, 64, 0, x3, 77*FLEN/8, x4, x1, x2)
inst_78:
// fs1 == 1 and fe1 == 0x3fe and fm1 == 0xccccccccccccd and fcsr == 0x60 and rm_val == 7
/* opcode: fcvt.s.d ; op1:f30; dest:f31; op1val:0xbfeccccccccccccd; valaddr_reg:x3;
val_offset:78*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
fcsr_val: 96 */
TEST_FPSR_OP(fcvt.s.d, f31, f30, dyn, 96, 0, x3, 78*FLEN/8, x4, x1, x2)
inst_79:
// fs1 == 1 and fe1 == 0x3fe and fm1 == 0xccccccccccccd and fcsr == 0x80 and rm_val == 7
/* opcode: fcvt.s.d ; op1:f30; dest:f31; op1val:0xbfeccccccccccccd; valaddr_reg:x3;
val_offset:79*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
fcsr_val: 128 */
TEST_FPSR_OP(fcvt.s.d, f31, f30, dyn, 128, 0, x3, 79*FLEN/8, x4, x1, x2)
inst_80:
// fs1 == 1 and fe1 == 0x3fe and fm1 == 0xfae147ae147ae and fcsr == 0x0 and rm_val == 7
/* opcode: fcvt.s.d ; op1:f30; dest:f31; op1val:0xbfefae147ae147ae; valaddr_reg:x3;
val_offset:80*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
fcsr_val: 0 */
TEST_FPSR_OP(fcvt.s.d, f31, f30, dyn, 0, 0, x3, 80*FLEN/8, x4, x1, x2)
inst_81:
// fs1 == 1 and fe1 == 0x3fe and fm1 == 0xfae147ae147ae and fcsr == 0x20 and rm_val == 7
/* opcode: fcvt.s.d ; op1:f30; dest:f31; op1val:0xbfefae147ae147ae; valaddr_reg:x3;
val_offset:81*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
fcsr_val: 32 */
TEST_FPSR_OP(fcvt.s.d, f31, f30, dyn, 32, 0, x3, 81*FLEN/8, x4, x1, x2)
inst_82:
// fs1 == 1 and fe1 == 0x3fe and fm1 == 0xfae147ae147ae and fcsr == 0x40 and rm_val == 7
/* opcode: fcvt.s.d ; op1:f30; dest:f31; op1val:0xbfefae147ae147ae; valaddr_reg:x3;
val_offset:82*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
fcsr_val: 64 */
TEST_FPSR_OP(fcvt.s.d, f31, f30, dyn, 64, 0, x3, 82*FLEN/8, x4, x1, x2)
inst_83:
// fs1 == 1 and fe1 == 0x3fe and fm1 == 0xfae147ae147ae and fcsr == 0x60 and rm_val == 7
/* opcode: fcvt.s.d ; op1:f30; dest:f31; op1val:0xbfefae147ae147ae; valaddr_reg:x3;
val_offset:83*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
fcsr_val: 96 */
TEST_FPSR_OP(fcvt.s.d, f31, f30, dyn, 96, 0, x3, 83*FLEN/8, x4, x1, x2)
inst_84:
// fs1 == 1 and fe1 == 0x3fe and fm1 == 0xfae147ae147ae and fcsr == 0x80 and rm_val == 7
/* opcode: fcvt.s.d ; op1:f30; dest:f31; op1val:0xbfefae147ae147ae; valaddr_reg:x3;
val_offset:84*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
fcsr_val: 128 */
TEST_FPSR_OP(fcvt.s.d, f31, f30, dyn, 128, 0, x3, 84*FLEN/8, x4, x1, x2)
inst_85:
// fs1 == 1 and fe1 == 0x3ff and fm1 == 0x0000000000000 and fcsr == 0x0 and rm_val == 7
/* opcode: fcvt.s.d ; op1:f30; dest:f31; op1val:0xbff0000000000000; valaddr_reg:x3;
val_offset:85*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
fcsr_val: 0 */
TEST_FPSR_OP(fcvt.s.d, f31, f30, dyn, 0, 0, x3, 85*FLEN/8, x4, x1, x2)
inst_86:
// fs1 == 1 and fe1 == 0x3ff and fm1 == 0x0000000000000 and fcsr == 0x20 and rm_val == 7
/* opcode: fcvt.s.d ; op1:f30; dest:f31; op1val:0xbff0000000000000; valaddr_reg:x3;
val_offset:86*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
fcsr_val: 32 */
TEST_FPSR_OP(fcvt.s.d, f31, f30, dyn, 32, 0, x3, 86*FLEN/8, x4, x1, x2)
inst_87:
// fs1 == 1 and fe1 == 0x3ff and fm1 == 0x0000000000000 and fcsr == 0x40 and rm_val == 7
/* opcode: fcvt.s.d ; op1:f30; dest:f31; op1val:0xbff0000000000000; valaddr_reg:x3;
val_offset:87*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
fcsr_val: 64 */
TEST_FPSR_OP(fcvt.s.d, f31, f30, dyn, 64, 0, x3, 87*FLEN/8, x4, x1, x2)
inst_88:
// fs1 == 1 and fe1 == 0x3ff and fm1 == 0x0000000000000 and fcsr == 0x60 and rm_val == 7
/* opcode: fcvt.s.d ; op1:f30; dest:f31; op1val:0xbff0000000000000; valaddr_reg:x3;
val_offset:88*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
fcsr_val: 96 */
TEST_FPSR_OP(fcvt.s.d, f31, f30, dyn, 96, 0, x3, 88*FLEN/8, x4, x1, x2)
inst_89:
// fs1 == 1 and fe1 == 0x3ff and fm1 == 0x0000000000000 and fcsr == 0x80 and rm_val == 7
/* opcode: fcvt.s.d ; op1:f30; dest:f31; op1val:0xbff0000000000000; valaddr_reg:x3;
val_offset:89*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
fcsr_val: 128 */
TEST_FPSR_OP(fcvt.s.d, f31, f30, dyn, 128, 0, x3, 89*FLEN/8, x4, x1, x2)
inst_90:
// fs1 == 1 and fe1 == 0x3ff and fm1 == 0x028f5c28f5c29 and fcsr == 0x0 and rm_val == 7
/* opcode: fcvt.s.d ; op1:f30; dest:f31; op1val:0xbff028f5c28f5c29; valaddr_reg:x3;
val_offset:90*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
fcsr_val: 0 */
TEST_FPSR_OP(fcvt.s.d, f31, f30, dyn, 0, 0, x3, 90*FLEN/8, x4, x1, x2)
inst_91:
// fs1 == 1 and fe1 == 0x3ff and fm1 == 0x028f5c28f5c29 and fcsr == 0x20 and rm_val == 7
/* opcode: fcvt.s.d ; op1:f30; dest:f31; op1val:0xbff028f5c28f5c29; valaddr_reg:x3;
val_offset:91*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
fcsr_val: 32 */
TEST_FPSR_OP(fcvt.s.d, f31, f30, dyn, 32, 0, x3, 91*FLEN/8, x4, x1, x2)
inst_92:
// fs1 == 1 and fe1 == 0x3ff and fm1 == 0x028f5c28f5c29 and fcsr == 0x40 and rm_val == 7
/* opcode: fcvt.s.d ; op1:f30; dest:f31; op1val:0xbff028f5c28f5c29; valaddr_reg:x3;
val_offset:92*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
fcsr_val: 64 */
TEST_FPSR_OP(fcvt.s.d, f31, f30, dyn, 64, 0, x3, 92*FLEN/8, x4, x1, x2)
inst_93:
// fs1 == 1 and fe1 == 0x3ff and fm1 == 0x028f5c28f5c29 and fcsr == 0x60 and rm_val == 7
/* opcode: fcvt.s.d ; op1:f30; dest:f31; op1val:0xbff028f5c28f5c29; valaddr_reg:x3;
val_offset:93*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
fcsr_val: 96 */
TEST_FPSR_OP(fcvt.s.d, f31, f30, dyn, 96, 0, x3, 93*FLEN/8, x4, x1, x2)
inst_94:
// fs1 == 1 and fe1 == 0x3ff and fm1 == 0x028f5c28f5c29 and fcsr == 0x80 and rm_val == 7
/* opcode: fcvt.s.d ; op1:f30; dest:f31; op1val:0xbff028f5c28f5c29; valaddr_reg:x3;
val_offset:94*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
fcsr_val: 128 */
TEST_FPSR_OP(fcvt.s.d, f31, f30, dyn, 128, 0, x3, 94*FLEN/8, x4, x1, x2)
inst_95:
// fs1 == 1 and fe1 == 0x3ff and fm1 == 0x199999999999a and fcsr == 0x0 and rm_val == 7
/* opcode: fcvt.s.d ; op1:f30; dest:f31; op1val:0xbff199999999999a; valaddr_reg:x3;
val_offset:95*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
fcsr_val: 0 */
TEST_FPSR_OP(fcvt.s.d, f31, f30, dyn, 0, 0, x3, 95*FLEN/8, x4, x1, x2)
inst_96:
// fs1 == 1 and fe1 == 0x3ff and fm1 == 0x199999999999a and fcsr == 0x20 and rm_val == 7
/* opcode: fcvt.s.d ; op1:f30; dest:f31; op1val:0xbff199999999999a; valaddr_reg:x3;
val_offset:96*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
fcsr_val: 32 */
TEST_FPSR_OP(fcvt.s.d, f31, f30, dyn, 32, 0, x3, 96*FLEN/8, x4, x1, x2)
inst_97:
// fs1 == 1 and fe1 == 0x3ff and fm1 == 0x199999999999a and fcsr == 0x40 and rm_val == 7
/* opcode: fcvt.s.d ; op1:f30; dest:f31; op1val:0xbff199999999999a; valaddr_reg:x3;
val_offset:97*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
fcsr_val: 64 */
TEST_FPSR_OP(fcvt.s.d, f31, f30, dyn, 64, 0, x3, 97*FLEN/8, x4, x1, x2)
inst_98:
// fs1 == 1 and fe1 == 0x3ff and fm1 == 0x199999999999a and fcsr == 0x60 and rm_val == 7
/* opcode: fcvt.s.d ; op1:f30; dest:f31; op1val:0xbff199999999999a; valaddr_reg:x3;
val_offset:98*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
fcsr_val: 96 */
TEST_FPSR_OP(fcvt.s.d, f31, f30, dyn, 96, 0, x3, 98*FLEN/8, x4, x1, x2)
inst_99:
// fs1 == 1 and fe1 == 0x3ff and fm1 == 0x199999999999a and fcsr == 0x80 and rm_val == 7
/* opcode: fcvt.s.d ; op1:f30; dest:f31; op1val:0xbff199999999999a; valaddr_reg:x3;
val_offset:99*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
fcsr_val: 128 */
TEST_FPSR_OP(fcvt.s.d, f31, f30, dyn, 128, 0, x3, 99*FLEN/8, x4, x1, x2)
inst_100:
// fs1 == 1 and fe1 == 0x3ff and fm1 == 0x1c28f5c28f5c3 and fcsr == 0x0 and rm_val == 7
/* opcode: fcvt.s.d ; op1:f30; dest:f31; op1val:0xbff1c28f5c28f5c3; valaddr_reg:x3;
val_offset:100*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
fcsr_val: 0 */
TEST_FPSR_OP(fcvt.s.d, f31, f30, dyn, 0, 0, x3, 100*FLEN/8, x4, x1, x2)
inst_101:
// fs1 == 1 and fe1 == 0x3ff and fm1 == 0x1c28f5c28f5c3 and fcsr == 0x20 and rm_val == 7
/* opcode: fcvt.s.d ; op1:f30; dest:f31; op1val:0xbff1c28f5c28f5c3; valaddr_reg:x3;
val_offset:101*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
fcsr_val: 32 */
TEST_FPSR_OP(fcvt.s.d, f31, f30, dyn, 32, 0, x3, 101*FLEN/8, x4, x1, x2)
inst_102:
// fs1 == 1 and fe1 == 0x3ff and fm1 == 0x1c28f5c28f5c3 and fcsr == 0x40 and rm_val == 7
/* opcode: fcvt.s.d ; op1:f30; dest:f31; op1val:0xbff1c28f5c28f5c3; valaddr_reg:x3;
val_offset:102*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
fcsr_val: 64 */
TEST_FPSR_OP(fcvt.s.d, f31, f30, dyn, 64, 0, x3, 102*FLEN/8, x4, x1, x2)
inst_103:
// fs1 == 1 and fe1 == 0x3ff and fm1 == 0x1c28f5c28f5c3 and fcsr == 0x60 and rm_val == 7
/* opcode: fcvt.s.d ; op1:f30; dest:f31; op1val:0xbff1c28f5c28f5c3; valaddr_reg:x3;
val_offset:103*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
fcsr_val: 96 */
TEST_FPSR_OP(fcvt.s.d, f31, f30, dyn, 96, 0, x3, 103*FLEN/8, x4, x1, x2)
inst_104:
// fs1 == 1 and fe1 == 0x3ff and fm1 == 0x1c28f5c28f5c3 and fcsr == 0x80 and rm_val == 7
/* opcode: fcvt.s.d ; op1:f30; dest:f31; op1val:0xbff1c28f5c28f5c3; valaddr_reg:x3;
val_offset:104*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
fcsr_val: 128 */
TEST_FPSR_OP(fcvt.s.d, f31, f30, dyn, 128, 0, x3, 104*FLEN/8, x4, x1, x2)
inst_105:
// fs1 == 0 and fe1 == 0x000 and fm1 == 0x0000000000000 and fcsr == 0x20 and rm_val == 7
/* opcode: fcvt.s.d ; op1:f30; dest:f31; op1val:0x0; valaddr_reg:x3;
val_offset:105*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
fcsr_val: 32 */
TEST_FPSR_OP(fcvt.s.d, f31, f30, dyn, 32, 0, x3, 105*FLEN/8, x4, x1, x2)
#endif
RVTEST_CODE_END
RVMODEL_HALT
RVTEST_DATA_BEGIN
.align 4
rvtest_data:
.word 0xbabecafe
.word 0xabecafeb
.word 0xbecafeba
.word 0xecafebab
test_dataset_0:
NAN_BOXED(0,64,FLEN)
NAN_BOXED(0,64,FLEN)
NAN_BOXED(0,64,FLEN)
NAN_BOXED(0,64,FLEN)
NAN_BOXED(0,64,FLEN)
NAN_BOXED(4576918229304087675,64,FLEN)
NAN_BOXED(4576918229304087675,64,FLEN)
NAN_BOXED(4576918229304087675,64,FLEN)
NAN_BOXED(4576918229304087675,64,FLEN)
NAN_BOXED(4576918229304087675,64,FLEN)
NAN_BOXED(4591870180066957722,64,FLEN)
NAN_BOXED(4591870180066957722,64,FLEN)
NAN_BOXED(4591870180066957722,64,FLEN)
NAN_BOXED(4591870180066957722,64,FLEN)
NAN_BOXED(4591870180066957722,64,FLEN)
NAN_BOXED(4592590756007337001,64,FLEN)
NAN_BOXED(4592590756007337001,64,FLEN)
NAN_BOXED(4592590756007337001,64,FLEN)
NAN_BOXED(4592590756007337001,64,FLEN)
NAN_BOXED(4592590756007337001,64,FLEN)
NAN_BOXED(4606191626881995899,64,FLEN)
NAN_BOXED(4606191626881995899,64,FLEN)
NAN_BOXED(4606191626881995899,64,FLEN)
NAN_BOXED(4606191626881995899,64,FLEN)
NAN_BOXED(4606191626881995899,64,FLEN)
NAN_BOXED(4606281698874543309,64,FLEN)
NAN_BOXED(4606281698874543309,64,FLEN)
NAN_BOXED(4606281698874543309,64,FLEN)
NAN_BOXED(4606281698874543309,64,FLEN)
NAN_BOXED(4606281698874543309,64,FLEN)
NAN_BOXED(4607092346807469998,64,FLEN)
NAN_BOXED(4607092346807469998,64,FLEN)
NAN_BOXED(4607092346807469998,64,FLEN)
NAN_BOXED(4607092346807469998,64,FLEN)
NAN_BOXED(4607092346807469998,64,FLEN)
NAN_BOXED(4607182418800017408,64,FLEN)
NAN_BOXED(4607182418800017408,64,FLEN)
NAN_BOXED(4607182418800017408,64,FLEN)
NAN_BOXED(4607182418800017408,64,FLEN)
NAN_BOXED(4607182418800017408,64,FLEN)
NAN_BOXED(4607227454796291113,64,FLEN)
NAN_BOXED(4607227454796291113,64,FLEN)
NAN_BOXED(4607227454796291113,64,FLEN)
NAN_BOXED(4607227454796291113,64,FLEN)
NAN_BOXED(4607227454796291113,64,FLEN)
NAN_BOXED(4607632778762754458,64,FLEN)
NAN_BOXED(4607632778762754458,64,FLEN)
NAN_BOXED(4607632778762754458,64,FLEN)
NAN_BOXED(4607632778762754458,64,FLEN)
NAN_BOXED(4607632778762754458,64,FLEN)
NAN_BOXED(4607677814759028163,64,FLEN)
NAN_BOXED(4607677814759028163,64,FLEN)
NAN_BOXED(4607677814759028163,64,FLEN)
NAN_BOXED(4607677814759028163,64,FLEN)
NAN_BOXED(4607677814759028163,64,FLEN)
NAN_BOXED(13800290266158863483,64,FLEN)
NAN_BOXED(13800290266158863483,64,FLEN)
NAN_BOXED(13800290266158863483,64,FLEN)
NAN_BOXED(13800290266158863483,64,FLEN)
NAN_BOXED(13800290266158863483,64,FLEN)
NAN_BOXED(13815242216921733530,64,FLEN)
NAN_BOXED(13815242216921733530,64,FLEN)
NAN_BOXED(13815242216921733530,64,FLEN)
NAN_BOXED(13815242216921733530,64,FLEN)
NAN_BOXED(13815242216921733530,64,FLEN)
NAN_BOXED(13815962792862112809,64,FLEN)
NAN_BOXED(13815962792862112809,64,FLEN)
NAN_BOXED(13815962792862112809,64,FLEN)
NAN_BOXED(13815962792862112809,64,FLEN)
NAN_BOXED(13815962792862112809,64,FLEN)
NAN_BOXED(13829563663736771707,64,FLEN)
NAN_BOXED(13829563663736771707,64,FLEN)
NAN_BOXED(13829563663736771707,64,FLEN)
NAN_BOXED(13829563663736771707,64,FLEN)
NAN_BOXED(13829563663736771707,64,FLEN)
NAN_BOXED(13829653735729319117,64,FLEN)
NAN_BOXED(13829653735729319117,64,FLEN)
NAN_BOXED(13829653735729319117,64,FLEN)
NAN_BOXED(13829653735729319117,64,FLEN)
NAN_BOXED(13829653735729319117,64,FLEN)
NAN_BOXED(13830464383662245806,64,FLEN)
NAN_BOXED(13830464383662245806,64,FLEN)
NAN_BOXED(13830464383662245806,64,FLEN)
NAN_BOXED(13830464383662245806,64,FLEN)
NAN_BOXED(13830464383662245806,64,FLEN)
NAN_BOXED(13830554455654793216,64,FLEN)
NAN_BOXED(13830554455654793216,64,FLEN)
NAN_BOXED(13830554455654793216,64,FLEN)
NAN_BOXED(13830554455654793216,64,FLEN)
NAN_BOXED(13830554455654793216,64,FLEN)
NAN_BOXED(13830599491651066921,64,FLEN)
NAN_BOXED(13830599491651066921,64,FLEN)
NAN_BOXED(13830599491651066921,64,FLEN)
NAN_BOXED(13830599491651066921,64,FLEN)
NAN_BOXED(13830599491651066921,64,FLEN)
NAN_BOXED(13831004815617530266,64,FLEN)
NAN_BOXED(13831004815617530266,64,FLEN)
NAN_BOXED(13831004815617530266,64,FLEN)
NAN_BOXED(13831004815617530266,64,FLEN)
NAN_BOXED(13831004815617530266,64,FLEN)
NAN_BOXED(13831049851613803971,64,FLEN)
NAN_BOXED(13831049851613803971,64,FLEN)
NAN_BOXED(13831049851613803971,64,FLEN)
NAN_BOXED(13831049851613803971,64,FLEN)
NAN_BOXED(13831049851613803971,64,FLEN)
NAN_BOXED(0,64,FLEN)
RVTEST_DATA_END
RVMODEL_DATA_BEGIN
rvtest_sig_begin:
sig_begin_canary:
CANARY;
signature_x1_0:
.fill 0*((SIGALIGN)/4),4,0xdeadbeef
signature_x1_1:
.fill 212*((SIGALIGN)/4),4,0xdeadbeef
#ifdef rvtest_mtrap_routine
tsig_begin_canary:
CANARY;
tsig_begin_canary:
CANARY;
mtrap_sigptr:
.fill 64*(XLEN/32),4,0xdeadbeef
tsig_end_canary:
CANARY;
tsig_end_canary:
CANARY;
#endif
#ifdef rvtest_gpr_save
gpr_save:
.fill 32*XLEN/32,4,0xdeadbeef
#endif
sig_end_canary:
CANARY;
rvtest_sig_end:
RVMODEL_DATA_END

356
vendor/riscv-arch-tests/riscv-test-suite/rv32i_m/D/src/fcvt.s.d_b27-01.S vendored
View file

@ -1,356 +0,0 @@
// -----------
// This file was generated by riscv_ctg (https://github.com/riscv-software-src/riscv-ctg)
// version : 0.7.1
// timestamp : Fri Jun 17 14:03:33 2022 GMT
// usage : riscv_ctg \
// -- cgf // --cgf /scratch/pawan/work/normalised/RV32D/fcvt.s.d.cgf \
\
// -- xlen 32 \
// --randomize \
// -----------
//
// -----------
// Copyright (c) 2020. RISC-V International. All rights reserved.
// SPDX-License-Identifier: BSD-3-Clause
// -----------
//
// This assembly file tests the fcvt.s.d instruction of the RISC-V RV32FD_Zicsr,RV64FD_Zicsr extension for the fcvt.s.d_b27 covergroup.
//
#include "model_test.h"
#include "arch_test.h"
RVTEST_ISA("RV32IFD_Zicsr,RV64IFD_Zicsr")
.section .text.init
.org 0x80
.globl rvtest_entry_point
rvtest_entry_point:
RVMODEL_BOOT
RVTEST_CODE_BEGIN
#ifdef TEST_CASE_1
RVTEST_CASE(0,"//check ISA:=regex(.*I.*D.*);def TEST_CASE_1=True;",fcvt.s.d_b27)
RVTEST_FP_ENABLE()
RVTEST_VALBASEUPD(x3,test_dataset_0)
RVTEST_SIGBASE(x1,signature_x1_1)
inst_0:
// rs1 != rd, rs1==f16, rd==f21,fs1 == 0 and fe1 == 0x7ff and fm1 == 0x0000000000001 and fcsr == 0x0 and rm_val == 7
/* opcode: fcvt.s.d ; op1:f16; dest:f21; op1val:0x7ff0000000000001; valaddr_reg:x3;
val_offset:0*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
fcsr_val: 0 */
TEST_FPSR_OP(fcvt.s.d, f21, f16, dyn, 0, 0, x3, 0*FLEN/8, x4, x1, x2)
inst_1:
// rs1 == rd, rs1==f4, rd==f4,fs1 == 0 and fe1 == 0x7ff and fm1 == 0x4aaaaaaaaaaaa and fcsr == 0x0 and rm_val == 7
/* opcode: fcvt.s.d ; op1:f4; dest:f4; op1val:0x7ff4aaaaaaaaaaaa; valaddr_reg:x3;
val_offset:1*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
fcsr_val: 0 */
TEST_FPSR_OP(fcvt.s.d, f4, f4, dyn, 0, 0, x3, 1*FLEN/8, x4, x1, x2)
inst_2:
// rs1==f2, rd==f13,fs1 == 0 and fe1 == 0x7ff and fm1 == 0x8000000000001 and fcsr == 0x0 and rm_val == 7
/* opcode: fcvt.s.d ; op1:f2; dest:f13; op1val:0x7ff8000000000001; valaddr_reg:x3;
val_offset:2*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
fcsr_val: 0 */
TEST_FPSR_OP(fcvt.s.d, f13, f2, dyn, 0, 0, x3, 2*FLEN/8, x4, x1, x2)
inst_3:
// rs1==f7, rd==f3,fs1 == 0 and fe1 == 0x7ff and fm1 == 0xc000000000001 and fcsr == 0x0 and rm_val == 7
/* opcode: fcvt.s.d ; op1:f7; dest:f3; op1val:0x7ffc000000000001; valaddr_reg:x3;
val_offset:3*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
fcsr_val: 0 */
TEST_FPSR_OP(fcvt.s.d, f3, f7, dyn, 0, 0, x3, 3*FLEN/8, x4, x1, x2)
inst_4:
// rs1==f25, rd==f5,fs1 == 1 and fe1 == 0x7ff and fm1 == 0x0000000000001 and fcsr == 0x0 and rm_val == 7
/* opcode: fcvt.s.d ; op1:f25; dest:f5; op1val:0xfff0000000000001; valaddr_reg:x3;
val_offset:4*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
fcsr_val: 0 */
TEST_FPSR_OP(fcvt.s.d, f5, f25, dyn, 0, 0, x3, 4*FLEN/8, x4, x1, x2)
inst_5:
// rs1==f6, rd==f20,fs1 == 1 and fe1 == 0x7ff and fm1 == 0x4aaaaaaaaaaaa and fcsr == 0x0 and rm_val == 7
/* opcode: fcvt.s.d ; op1:f6; dest:f20; op1val:0xfff4aaaaaaaaaaaa; valaddr_reg:x3;
val_offset:5*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
fcsr_val: 0 */
TEST_FPSR_OP(fcvt.s.d, f20, f6, dyn, 0, 0, x3, 5*FLEN/8, x4, x1, x2)
inst_6:
// rs1==f21, rd==f2,fs1 == 1 and fe1 == 0x7ff and fm1 == 0x8000000000001 and fcsr == 0x0 and rm_val == 7
/* opcode: fcvt.s.d ; op1:f21; dest:f2; op1val:0xfff8000000000001; valaddr_reg:x3;
val_offset:6*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
fcsr_val: 0 */
TEST_FPSR_OP(fcvt.s.d, f2, f21, dyn, 0, 0, x3, 6*FLEN/8, x4, x1, x2)
inst_7:
// rs1==f1, rd==f0,fs1 == 1 and fe1 == 0x7ff and fm1 == 0xc000000000001 and fcsr == 0x0 and rm_val == 7
/* opcode: fcvt.s.d ; op1:f1; dest:f0; op1val:0xfffc000000000001; valaddr_reg:x3;
val_offset:7*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
fcsr_val: 0 */
TEST_FPSR_OP(fcvt.s.d, f0, f1, dyn, 0, 0, x3, 7*FLEN/8, x4, x1, x2)
inst_8:
// rs1==f30, rd==f24,
/* opcode: fcvt.s.d ; op1:f30; dest:f24; op1val:0x0; valaddr_reg:x3;
val_offset:8*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
fcsr_val: 0 */
TEST_FPSR_OP(fcvt.s.d, f24, f30, dyn, 0, 0, x3, 8*FLEN/8, x4, x1, x2)
inst_9:
// rs1==f12, rd==f22,
/* opcode: fcvt.s.d ; op1:f12; dest:f22; op1val:0x0; valaddr_reg:x3;
val_offset:9*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
fcsr_val: 0 */
TEST_FPSR_OP(fcvt.s.d, f22, f12, dyn, 0, 0, x3, 9*FLEN/8, x4, x1, x2)
inst_10:
// rs1==f0, rd==f14,
/* opcode: fcvt.s.d ; op1:f0; dest:f14; op1val:0x0; valaddr_reg:x3;
val_offset:10*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
fcsr_val: 0 */
TEST_FPSR_OP(fcvt.s.d, f14, f0, dyn, 0, 0, x3, 10*FLEN/8, x4, x1, x2)
inst_11:
// rs1==f11, rd==f25,
/* opcode: fcvt.s.d ; op1:f11; dest:f25; op1val:0x0; valaddr_reg:x3;
val_offset:11*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
fcsr_val: 0 */
TEST_FPSR_OP(fcvt.s.d, f25, f11, dyn, 0, 0, x3, 11*FLEN/8, x4, x1, x2)
inst_12:
// rs1==f29, rd==f26,
/* opcode: fcvt.s.d ; op1:f29; dest:f26; op1val:0x0; valaddr_reg:x3;
val_offset:12*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
fcsr_val: 0 */
TEST_FPSR_OP(fcvt.s.d, f26, f29, dyn, 0, 0, x3, 12*FLEN/8, x4, x1, x2)
inst_13:
// rs1==f27, rd==f16,
/* opcode: fcvt.s.d ; op1:f27; dest:f16; op1val:0x0; valaddr_reg:x3;
val_offset:13*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
fcsr_val: 0 */
TEST_FPSR_OP(fcvt.s.d, f16, f27, dyn, 0, 0, x3, 13*FLEN/8, x4, x1, x2)
inst_14:
// rs1==f15, rd==f17,
/* opcode: fcvt.s.d ; op1:f15; dest:f17; op1val:0x0; valaddr_reg:x3;
val_offset:14*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
fcsr_val: 0 */
TEST_FPSR_OP(fcvt.s.d, f17, f15, dyn, 0, 0, x3, 14*FLEN/8, x4, x1, x2)
inst_15:
// rs1==f22, rd==f30,
/* opcode: fcvt.s.d ; op1:f22; dest:f30; op1val:0x0; valaddr_reg:x3;
val_offset:15*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
fcsr_val: 0 */
TEST_FPSR_OP(fcvt.s.d, f30, f22, dyn, 0, 0, x3, 15*FLEN/8, x4, x1, x2)
inst_16:
// rs1==f18, rd==f10,
/* opcode: fcvt.s.d ; op1:f18; dest:f10; op1val:0x0; valaddr_reg:x3;
val_offset:16*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
fcsr_val: 0 */
TEST_FPSR_OP(fcvt.s.d, f10, f18, dyn, 0, 0, x3, 16*FLEN/8, x4, x1, x2)
inst_17:
// rs1==f28, rd==f8,
/* opcode: fcvt.s.d ; op1:f28; dest:f8; op1val:0x0; valaddr_reg:x3;
val_offset:17*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
fcsr_val: 0 */
TEST_FPSR_OP(fcvt.s.d, f8, f28, dyn, 0, 0, x3, 17*FLEN/8, x4, x1, x2)
inst_18:
// rs1==f31, rd==f29,
/* opcode: fcvt.s.d ; op1:f31; dest:f29; op1val:0x0; valaddr_reg:x3;
val_offset:18*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
fcsr_val: 0 */
TEST_FPSR_OP(fcvt.s.d, f29, f31, dyn, 0, 0, x3, 18*FLEN/8, x4, x1, x2)
inst_19:
// rs1==f17, rd==f12,
/* opcode: fcvt.s.d ; op1:f17; dest:f12; op1val:0x0; valaddr_reg:x3;
val_offset:19*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
fcsr_val: 0 */
TEST_FPSR_OP(fcvt.s.d, f12, f17, dyn, 0, 0, x3, 19*FLEN/8, x4, x1, x2)
inst_20:
// rs1==f3, rd==f11,
/* opcode: fcvt.s.d ; op1:f3; dest:f11; op1val:0x0; valaddr_reg:x3;
val_offset:20*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
fcsr_val: 0 */
TEST_FPSR_OP(fcvt.s.d, f11, f3, dyn, 0, 0, x3, 20*FLEN/8, x4, x1, x2)
inst_21:
// rs1==f10, rd==f27,
/* opcode: fcvt.s.d ; op1:f10; dest:f27; op1val:0x0; valaddr_reg:x3;
val_offset:21*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
fcsr_val: 0 */
TEST_FPSR_OP(fcvt.s.d, f27, f10, dyn, 0, 0, x3, 21*FLEN/8, x4, x1, x2)
inst_22:
// rs1==f9, rd==f31,
/* opcode: fcvt.s.d ; op1:f9; dest:f31; op1val:0x0; valaddr_reg:x3;
val_offset:22*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
fcsr_val: 0 */
TEST_FPSR_OP(fcvt.s.d, f31, f9, dyn, 0, 0, x3, 22*FLEN/8, x4, x1, x2)
inst_23:
// rs1==f8, rd==f18,
/* opcode: fcvt.s.d ; op1:f8; dest:f18; op1val:0x0; valaddr_reg:x3;
val_offset:23*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
fcsr_val: 0 */
TEST_FPSR_OP(fcvt.s.d, f18, f8, dyn, 0, 0, x3, 23*FLEN/8, x4, x1, x2)
inst_24:
// rs1==f14, rd==f6,
/* opcode: fcvt.s.d ; op1:f14; dest:f6; op1val:0x0; valaddr_reg:x3;
val_offset:24*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
fcsr_val: 0 */
TEST_FPSR_OP(fcvt.s.d, f6, f14, dyn, 0, 0, x3, 24*FLEN/8, x4, x1, x2)
inst_25:
// rs1==f23, rd==f15,
/* opcode: fcvt.s.d ; op1:f23; dest:f15; op1val:0x0; valaddr_reg:x3;
val_offset:25*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
fcsr_val: 0 */
TEST_FPSR_OP(fcvt.s.d, f15, f23, dyn, 0, 0, x3, 25*FLEN/8, x4, x1, x2)
inst_26:
// rs1==f24, rd==f19,
/* opcode: fcvt.s.d ; op1:f24; dest:f19; op1val:0x0; valaddr_reg:x3;
val_offset:26*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
fcsr_val: 0 */
TEST_FPSR_OP(fcvt.s.d, f19, f24, dyn, 0, 0, x3, 26*FLEN/8, x4, x1, x2)
inst_27:
// rs1==f20, rd==f28,
/* opcode: fcvt.s.d ; op1:f20; dest:f28; op1val:0x0; valaddr_reg:x3;
val_offset:27*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
fcsr_val: 0 */
TEST_FPSR_OP(fcvt.s.d, f28, f20, dyn, 0, 0, x3, 27*FLEN/8, x4, x1, x2)
inst_28:
// rs1==f19, rd==f23,
/* opcode: fcvt.s.d ; op1:f19; dest:f23; op1val:0x0; valaddr_reg:x3;
val_offset:28*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
fcsr_val: 0 */
TEST_FPSR_OP(fcvt.s.d, f23, f19, dyn, 0, 0, x3, 28*FLEN/8, x4, x1, x2)
inst_29:
// rs1==f5, rd==f9,
/* opcode: fcvt.s.d ; op1:f5; dest:f9; op1val:0x0; valaddr_reg:x3;
val_offset:29*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
fcsr_val: 0 */
TEST_FPSR_OP(fcvt.s.d, f9, f5, dyn, 0, 0, x3, 29*FLEN/8, x4, x1, x2)
inst_30:
// rs1==f26, rd==f7,
/* opcode: fcvt.s.d ; op1:f26; dest:f7; op1val:0x0; valaddr_reg:x3;
val_offset:30*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
fcsr_val: 0 */
TEST_FPSR_OP(fcvt.s.d, f7, f26, dyn, 0, 0, x3, 30*FLEN/8, x4, x1, x2)
inst_31:
// rs1==f13, rd==f1,
/* opcode: fcvt.s.d ; op1:f13; dest:f1; op1val:0x0; valaddr_reg:x3;
val_offset:31*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
fcsr_val: 0 */
TEST_FPSR_OP(fcvt.s.d, f1, f13, dyn, 0, 0, x3, 31*FLEN/8, x4, x1, x2)
inst_32:
// fs1 == 0 and fe1 == 0x7ff and fm1 == 0x4aaaaaaaaaaaa and fcsr == 0x0 and rm_val == 7
/* opcode: fcvt.s.d ; op1:f30; dest:f31; op1val:0x7ff4aaaaaaaaaaaa; valaddr_reg:x3;
val_offset:32*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
fcsr_val: 0 */
TEST_FPSR_OP(fcvt.s.d, f31, f30, dyn, 0, 0, x3, 32*FLEN/8, x4, x1, x2)
#endif
RVTEST_CODE_END
RVMODEL_HALT
RVTEST_DATA_BEGIN
.align 4
rvtest_data:
.word 0xbabecafe
.word 0xabecafeb
.word 0xbecafeba
.word 0xecafebab
test_dataset_0:
NAN_BOXED(9218868437227405313,64,FLEN)
NAN_BOXED(9220181987118721706,64,FLEN)
NAN_BOXED(9221120237041090561,64,FLEN)
NAN_BOXED(9222246136947933185,64,FLEN)
NAN_BOXED(18442240474082181121,64,FLEN)
NAN_BOXED(18443554023973497514,64,FLEN)
NAN_BOXED(18444492273895866369,64,FLEN)
NAN_BOXED(18445618173802708993,64,FLEN)
NAN_BOXED(0,64,FLEN)
NAN_BOXED(0,64,FLEN)
NAN_BOXED(0,64,FLEN)
NAN_BOXED(0,64,FLEN)
NAN_BOXED(0,64,FLEN)
NAN_BOXED(0,64,FLEN)
NAN_BOXED(0,64,FLEN)
NAN_BOXED(0,64,FLEN)
NAN_BOXED(0,64,FLEN)
NAN_BOXED(0,64,FLEN)
NAN_BOXED(0,64,FLEN)
NAN_BOXED(0,64,FLEN)
NAN_BOXED(0,64,FLEN)
NAN_BOXED(0,64,FLEN)
NAN_BOXED(0,64,FLEN)
NAN_BOXED(0,64,FLEN)
NAN_BOXED(0,64,FLEN)
NAN_BOXED(0,64,FLEN)
NAN_BOXED(0,64,FLEN)
NAN_BOXED(0,64,FLEN)
NAN_BOXED(0,64,FLEN)
NAN_BOXED(0,64,FLEN)
NAN_BOXED(0,64,FLEN)
NAN_BOXED(0,64,FLEN)
NAN_BOXED(9220181987118721706,64,FLEN)
RVTEST_DATA_END
RVMODEL_DATA_BEGIN
rvtest_sig_begin:
sig_begin_canary:
CANARY;
signature_x1_0:
.fill 0*((SIGALIGN)/4),4,0xdeadbeef
signature_x1_1:
.fill 66*((SIGALIGN)/4),4,0xdeadbeef
#ifdef rvtest_mtrap_routine
tsig_begin_canary:
CANARY;
tsig_begin_canary:
CANARY;
mtrap_sigptr:
.fill 64*(XLEN/32),4,0xdeadbeef
tsig_end_canary:
CANARY;
tsig_end_canary:
CANARY;
#endif
#ifdef rvtest_gpr_save
gpr_save:
.fill 32*XLEN/32,4,0xdeadbeef
#endif
sig_end_canary:
CANARY;
rvtest_sig_end:
RVMODEL_DATA_END

356
vendor/riscv-arch-tests/riscv-test-suite/rv32i_m/D/src/fcvt.s.d_b28-01.S vendored
View file

@ -1,356 +0,0 @@
// -----------
// This file was generated by riscv_ctg (https://github.com/riscv-software-src/riscv-ctg)
// version : 0.7.1
// timestamp : Fri Jun 17 14:03:33 2022 GMT
// usage : riscv_ctg \
// -- cgf // --cgf /scratch/pawan/work/normalised/RV32D/fcvt.s.d.cgf \
\
// -- xlen 32 \
// --randomize \
// -----------
//
// -----------
// Copyright (c) 2020. RISC-V International. All rights reserved.
// SPDX-License-Identifier: BSD-3-Clause
// -----------
//
// This assembly file tests the fcvt.s.d instruction of the RISC-V RV32FD_Zicsr,RV64FD_Zicsr extension for the fcvt.s.d_b28 covergroup.
//
#include "model_test.h"
#include "arch_test.h"
RVTEST_ISA("RV32IFD_Zicsr,RV64IFD_Zicsr")
.section .text.init
.org 0x80
.globl rvtest_entry_point
rvtest_entry_point:
RVMODEL_BOOT
RVTEST_CODE_BEGIN
#ifdef TEST_CASE_1
RVTEST_CASE(0,"//check ISA:=regex(.*I.*D.*);def TEST_CASE_1=True;",fcvt.s.d_b28)
RVTEST_FP_ENABLE()
RVTEST_VALBASEUPD(x3,test_dataset_0)
RVTEST_SIGBASE(x1,signature_x1_1)
inst_0:
// rs1 != rd, rs1==f29, rd==f9,fs1 == 0 and fe1 == 0x000 and fm1 == 0x0000000000000 and fcsr == 0x0 and rm_val == 7
/* opcode: fcvt.s.d ; op1:f29; dest:f9; op1val:0x0; valaddr_reg:x3;
val_offset:0*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
fcsr_val: 0 */
TEST_FPSR_OP(fcvt.s.d, f9, f29, dyn, 0, 0, x3, 0*FLEN/8, x4, x1, x2)
inst_1:
// rs1 == rd, rs1==f27, rd==f27,fs1 == 0 and fe1 == 0x3fe and fm1 == 0x248ee18215dfa and fcsr == 0x0 and rm_val == 7
/* opcode: fcvt.s.d ; op1:f27; dest:f27; op1val:0x3fe248ee18215dfa; valaddr_reg:x3;
val_offset:1*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
fcsr_val: 0 */
TEST_FPSR_OP(fcvt.s.d, f27, f27, dyn, 0, 0, x3, 1*FLEN/8, x4, x1, x2)
inst_2:
// rs1==f19, rd==f17,fs1 == 0 and fe1 == 0x3ff and fm1 == 0x0000000000000 and fcsr == 0x0 and rm_val == 7
/* opcode: fcvt.s.d ; op1:f19; dest:f17; op1val:0x3ff0000000000000; valaddr_reg:x3;
val_offset:2*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
fcsr_val: 0 */
TEST_FPSR_OP(fcvt.s.d, f17, f19, dyn, 0, 0, x3, 2*FLEN/8, x4, x1, x2)
inst_3:
// rs1==f22, rd==f30,fs1 == 0 and fe1 == 0x3ff and fm1 == 0x4000000000000 and fcsr == 0x0 and rm_val == 7
/* opcode: fcvt.s.d ; op1:f22; dest:f30; op1val:0x3ff4000000000000; valaddr_reg:x3;
val_offset:3*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
fcsr_val: 0 */
TEST_FPSR_OP(fcvt.s.d, f30, f22, dyn, 0, 0, x3, 3*FLEN/8, x4, x1, x2)
inst_4:
// rs1==f21, rd==f11,fs1 == 0 and fe1 == 0x3ff and fm1 == 0x8000000000000 and fcsr == 0x0 and rm_val == 7
/* opcode: fcvt.s.d ; op1:f21; dest:f11; op1val:0x3ff8000000000000; valaddr_reg:x3;
val_offset:4*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
fcsr_val: 0 */
TEST_FPSR_OP(fcvt.s.d, f11, f21, dyn, 0, 0, x3, 4*FLEN/8, x4, x1, x2)
inst_5:
// rs1==f12, rd==f13,fs1 == 0 and fe1 == 0x3ff and fm1 == 0xc000000000000 and fcsr == 0x0 and rm_val == 7
/* opcode: fcvt.s.d ; op1:f12; dest:f13; op1val:0x3ffc000000000000; valaddr_reg:x3;
val_offset:5*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
fcsr_val: 0 */
TEST_FPSR_OP(fcvt.s.d, f13, f12, dyn, 0, 0, x3, 5*FLEN/8, x4, x1, x2)
inst_6:
// rs1==f5, rd==f24,fs1 == 0 and fe1 == 0x400 and fm1 == 0x0000000000000 and fcsr == 0x0 and rm_val == 7
/* opcode: fcvt.s.d ; op1:f5; dest:f24; op1val:0x4000000000000000; valaddr_reg:x3;
val_offset:6*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
fcsr_val: 0 */
TEST_FPSR_OP(fcvt.s.d, f24, f5, dyn, 0, 0, x3, 6*FLEN/8, x4, x1, x2)
inst_7:
// rs1==f6, rd==f8,fs1 == 0 and fe1 == 0x400 and fm1 == 0x2000000000000 and fcsr == 0x0 and rm_val == 7
/* opcode: fcvt.s.d ; op1:f6; dest:f8; op1val:0x4002000000000000; valaddr_reg:x3;
val_offset:7*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
fcsr_val: 0 */
TEST_FPSR_OP(fcvt.s.d, f8, f6, dyn, 0, 0, x3, 7*FLEN/8, x4, x1, x2)
inst_8:
// rs1==f0, rd==f25,fs1 == 0 and fe1 == 0x400 and fm1 == 0x4000000000000 and fcsr == 0x0 and rm_val == 7
/* opcode: fcvt.s.d ; op1:f0; dest:f25; op1val:0x4004000000000000; valaddr_reg:x3;
val_offset:8*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
fcsr_val: 0 */
TEST_FPSR_OP(fcvt.s.d, f25, f0, dyn, 0, 0, x3, 8*FLEN/8, x4, x1, x2)
inst_9:
// rs1==f28, rd==f23,fs1 == 0 and fe1 == 0x400 and fm1 == 0x6000000000000 and fcsr == 0x0 and rm_val == 7
/* opcode: fcvt.s.d ; op1:f28; dest:f23; op1val:0x4006000000000000; valaddr_reg:x3;
val_offset:9*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
fcsr_val: 0 */
TEST_FPSR_OP(fcvt.s.d, f23, f28, dyn, 0, 0, x3, 9*FLEN/8, x4, x1, x2)
inst_10:
// rs1==f23, rd==f0,fs1 == 0 and fe1 == 0x43c and fm1 == 0xb72eb13dc494a and fcsr == 0x0 and rm_val == 7
/* opcode: fcvt.s.d ; op1:f23; dest:f0; op1val:0x43cb72eb13dc494a; valaddr_reg:x3;
val_offset:10*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
fcsr_val: 0 */
TEST_FPSR_OP(fcvt.s.d, f0, f23, dyn, 0, 0, x3, 10*FLEN/8, x4, x1, x2)
inst_11:
// rs1==f3, rd==f22,fs1 == 0 and fe1 == 0x43e and fm1 == 0x0000000000000 and fcsr == 0x0 and rm_val == 7
/* opcode: fcvt.s.d ; op1:f3; dest:f22; op1val:0x43e0000000000000; valaddr_reg:x3;
val_offset:11*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
fcsr_val: 0 */
TEST_FPSR_OP(fcvt.s.d, f22, f3, dyn, 0, 0, x3, 11*FLEN/8, x4, x1, x2)
inst_12:
// rs1==f17, rd==f10,fs1 == 0 and fe1 == 0x7ff and fm1 == 0x0000000000000 and fcsr == 0x0 and rm_val == 7
/* opcode: fcvt.s.d ; op1:f17; dest:f10; op1val:0x7ff0000000000000; valaddr_reg:x3;
val_offset:12*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
fcsr_val: 0 */
TEST_FPSR_OP(fcvt.s.d, f10, f17, dyn, 0, 0, x3, 12*FLEN/8, x4, x1, x2)
inst_13:
// rs1==f15, rd==f12,fs1 == 0 and fe1 == 0x7ff and fm1 == 0x0000000000001 and fcsr == 0x0 and rm_val == 7
/* opcode: fcvt.s.d ; op1:f15; dest:f12; op1val:0x7ff0000000000001; valaddr_reg:x3;
val_offset:13*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
fcsr_val: 0 */
TEST_FPSR_OP(fcvt.s.d, f12, f15, dyn, 0, 0, x3, 13*FLEN/8, x4, x1, x2)
inst_14:
// rs1==f31, rd==f5,fs1 == 0 and fe1 == 0x7ff and fm1 == 0x8000000000001 and fcsr == 0x0 and rm_val == 7
/* opcode: fcvt.s.d ; op1:f31; dest:f5; op1val:0x7ff8000000000001; valaddr_reg:x3;
val_offset:14*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
fcsr_val: 0 */
TEST_FPSR_OP(fcvt.s.d, f5, f31, dyn, 0, 0, x3, 14*FLEN/8, x4, x1, x2)
inst_15:
// rs1==f30, rd==f19,fs1 == 1 and fe1 == 0x000 and fm1 == 0x0000000000000 and fcsr == 0x0 and rm_val == 7
/* opcode: fcvt.s.d ; op1:f30; dest:f19; op1val:0x8000000000000000; valaddr_reg:x3;
val_offset:15*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
fcsr_val: 0 */
TEST_FPSR_OP(fcvt.s.d, f19, f30, dyn, 0, 0, x3, 15*FLEN/8, x4, x1, x2)
inst_16:
// rs1==f14, rd==f29,fs1 == 1 and fe1 == 0x3f8 and fm1 == 0x0000000000000 and fcsr == 0x0 and rm_val == 7
/* opcode: fcvt.s.d ; op1:f14; dest:f29; op1val:0xbf80000000000000; valaddr_reg:x3;
val_offset:16*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
fcsr_val: 0 */
TEST_FPSR_OP(fcvt.s.d, f29, f14, dyn, 0, 0, x3, 16*FLEN/8, x4, x1, x2)
inst_17:
// rs1==f24, rd==f26,fs1 == 1 and fe1 == 0x3fd and fm1 == 0xb008d57e19f88 and fcsr == 0x0 and rm_val == 7
/* opcode: fcvt.s.d ; op1:f24; dest:f26; op1val:0xbfdb008d57e19f88; valaddr_reg:x3;
val_offset:17*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
fcsr_val: 0 */
TEST_FPSR_OP(fcvt.s.d, f26, f24, dyn, 0, 0, x3, 17*FLEN/8, x4, x1, x2)
inst_18:
// rs1==f11, rd==f4,fs1 == 1 and fe1 == 0x3ff and fm1 == 0x4000000000000 and fcsr == 0x0 and rm_val == 7
/* opcode: fcvt.s.d ; op1:f11; dest:f4; op1val:0xbff4000000000000; valaddr_reg:x3;
val_offset:18*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
fcsr_val: 0 */
TEST_FPSR_OP(fcvt.s.d, f4, f11, dyn, 0, 0, x3, 18*FLEN/8, x4, x1, x2)
inst_19:
// rs1==f4, rd==f31,fs1 == 1 and fe1 == 0x3ff and fm1 == 0x8000000000000 and fcsr == 0x0 and rm_val == 7
/* opcode: fcvt.s.d ; op1:f4; dest:f31; op1val:0xbff8000000000000; valaddr_reg:x3;
val_offset:19*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
fcsr_val: 0 */
TEST_FPSR_OP(fcvt.s.d, f31, f4, dyn, 0, 0, x3, 19*FLEN/8, x4, x1, x2)
inst_20:
// rs1==f25, rd==f15,fs1 == 1 and fe1 == 0x3ff and fm1 == 0xc000000000000 and fcsr == 0x0 and rm_val == 7
/* opcode: fcvt.s.d ; op1:f25; dest:f15; op1val:0xbffc000000000000; valaddr_reg:x3;
val_offset:20*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
fcsr_val: 0 */
TEST_FPSR_OP(fcvt.s.d, f15, f25, dyn, 0, 0, x3, 20*FLEN/8, x4, x1, x2)
inst_21:
// rs1==f26, rd==f2,fs1 == 1 and fe1 == 0x400 and fm1 == 0x0000000000000 and fcsr == 0x0 and rm_val == 7
/* opcode: fcvt.s.d ; op1:f26; dest:f2; op1val:0xc000000000000000; valaddr_reg:x3;
val_offset:21*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
fcsr_val: 0 */
TEST_FPSR_OP(fcvt.s.d, f2, f26, dyn, 0, 0, x3, 21*FLEN/8, x4, x1, x2)
inst_22:
// rs1==f10, rd==f14,fs1 == 1 and fe1 == 0x400 and fm1 == 0x2000000000000 and fcsr == 0x0 and rm_val == 7
/* opcode: fcvt.s.d ; op1:f10; dest:f14; op1val:0xc002000000000000; valaddr_reg:x3;
val_offset:22*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
fcsr_val: 0 */
TEST_FPSR_OP(fcvt.s.d, f14, f10, dyn, 0, 0, x3, 22*FLEN/8, x4, x1, x2)
inst_23:
// rs1==f16, rd==f3,fs1 == 1 and fe1 == 0x400 and fm1 == 0x4000000000000 and fcsr == 0x0 and rm_val == 7
/* opcode: fcvt.s.d ; op1:f16; dest:f3; op1val:0xc004000000000000; valaddr_reg:x3;
val_offset:23*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
fcsr_val: 0 */
TEST_FPSR_OP(fcvt.s.d, f3, f16, dyn, 0, 0, x3, 23*FLEN/8, x4, x1, x2)
inst_24:
// rs1==f7, rd==f18,fs1 == 1 and fe1 == 0x400 and fm1 == 0x6000000000000 and fcsr == 0x0 and rm_val == 7
/* opcode: fcvt.s.d ; op1:f7; dest:f18; op1val:0xc006000000000000; valaddr_reg:x3;
val_offset:24*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
fcsr_val: 0 */
TEST_FPSR_OP(fcvt.s.d, f18, f7, dyn, 0, 0, x3, 24*FLEN/8, x4, x1, x2)
inst_25:
// rs1==f2, rd==f1,fs1 == 1 and fe1 == 0x43d and fm1 == 0x967a4ae26514c and fcsr == 0x0 and rm_val == 7
/* opcode: fcvt.s.d ; op1:f2; dest:f1; op1val:0xc3d967a4ae26514c; valaddr_reg:x3;
val_offset:25*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
fcsr_val: 0 */
TEST_FPSR_OP(fcvt.s.d, f1, f2, dyn, 0, 0, x3, 25*FLEN/8, x4, x1, x2)
inst_26:
// rs1==f18, rd==f28,fs1 == 1 and fe1 == 0x43e and fm1 == 0x0000000000000 and fcsr == 0x0 and rm_val == 7
/* opcode: fcvt.s.d ; op1:f18; dest:f28; op1val:0xc3e0000000000000; valaddr_reg:x3;
val_offset:26*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
fcsr_val: 0 */
TEST_FPSR_OP(fcvt.s.d, f28, f18, dyn, 0, 0, x3, 26*FLEN/8, x4, x1, x2)
inst_27:
// rs1==f1, rd==f7,fs1 == 1 and fe1 == 0x7ff and fm1 == 0x0000000000000 and fcsr == 0x0 and rm_val == 7
/* opcode: fcvt.s.d ; op1:f1; dest:f7; op1val:0xfff0000000000000; valaddr_reg:x3;
val_offset:27*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
fcsr_val: 0 */
TEST_FPSR_OP(fcvt.s.d, f7, f1, dyn, 0, 0, x3, 27*FLEN/8, x4, x1, x2)
inst_28:
// rs1==f13, rd==f20,
/* opcode: fcvt.s.d ; op1:f13; dest:f20; op1val:0x0; valaddr_reg:x3;
val_offset:28*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
fcsr_val: 0 */
TEST_FPSR_OP(fcvt.s.d, f20, f13, dyn, 0, 0, x3, 28*FLEN/8, x4, x1, x2)
inst_29:
// rs1==f8, rd==f16,
/* opcode: fcvt.s.d ; op1:f8; dest:f16; op1val:0x0; valaddr_reg:x3;
val_offset:29*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
fcsr_val: 0 */
TEST_FPSR_OP(fcvt.s.d, f16, f8, dyn, 0, 0, x3, 29*FLEN/8, x4, x1, x2)
inst_30:
// rs1==f20, rd==f21,
/* opcode: fcvt.s.d ; op1:f20; dest:f21; op1val:0x0; valaddr_reg:x3;
val_offset:30*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
fcsr_val: 0 */
TEST_FPSR_OP(fcvt.s.d, f21, f20, dyn, 0, 0, x3, 30*FLEN/8, x4, x1, x2)
inst_31:
// rs1==f9, rd==f6,
/* opcode: fcvt.s.d ; op1:f9; dest:f6; op1val:0x0; valaddr_reg:x3;
val_offset:31*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
fcsr_val: 0 */
TEST_FPSR_OP(fcvt.s.d, f6, f9, dyn, 0, 0, x3, 31*FLEN/8, x4, x1, x2)
inst_32:
// fs1 == 0 and fe1 == 0x3fe and fm1 == 0x248ee18215dfa and fcsr == 0x0 and rm_val == 7
/* opcode: fcvt.s.d ; op1:f30; dest:f31; op1val:0x3fe248ee18215dfa; valaddr_reg:x3;
val_offset:32*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
fcsr_val: 0 */
TEST_FPSR_OP(fcvt.s.d, f31, f30, dyn, 0, 0, x3, 32*FLEN/8, x4, x1, x2)
#endif
RVTEST_CODE_END
RVMODEL_HALT
RVTEST_DATA_BEGIN
.align 4
rvtest_data:
.word 0xbabecafe
.word 0xabecafeb
.word 0xbecafeba
.word 0xecafebab
test_dataset_0:
NAN_BOXED(0,64,FLEN)
NAN_BOXED(4603321956570324474,64,FLEN)
NAN_BOXED(4607182418800017408,64,FLEN)
NAN_BOXED(4608308318706860032,64,FLEN)
NAN_BOXED(4609434218613702656,64,FLEN)
NAN_BOXED(4610560118520545280,64,FLEN)
NAN_BOXED(4611686018427387904,64,FLEN)
NAN_BOXED(4612248968380809216,64,FLEN)
NAN_BOXED(4612811918334230528,64,FLEN)
NAN_BOXED(4613374868287651840,64,FLEN)
NAN_BOXED(4885124574789519690,64,FLEN)
NAN_BOXED(4890909195324358656,64,FLEN)
NAN_BOXED(9218868437227405312,64,FLEN)
NAN_BOXED(9218868437227405313,64,FLEN)
NAN_BOXED(9221120237041090561,64,FLEN)
NAN_BOXED(9223372036854775808,64,FLEN)
NAN_BOXED(13799029258263199744,64,FLEN)
NAN_BOXED(13824644088208662408,64,FLEN)
NAN_BOXED(13831680355561635840,64,FLEN)
NAN_BOXED(13832806255468478464,64,FLEN)
NAN_BOXED(13833932155375321088,64,FLEN)
NAN_BOXED(13835058055282163712,64,FLEN)
NAN_BOXED(13835621005235585024,64,FLEN)
NAN_BOXED(13836183955189006336,64,FLEN)
NAN_BOXED(13836746905142427648,64,FLEN)
NAN_BOXED(14112424864336204108,64,FLEN)
NAN_BOXED(14114281232179134464,64,FLEN)
NAN_BOXED(18442240474082181120,64,FLEN)
NAN_BOXED(0,64,FLEN)
NAN_BOXED(0,64,FLEN)
NAN_BOXED(0,64,FLEN)
NAN_BOXED(0,64,FLEN)
NAN_BOXED(4603321956570324474,64,FLEN)
RVTEST_DATA_END
RVMODEL_DATA_BEGIN
rvtest_sig_begin:
sig_begin_canary:
CANARY;
signature_x1_0:
.fill 0*((SIGALIGN)/4),4,0xdeadbeef
signature_x1_1:
.fill 66*((SIGALIGN)/4),4,0xdeadbeef
#ifdef rvtest_mtrap_routine
tsig_begin_canary:
CANARY;
tsig_begin_canary:
CANARY;
mtrap_sigptr:
.fill 64*(XLEN/32),4,0xdeadbeef
tsig_end_canary:
CANARY;
tsig_end_canary:
CANARY;
#endif
#ifdef rvtest_gpr_save
gpr_save:
.fill 32*XLEN/32,4,0xdeadbeef
#endif
sig_end_canary:
CANARY;
rvtest_sig_end:
RVMODEL_DATA_END

740
vendor/riscv-arch-tests/riscv-test-suite/rv32i_m/D/src/fcvt.s.d_b29-01.S vendored
View file

@ -1,740 +0,0 @@
// -----------
// This file was generated by riscv_ctg (https://github.com/riscv-software-src/riscv-ctg)
// version : 0.7.1
// timestamp : Fri Jun 17 14:03:33 2022 GMT
// usage : riscv_ctg \
// -- cgf // --cgf /scratch/pawan/work/normalised/RV32D/fcvt.s.d.cgf \
\
// -- xlen 32 \
// --randomize \
// -----------
//
// -----------
// Copyright (c) 2020. RISC-V International. All rights reserved.
// SPDX-License-Identifier: BSD-3-Clause
// -----------
//
// This assembly file tests the fcvt.s.d instruction of the RISC-V RV32FD_Zicsr,RV64FD_Zicsr extension for the fcvt.s.d_b29 covergroup.
//
#include "model_test.h"
#include "arch_test.h"
RVTEST_ISA("RV32IFD_Zicsr,RV64IFD_Zicsr")
.section .text.init
.org 0x80
.globl rvtest_entry_point
rvtest_entry_point:
RVMODEL_BOOT
RVTEST_CODE_BEGIN
#ifdef TEST_CASE_1
RVTEST_CASE(0,"//check ISA:=regex(.*I.*D.*);def TEST_CASE_1=True;",fcvt.s.d_b29)
RVTEST_FP_ENABLE()
RVTEST_VALBASEUPD(x3,test_dataset_0)
RVTEST_SIGBASE(x1,signature_x1_1)
inst_0:
// rs1 != rd, rs1==f18, rd==f24,fs1 == 0 and fe1 == 0x3fc and fm1 == 0x08574923b8698 and fcsr == 0x0 and rm_val == 7
/* opcode: fcvt.s.d ; op1:f18; dest:f24; op1val:0x3fc08574923b8698; valaddr_reg:x3;
val_offset:0*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
fcsr_val: 0 */
TEST_FPSR_OP(fcvt.s.d, f24, f18, dyn, 0, 0, x3, 0*FLEN/8, x4, x1, x2)
inst_1:
// rs1 == rd, rs1==f1, rd==f1,fs1 == 0 and fe1 == 0x3fc and fm1 == 0x08574923b8698 and fcsr == 0x20 and rm_val == 7
/* opcode: fcvt.s.d ; op1:f1; dest:f1; op1val:0x3fc08574923b8698; valaddr_reg:x3;
val_offset:1*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
fcsr_val: 32 */
TEST_FPSR_OP(fcvt.s.d, f1, f1, dyn, 32, 0, x3, 1*FLEN/8, x4, x1, x2)
inst_2:
// rs1==f14, rd==f10,fs1 == 0 and fe1 == 0x3fc and fm1 == 0x08574923b8698 and fcsr == 0x40 and rm_val == 7
/* opcode: fcvt.s.d ; op1:f14; dest:f10; op1val:0x3fc08574923b8698; valaddr_reg:x3;
val_offset:2*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
fcsr_val: 64 */
TEST_FPSR_OP(fcvt.s.d, f10, f14, dyn, 64, 0, x3, 2*FLEN/8, x4, x1, x2)
inst_3:
// rs1==f9, rd==f0,fs1 == 0 and fe1 == 0x3fc and fm1 == 0x08574923b8698 and fcsr == 0x60 and rm_val == 7
/* opcode: fcvt.s.d ; op1:f9; dest:f0; op1val:0x3fc08574923b8698; valaddr_reg:x3;
val_offset:3*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
fcsr_val: 96 */
TEST_FPSR_OP(fcvt.s.d, f0, f9, dyn, 96, 0, x3, 3*FLEN/8, x4, x1, x2)
inst_4:
// rs1==f21, rd==f26,fs1 == 0 and fe1 == 0x3fc and fm1 == 0x08574923b8698 and fcsr == 0x80 and rm_val == 7
/* opcode: fcvt.s.d ; op1:f21; dest:f26; op1val:0x3fc08574923b8698; valaddr_reg:x3;
val_offset:4*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
fcsr_val: 128 */
TEST_FPSR_OP(fcvt.s.d, f26, f21, dyn, 128, 0, x3, 4*FLEN/8, x4, x1, x2)
inst_5:
// rs1==f27, rd==f23,fs1 == 0 and fe1 == 0x3fc and fm1 == 0x08574923b8699 and fcsr == 0x0 and rm_val == 7
/* opcode: fcvt.s.d ; op1:f27; dest:f23; op1val:0x3fc08574923b8699; valaddr_reg:x3;
val_offset:5*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
fcsr_val: 0 */
TEST_FPSR_OP(fcvt.s.d, f23, f27, dyn, 0, 0, x3, 5*FLEN/8, x4, x1, x2)
inst_6:
// rs1==f19, rd==f30,fs1 == 0 and fe1 == 0x3fc and fm1 == 0x08574923b8699 and fcsr == 0x20 and rm_val == 7
/* opcode: fcvt.s.d ; op1:f19; dest:f30; op1val:0x3fc08574923b8699; valaddr_reg:x3;
val_offset:6*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
fcsr_val: 32 */
TEST_FPSR_OP(fcvt.s.d, f30, f19, dyn, 32, 0, x3, 6*FLEN/8, x4, x1, x2)
inst_7:
// rs1==f13, rd==f8,fs1 == 0 and fe1 == 0x3fc and fm1 == 0x08574923b8699 and fcsr == 0x40 and rm_val == 7
/* opcode: fcvt.s.d ; op1:f13; dest:f8; op1val:0x3fc08574923b8699; valaddr_reg:x3;
val_offset:7*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
fcsr_val: 64 */
TEST_FPSR_OP(fcvt.s.d, f8, f13, dyn, 64, 0, x3, 7*FLEN/8, x4, x1, x2)
inst_8:
// rs1==f23, rd==f29,fs1 == 0 and fe1 == 0x3fc and fm1 == 0x08574923b8699 and fcsr == 0x60 and rm_val == 7
/* opcode: fcvt.s.d ; op1:f23; dest:f29; op1val:0x3fc08574923b8699; valaddr_reg:x3;
val_offset:8*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
fcsr_val: 96 */
TEST_FPSR_OP(fcvt.s.d, f29, f23, dyn, 96, 0, x3, 8*FLEN/8, x4, x1, x2)
inst_9:
// rs1==f10, rd==f20,fs1 == 0 and fe1 == 0x3fc and fm1 == 0x08574923b8699 and fcsr == 0x80 and rm_val == 7
/* opcode: fcvt.s.d ; op1:f10; dest:f20; op1val:0x3fc08574923b8699; valaddr_reg:x3;
val_offset:9*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
fcsr_val: 128 */
TEST_FPSR_OP(fcvt.s.d, f20, f10, dyn, 128, 0, x3, 9*FLEN/8, x4, x1, x2)
inst_10:
// rs1==f28, rd==f7,fs1 == 0 and fe1 == 0x3fc and fm1 == 0x08574923b869a and fcsr == 0x0 and rm_val == 7
/* opcode: fcvt.s.d ; op1:f28; dest:f7; op1val:0x3fc08574923b869a; valaddr_reg:x3;
val_offset:10*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
fcsr_val: 0 */
TEST_FPSR_OP(fcvt.s.d, f7, f28, dyn, 0, 0, x3, 10*FLEN/8, x4, x1, x2)
inst_11:
// rs1==f25, rd==f13,fs1 == 0 and fe1 == 0x3fc and fm1 == 0x08574923b869a and fcsr == 0x20 and rm_val == 7
/* opcode: fcvt.s.d ; op1:f25; dest:f13; op1val:0x3fc08574923b869a; valaddr_reg:x3;
val_offset:11*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
fcsr_val: 32 */
TEST_FPSR_OP(fcvt.s.d, f13, f25, dyn, 32, 0, x3, 11*FLEN/8, x4, x1, x2)
inst_12:
// rs1==f3, rd==f18,fs1 == 0 and fe1 == 0x3fc and fm1 == 0x08574923b869a and fcsr == 0x40 and rm_val == 7
/* opcode: fcvt.s.d ; op1:f3; dest:f18; op1val:0x3fc08574923b869a; valaddr_reg:x3;
val_offset:12*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
fcsr_val: 64 */
TEST_FPSR_OP(fcvt.s.d, f18, f3, dyn, 64, 0, x3, 12*FLEN/8, x4, x1, x2)
inst_13:
// rs1==f15, rd==f19,fs1 == 0 and fe1 == 0x3fc and fm1 == 0x08574923b869a and fcsr == 0x60 and rm_val == 7
/* opcode: fcvt.s.d ; op1:f15; dest:f19; op1val:0x3fc08574923b869a; valaddr_reg:x3;
val_offset:13*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
fcsr_val: 96 */
TEST_FPSR_OP(fcvt.s.d, f19, f15, dyn, 96, 0, x3, 13*FLEN/8, x4, x1, x2)
inst_14:
// rs1==f26, rd==f3,fs1 == 0 and fe1 == 0x3fc and fm1 == 0x08574923b869a and fcsr == 0x80 and rm_val == 7
/* opcode: fcvt.s.d ; op1:f26; dest:f3; op1val:0x3fc08574923b869a; valaddr_reg:x3;
val_offset:14*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
fcsr_val: 128 */
TEST_FPSR_OP(fcvt.s.d, f3, f26, dyn, 128, 0, x3, 14*FLEN/8, x4, x1, x2)
inst_15:
// rs1==f24, rd==f5,fs1 == 0 and fe1 == 0x3fc and fm1 == 0x08574923b869b and fcsr == 0x0 and rm_val == 7
/* opcode: fcvt.s.d ; op1:f24; dest:f5; op1val:0x3fc08574923b869b; valaddr_reg:x3;
val_offset:15*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
fcsr_val: 0 */
TEST_FPSR_OP(fcvt.s.d, f5, f24, dyn, 0, 0, x3, 15*FLEN/8, x4, x1, x2)
inst_16:
// rs1==f5, rd==f11,fs1 == 0 and fe1 == 0x3fc and fm1 == 0x08574923b869b and fcsr == 0x20 and rm_val == 7
/* opcode: fcvt.s.d ; op1:f5; dest:f11; op1val:0x3fc08574923b869b; valaddr_reg:x3;
val_offset:16*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
fcsr_val: 32 */
TEST_FPSR_OP(fcvt.s.d, f11, f5, dyn, 32, 0, x3, 16*FLEN/8, x4, x1, x2)
inst_17:
// rs1==f31, rd==f17,fs1 == 0 and fe1 == 0x3fc and fm1 == 0x08574923b869b and fcsr == 0x40 and rm_val == 7
/* opcode: fcvt.s.d ; op1:f31; dest:f17; op1val:0x3fc08574923b869b; valaddr_reg:x3;
val_offset:17*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
fcsr_val: 64 */
TEST_FPSR_OP(fcvt.s.d, f17, f31, dyn, 64, 0, x3, 17*FLEN/8, x4, x1, x2)
inst_18:
// rs1==f30, rd==f6,fs1 == 0 and fe1 == 0x3fc and fm1 == 0x08574923b869b and fcsr == 0x60 and rm_val == 7
/* opcode: fcvt.s.d ; op1:f30; dest:f6; op1val:0x3fc08574923b869b; valaddr_reg:x3;
val_offset:18*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
fcsr_val: 96 */
TEST_FPSR_OP(fcvt.s.d, f6, f30, dyn, 96, 0, x3, 18*FLEN/8, x4, x1, x2)
inst_19:
// rs1==f2, rd==f25,fs1 == 0 and fe1 == 0x3fc and fm1 == 0x08574923b869b and fcsr == 0x80 and rm_val == 7
/* opcode: fcvt.s.d ; op1:f2; dest:f25; op1val:0x3fc08574923b869b; valaddr_reg:x3;
val_offset:19*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
fcsr_val: 128 */
TEST_FPSR_OP(fcvt.s.d, f25, f2, dyn, 128, 0, x3, 19*FLEN/8, x4, x1, x2)
inst_20:
// rs1==f11, rd==f4,fs1 == 0 and fe1 == 0x3fc and fm1 == 0x08574923b869c and fcsr == 0x0 and rm_val == 7
/* opcode: fcvt.s.d ; op1:f11; dest:f4; op1val:0x3fc08574923b869c; valaddr_reg:x3;
val_offset:20*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
fcsr_val: 0 */
TEST_FPSR_OP(fcvt.s.d, f4, f11, dyn, 0, 0, x3, 20*FLEN/8, x4, x1, x2)
inst_21:
// rs1==f0, rd==f2,fs1 == 0 and fe1 == 0x3fc and fm1 == 0x08574923b869c and fcsr == 0x20 and rm_val == 7
/* opcode: fcvt.s.d ; op1:f0; dest:f2; op1val:0x3fc08574923b869c; valaddr_reg:x3;
val_offset:21*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
fcsr_val: 32 */
TEST_FPSR_OP(fcvt.s.d, f2, f0, dyn, 32, 0, x3, 21*FLEN/8, x4, x1, x2)
inst_22:
// rs1==f17, rd==f31,fs1 == 0 and fe1 == 0x3fc and fm1 == 0x08574923b869c and fcsr == 0x40 and rm_val == 7
/* opcode: fcvt.s.d ; op1:f17; dest:f31; op1val:0x3fc08574923b869c; valaddr_reg:x3;
val_offset:22*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
fcsr_val: 64 */
TEST_FPSR_OP(fcvt.s.d, f31, f17, dyn, 64, 0, x3, 22*FLEN/8, x4, x1, x2)
inst_23:
// rs1==f7, rd==f12,fs1 == 0 and fe1 == 0x3fc and fm1 == 0x08574923b869c and fcsr == 0x60 and rm_val == 7
/* opcode: fcvt.s.d ; op1:f7; dest:f12; op1val:0x3fc08574923b869c; valaddr_reg:x3;
val_offset:23*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
fcsr_val: 96 */
TEST_FPSR_OP(fcvt.s.d, f12, f7, dyn, 96, 0, x3, 23*FLEN/8, x4, x1, x2)
inst_24:
// rs1==f16, rd==f21,fs1 == 0 and fe1 == 0x3fc and fm1 == 0x08574923b869c and fcsr == 0x80 and rm_val == 7
/* opcode: fcvt.s.d ; op1:f16; dest:f21; op1val:0x3fc08574923b869c; valaddr_reg:x3;
val_offset:24*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
fcsr_val: 128 */
TEST_FPSR_OP(fcvt.s.d, f21, f16, dyn, 128, 0, x3, 24*FLEN/8, x4, x1, x2)
inst_25:
// rs1==f22, rd==f9,fs1 == 0 and fe1 == 0x3fc and fm1 == 0x08574923b869d and fcsr == 0x0 and rm_val == 7
/* opcode: fcvt.s.d ; op1:f22; dest:f9; op1val:0x3fc08574923b869d; valaddr_reg:x3;
val_offset:25*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
fcsr_val: 0 */
TEST_FPSR_OP(fcvt.s.d, f9, f22, dyn, 0, 0, x3, 25*FLEN/8, x4, x1, x2)
inst_26:
// rs1==f20, rd==f22,fs1 == 0 and fe1 == 0x3fc and fm1 == 0x08574923b869d and fcsr == 0x20 and rm_val == 7
/* opcode: fcvt.s.d ; op1:f20; dest:f22; op1val:0x3fc08574923b869d; valaddr_reg:x3;
val_offset:26*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
fcsr_val: 32 */
TEST_FPSR_OP(fcvt.s.d, f22, f20, dyn, 32, 0, x3, 26*FLEN/8, x4, x1, x2)
inst_27:
// rs1==f4, rd==f14,fs1 == 0 and fe1 == 0x3fc and fm1 == 0x08574923b869d and fcsr == 0x40 and rm_val == 7
/* opcode: fcvt.s.d ; op1:f4; dest:f14; op1val:0x3fc08574923b869d; valaddr_reg:x3;
val_offset:27*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
fcsr_val: 64 */
TEST_FPSR_OP(fcvt.s.d, f14, f4, dyn, 64, 0, x3, 27*FLEN/8, x4, x1, x2)
inst_28:
// rs1==f12, rd==f27,fs1 == 0 and fe1 == 0x3fc and fm1 == 0x08574923b869d and fcsr == 0x60 and rm_val == 7
/* opcode: fcvt.s.d ; op1:f12; dest:f27; op1val:0x3fc08574923b869d; valaddr_reg:x3;
val_offset:28*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
fcsr_val: 96 */
TEST_FPSR_OP(fcvt.s.d, f27, f12, dyn, 96, 0, x3, 28*FLEN/8, x4, x1, x2)
inst_29:
// rs1==f8, rd==f15,fs1 == 0 and fe1 == 0x3fc and fm1 == 0x08574923b869d and fcsr == 0x80 and rm_val == 7
/* opcode: fcvt.s.d ; op1:f8; dest:f15; op1val:0x3fc08574923b869d; valaddr_reg:x3;
val_offset:29*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
fcsr_val: 128 */
TEST_FPSR_OP(fcvt.s.d, f15, f8, dyn, 128, 0, x3, 29*FLEN/8, x4, x1, x2)
inst_30:
// rs1==f29, rd==f28,fs1 == 0 and fe1 == 0x3fc and fm1 == 0x08574923b869e and fcsr == 0x0 and rm_val == 7
/* opcode: fcvt.s.d ; op1:f29; dest:f28; op1val:0x3fc08574923b869e; valaddr_reg:x3;
val_offset:30*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
fcsr_val: 0 */
TEST_FPSR_OP(fcvt.s.d, f28, f29, dyn, 0, 0, x3, 30*FLEN/8, x4, x1, x2)
inst_31:
// rs1==f6, rd==f16,fs1 == 0 and fe1 == 0x3fc and fm1 == 0x08574923b869e and fcsr == 0x20 and rm_val == 7
/* opcode: fcvt.s.d ; op1:f6; dest:f16; op1val:0x3fc08574923b869e; valaddr_reg:x3;
val_offset:31*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
fcsr_val: 32 */
TEST_FPSR_OP(fcvt.s.d, f16, f6, dyn, 32, 0, x3, 31*FLEN/8, x4, x1, x2)
inst_32:
// fs1 == 0 and fe1 == 0x3fc and fm1 == 0x08574923b869e and fcsr == 0x40 and rm_val == 7
/* opcode: fcvt.s.d ; op1:f30; dest:f31; op1val:0x3fc08574923b869e; valaddr_reg:x3;
val_offset:32*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
fcsr_val: 64 */
TEST_FPSR_OP(fcvt.s.d, f31, f30, dyn, 64, 0, x3, 32*FLEN/8, x4, x1, x2)
inst_33:
// fs1 == 0 and fe1 == 0x3fc and fm1 == 0x08574923b869e and fcsr == 0x60 and rm_val == 7
/* opcode: fcvt.s.d ; op1:f30; dest:f31; op1val:0x3fc08574923b869e; valaddr_reg:x3;
val_offset:33*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
fcsr_val: 96 */
TEST_FPSR_OP(fcvt.s.d, f31, f30, dyn, 96, 0, x3, 33*FLEN/8, x4, x1, x2)
inst_34:
// fs1 == 0 and fe1 == 0x3fc and fm1 == 0x08574923b869e and fcsr == 0x80 and rm_val == 7
/* opcode: fcvt.s.d ; op1:f30; dest:f31; op1val:0x3fc08574923b869e; valaddr_reg:x3;
val_offset:34*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
fcsr_val: 128 */
TEST_FPSR_OP(fcvt.s.d, f31, f30, dyn, 128, 0, x3, 34*FLEN/8, x4, x1, x2)
inst_35:
// fs1 == 0 and fe1 == 0x3fc and fm1 == 0x08574923b869f and fcsr == 0x0 and rm_val == 7
/* opcode: fcvt.s.d ; op1:f30; dest:f31; op1val:0x3fc08574923b869f; valaddr_reg:x3;
val_offset:35*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
fcsr_val: 0 */
TEST_FPSR_OP(fcvt.s.d, f31, f30, dyn, 0, 0, x3, 35*FLEN/8, x4, x1, x2)
inst_36:
// fs1 == 0 and fe1 == 0x3fc and fm1 == 0x08574923b869f and fcsr == 0x20 and rm_val == 7
/* opcode: fcvt.s.d ; op1:f30; dest:f31; op1val:0x3fc08574923b869f; valaddr_reg:x3;
val_offset:36*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
fcsr_val: 32 */
TEST_FPSR_OP(fcvt.s.d, f31, f30, dyn, 32, 0, x3, 36*FLEN/8, x4, x1, x2)
inst_37:
// fs1 == 0 and fe1 == 0x3fc and fm1 == 0x08574923b869f and fcsr == 0x40 and rm_val == 7
/* opcode: fcvt.s.d ; op1:f30; dest:f31; op1val:0x3fc08574923b869f; valaddr_reg:x3;
val_offset:37*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
fcsr_val: 64 */
TEST_FPSR_OP(fcvt.s.d, f31, f30, dyn, 64, 0, x3, 37*FLEN/8, x4, x1, x2)
inst_38:
// fs1 == 0 and fe1 == 0x3fc and fm1 == 0x08574923b869f and fcsr == 0x60 and rm_val == 7
/* opcode: fcvt.s.d ; op1:f30; dest:f31; op1val:0x3fc08574923b869f; valaddr_reg:x3;
val_offset:38*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
fcsr_val: 96 */
TEST_FPSR_OP(fcvt.s.d, f31, f30, dyn, 96, 0, x3, 38*FLEN/8, x4, x1, x2)
inst_39:
// fs1 == 0 and fe1 == 0x3fc and fm1 == 0x08574923b869f and fcsr == 0x80 and rm_val == 7
/* opcode: fcvt.s.d ; op1:f30; dest:f31; op1val:0x3fc08574923b869f; valaddr_reg:x3;
val_offset:39*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
fcsr_val: 128 */
TEST_FPSR_OP(fcvt.s.d, f31, f30, dyn, 128, 0, x3, 39*FLEN/8, x4, x1, x2)
inst_40:
// fs1 == 1 and fe1 == 0x3fc and fm1 == 0x08574923b8698 and fcsr == 0x0 and rm_val == 7
/* opcode: fcvt.s.d ; op1:f30; dest:f31; op1val:0xbfc08574923b8698; valaddr_reg:x3;
val_offset:40*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
fcsr_val: 0 */
TEST_FPSR_OP(fcvt.s.d, f31, f30, dyn, 0, 0, x3, 40*FLEN/8, x4, x1, x2)
inst_41:
// fs1 == 1 and fe1 == 0x3fc and fm1 == 0x08574923b8698 and fcsr == 0x20 and rm_val == 7
/* opcode: fcvt.s.d ; op1:f30; dest:f31; op1val:0xbfc08574923b8698; valaddr_reg:x3;
val_offset:41*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
fcsr_val: 32 */
TEST_FPSR_OP(fcvt.s.d, f31, f30, dyn, 32, 0, x3, 41*FLEN/8, x4, x1, x2)
inst_42:
// fs1 == 1 and fe1 == 0x3fc and fm1 == 0x08574923b8698 and fcsr == 0x40 and rm_val == 7
/* opcode: fcvt.s.d ; op1:f30; dest:f31; op1val:0xbfc08574923b8698; valaddr_reg:x3;
val_offset:42*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
fcsr_val: 64 */
TEST_FPSR_OP(fcvt.s.d, f31, f30, dyn, 64, 0, x3, 42*FLEN/8, x4, x1, x2)
inst_43:
// fs1 == 1 and fe1 == 0x3fc and fm1 == 0x08574923b8698 and fcsr == 0x60 and rm_val == 7
/* opcode: fcvt.s.d ; op1:f30; dest:f31; op1val:0xbfc08574923b8698; valaddr_reg:x3;
val_offset:43*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
fcsr_val: 96 */
TEST_FPSR_OP(fcvt.s.d, f31, f30, dyn, 96, 0, x3, 43*FLEN/8, x4, x1, x2)
inst_44:
// fs1 == 1 and fe1 == 0x3fc and fm1 == 0x08574923b8698 and fcsr == 0x80 and rm_val == 7
/* opcode: fcvt.s.d ; op1:f30; dest:f31; op1val:0xbfc08574923b8698; valaddr_reg:x3;
val_offset:44*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
fcsr_val: 128 */
TEST_FPSR_OP(fcvt.s.d, f31, f30, dyn, 128, 0, x3, 44*FLEN/8, x4, x1, x2)
inst_45:
// fs1 == 1 and fe1 == 0x3fc and fm1 == 0x08574923b8699 and fcsr == 0x0 and rm_val == 7
/* opcode: fcvt.s.d ; op1:f30; dest:f31; op1val:0xbfc08574923b8699; valaddr_reg:x3;
val_offset:45*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
fcsr_val: 0 */
TEST_FPSR_OP(fcvt.s.d, f31, f30, dyn, 0, 0, x3, 45*FLEN/8, x4, x1, x2)
inst_46:
// fs1 == 1 and fe1 == 0x3fc and fm1 == 0x08574923b8699 and fcsr == 0x20 and rm_val == 7
/* opcode: fcvt.s.d ; op1:f30; dest:f31; op1val:0xbfc08574923b8699; valaddr_reg:x3;
val_offset:46*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
fcsr_val: 32 */
TEST_FPSR_OP(fcvt.s.d, f31, f30, dyn, 32, 0, x3, 46*FLEN/8, x4, x1, x2)
inst_47:
// fs1 == 1 and fe1 == 0x3fc and fm1 == 0x08574923b8699 and fcsr == 0x40 and rm_val == 7
/* opcode: fcvt.s.d ; op1:f30; dest:f31; op1val:0xbfc08574923b8699; valaddr_reg:x3;
val_offset:47*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
fcsr_val: 64 */
TEST_FPSR_OP(fcvt.s.d, f31, f30, dyn, 64, 0, x3, 47*FLEN/8, x4, x1, x2)
inst_48:
// fs1 == 1 and fe1 == 0x3fc and fm1 == 0x08574923b8699 and fcsr == 0x60 and rm_val == 7
/* opcode: fcvt.s.d ; op1:f30; dest:f31; op1val:0xbfc08574923b8699; valaddr_reg:x3;
val_offset:48*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
fcsr_val: 96 */
TEST_FPSR_OP(fcvt.s.d, f31, f30, dyn, 96, 0, x3, 48*FLEN/8, x4, x1, x2)
inst_49:
// fs1 == 1 and fe1 == 0x3fc and fm1 == 0x08574923b8699 and fcsr == 0x80 and rm_val == 7
/* opcode: fcvt.s.d ; op1:f30; dest:f31; op1val:0xbfc08574923b8699; valaddr_reg:x3;
val_offset:49*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
fcsr_val: 128 */
TEST_FPSR_OP(fcvt.s.d, f31, f30, dyn, 128, 0, x3, 49*FLEN/8, x4, x1, x2)
inst_50:
// fs1 == 1 and fe1 == 0x3fc and fm1 == 0x08574923b869a and fcsr == 0x0 and rm_val == 7
/* opcode: fcvt.s.d ; op1:f30; dest:f31; op1val:0xbfc08574923b869a; valaddr_reg:x3;
val_offset:50*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
fcsr_val: 0 */
TEST_FPSR_OP(fcvt.s.d, f31, f30, dyn, 0, 0, x3, 50*FLEN/8, x4, x1, x2)
inst_51:
// fs1 == 1 and fe1 == 0x3fc and fm1 == 0x08574923b869a and fcsr == 0x20 and rm_val == 7
/* opcode: fcvt.s.d ; op1:f30; dest:f31; op1val:0xbfc08574923b869a; valaddr_reg:x3;
val_offset:51*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
fcsr_val: 32 */
TEST_FPSR_OP(fcvt.s.d, f31, f30, dyn, 32, 0, x3, 51*FLEN/8, x4, x1, x2)
inst_52:
// fs1 == 1 and fe1 == 0x3fc and fm1 == 0x08574923b869a and fcsr == 0x40 and rm_val == 7
/* opcode: fcvt.s.d ; op1:f30; dest:f31; op1val:0xbfc08574923b869a; valaddr_reg:x3;
val_offset:52*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
fcsr_val: 64 */
TEST_FPSR_OP(fcvt.s.d, f31, f30, dyn, 64, 0, x3, 52*FLEN/8, x4, x1, x2)
inst_53:
// fs1 == 1 and fe1 == 0x3fc and fm1 == 0x08574923b869a and fcsr == 0x60 and rm_val == 7
/* opcode: fcvt.s.d ; op1:f30; dest:f31; op1val:0xbfc08574923b869a; valaddr_reg:x3;
val_offset:53*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
fcsr_val: 96 */
TEST_FPSR_OP(fcvt.s.d, f31, f30, dyn, 96, 0, x3, 53*FLEN/8, x4, x1, x2)
inst_54:
// fs1 == 1 and fe1 == 0x3fc and fm1 == 0x08574923b869a and fcsr == 0x80 and rm_val == 7
/* opcode: fcvt.s.d ; op1:f30; dest:f31; op1val:0xbfc08574923b869a; valaddr_reg:x3;
val_offset:54*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
fcsr_val: 128 */
TEST_FPSR_OP(fcvt.s.d, f31, f30, dyn, 128, 0, x3, 54*FLEN/8, x4, x1, x2)
inst_55:
// fs1 == 1 and fe1 == 0x3fc and fm1 == 0x08574923b869b and fcsr == 0x0 and rm_val == 7
/* opcode: fcvt.s.d ; op1:f30; dest:f31; op1val:0xbfc08574923b869b; valaddr_reg:x3;
val_offset:55*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
fcsr_val: 0 */
TEST_FPSR_OP(fcvt.s.d, f31, f30, dyn, 0, 0, x3, 55*FLEN/8, x4, x1, x2)
inst_56:
// fs1 == 1 and fe1 == 0x3fc and fm1 == 0x08574923b869b and fcsr == 0x20 and rm_val == 7
/* opcode: fcvt.s.d ; op1:f30; dest:f31; op1val:0xbfc08574923b869b; valaddr_reg:x3;
val_offset:56*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
fcsr_val: 32 */
TEST_FPSR_OP(fcvt.s.d, f31, f30, dyn, 32, 0, x3, 56*FLEN/8, x4, x1, x2)
inst_57:
// fs1 == 1 and fe1 == 0x3fc and fm1 == 0x08574923b869b and fcsr == 0x40 and rm_val == 7
/* opcode: fcvt.s.d ; op1:f30; dest:f31; op1val:0xbfc08574923b869b; valaddr_reg:x3;
val_offset:57*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
fcsr_val: 64 */
TEST_FPSR_OP(fcvt.s.d, f31, f30, dyn, 64, 0, x3, 57*FLEN/8, x4, x1, x2)
inst_58:
// fs1 == 1 and fe1 == 0x3fc and fm1 == 0x08574923b869b and fcsr == 0x60 and rm_val == 7
/* opcode: fcvt.s.d ; op1:f30; dest:f31; op1val:0xbfc08574923b869b; valaddr_reg:x3;
val_offset:58*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
fcsr_val: 96 */
TEST_FPSR_OP(fcvt.s.d, f31, f30, dyn, 96, 0, x3, 58*FLEN/8, x4, x1, x2)
inst_59:
// fs1 == 1 and fe1 == 0x3fc and fm1 == 0x08574923b869b and fcsr == 0x80 and rm_val == 7
/* opcode: fcvt.s.d ; op1:f30; dest:f31; op1val:0xbfc08574923b869b; valaddr_reg:x3;
val_offset:59*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
fcsr_val: 128 */
TEST_FPSR_OP(fcvt.s.d, f31, f30, dyn, 128, 0, x3, 59*FLEN/8, x4, x1, x2)
inst_60:
// fs1 == 1 and fe1 == 0x3fc and fm1 == 0x08574923b869c and fcsr == 0x0 and rm_val == 7
/* opcode: fcvt.s.d ; op1:f30; dest:f31; op1val:0xbfc08574923b869c; valaddr_reg:x3;
val_offset:60*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
fcsr_val: 0 */
TEST_FPSR_OP(fcvt.s.d, f31, f30, dyn, 0, 0, x3, 60*FLEN/8, x4, x1, x2)
inst_61:
// fs1 == 1 and fe1 == 0x3fc and fm1 == 0x08574923b869c and fcsr == 0x20 and rm_val == 7
/* opcode: fcvt.s.d ; op1:f30; dest:f31; op1val:0xbfc08574923b869c; valaddr_reg:x3;
val_offset:61*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
fcsr_val: 32 */
TEST_FPSR_OP(fcvt.s.d, f31, f30, dyn, 32, 0, x3, 61*FLEN/8, x4, x1, x2)
inst_62:
// fs1 == 1 and fe1 == 0x3fc and fm1 == 0x08574923b869c and fcsr == 0x40 and rm_val == 7
/* opcode: fcvt.s.d ; op1:f30; dest:f31; op1val:0xbfc08574923b869c; valaddr_reg:x3;
val_offset:62*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
fcsr_val: 64 */
TEST_FPSR_OP(fcvt.s.d, f31, f30, dyn, 64, 0, x3, 62*FLEN/8, x4, x1, x2)
inst_63:
// fs1 == 1 and fe1 == 0x3fc and fm1 == 0x08574923b869c and fcsr == 0x60 and rm_val == 7
/* opcode: fcvt.s.d ; op1:f30; dest:f31; op1val:0xbfc08574923b869c; valaddr_reg:x3;
val_offset:63*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
fcsr_val: 96 */
TEST_FPSR_OP(fcvt.s.d, f31, f30, dyn, 96, 0, x3, 63*FLEN/8, x4, x1, x2)
inst_64:
// fs1 == 1 and fe1 == 0x3fc and fm1 == 0x08574923b869c and fcsr == 0x80 and rm_val == 7
/* opcode: fcvt.s.d ; op1:f30; dest:f31; op1val:0xbfc08574923b869c; valaddr_reg:x3;
val_offset:64*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
fcsr_val: 128 */
TEST_FPSR_OP(fcvt.s.d, f31, f30, dyn, 128, 0, x3, 64*FLEN/8, x4, x1, x2)
inst_65:
// fs1 == 1 and fe1 == 0x3fc and fm1 == 0x08574923b869d and fcsr == 0x0 and rm_val == 7
/* opcode: fcvt.s.d ; op1:f30; dest:f31; op1val:0xbfc08574923b869d; valaddr_reg:x3;
val_offset:65*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
fcsr_val: 0 */
TEST_FPSR_OP(fcvt.s.d, f31, f30, dyn, 0, 0, x3, 65*FLEN/8, x4, x1, x2)
inst_66:
// fs1 == 1 and fe1 == 0x3fc and fm1 == 0x08574923b869d and fcsr == 0x20 and rm_val == 7
/* opcode: fcvt.s.d ; op1:f30; dest:f31; op1val:0xbfc08574923b869d; valaddr_reg:x3;
val_offset:66*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
fcsr_val: 32 */
TEST_FPSR_OP(fcvt.s.d, f31, f30, dyn, 32, 0, x3, 66*FLEN/8, x4, x1, x2)
inst_67:
// fs1 == 1 and fe1 == 0x3fc and fm1 == 0x08574923b869d and fcsr == 0x40 and rm_val == 7
/* opcode: fcvt.s.d ; op1:f30; dest:f31; op1val:0xbfc08574923b869d; valaddr_reg:x3;
val_offset:67*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
fcsr_val: 64 */
TEST_FPSR_OP(fcvt.s.d, f31, f30, dyn, 64, 0, x3, 67*FLEN/8, x4, x1, x2)
inst_68:
// fs1 == 1 and fe1 == 0x3fc and fm1 == 0x08574923b869d and fcsr == 0x60 and rm_val == 7
/* opcode: fcvt.s.d ; op1:f30; dest:f31; op1val:0xbfc08574923b869d; valaddr_reg:x3;
val_offset:68*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
fcsr_val: 96 */
TEST_FPSR_OP(fcvt.s.d, f31, f30, dyn, 96, 0, x3, 68*FLEN/8, x4, x1, x2)
inst_69:
// fs1 == 1 and fe1 == 0x3fc and fm1 == 0x08574923b869d and fcsr == 0x80 and rm_val == 7
/* opcode: fcvt.s.d ; op1:f30; dest:f31; op1val:0xbfc08574923b869d; valaddr_reg:x3;
val_offset:69*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
fcsr_val: 128 */
TEST_FPSR_OP(fcvt.s.d, f31, f30, dyn, 128, 0, x3, 69*FLEN/8, x4, x1, x2)
inst_70:
// fs1 == 1 and fe1 == 0x3fc and fm1 == 0x08574923b869e and fcsr == 0x0 and rm_val == 7
/* opcode: fcvt.s.d ; op1:f30; dest:f31; op1val:0xbfc08574923b869e; valaddr_reg:x3;
val_offset:70*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
fcsr_val: 0 */
TEST_FPSR_OP(fcvt.s.d, f31, f30, dyn, 0, 0, x3, 70*FLEN/8, x4, x1, x2)
inst_71:
// fs1 == 1 and fe1 == 0x3fc and fm1 == 0x08574923b869e and fcsr == 0x20 and rm_val == 7
/* opcode: fcvt.s.d ; op1:f30; dest:f31; op1val:0xbfc08574923b869e; valaddr_reg:x3;
val_offset:71*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
fcsr_val: 32 */
TEST_FPSR_OP(fcvt.s.d, f31, f30, dyn, 32, 0, x3, 71*FLEN/8, x4, x1, x2)
inst_72:
// fs1 == 1 and fe1 == 0x3fc and fm1 == 0x08574923b869e and fcsr == 0x40 and rm_val == 7
/* opcode: fcvt.s.d ; op1:f30; dest:f31; op1val:0xbfc08574923b869e; valaddr_reg:x3;
val_offset:72*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
fcsr_val: 64 */
TEST_FPSR_OP(fcvt.s.d, f31, f30, dyn, 64, 0, x3, 72*FLEN/8, x4, x1, x2)
inst_73:
// fs1 == 1 and fe1 == 0x3fc and fm1 == 0x08574923b869e and fcsr == 0x60 and rm_val == 7
/* opcode: fcvt.s.d ; op1:f30; dest:f31; op1val:0xbfc08574923b869e; valaddr_reg:x3;
val_offset:73*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
fcsr_val: 96 */
TEST_FPSR_OP(fcvt.s.d, f31, f30, dyn, 96, 0, x3, 73*FLEN/8, x4, x1, x2)
inst_74:
// fs1 == 1 and fe1 == 0x3fc and fm1 == 0x08574923b869e and fcsr == 0x80 and rm_val == 7
/* opcode: fcvt.s.d ; op1:f30; dest:f31; op1val:0xbfc08574923b869e; valaddr_reg:x3;
val_offset:74*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
fcsr_val: 128 */
TEST_FPSR_OP(fcvt.s.d, f31, f30, dyn, 128, 0, x3, 74*FLEN/8, x4, x1, x2)
inst_75:
// fs1 == 1 and fe1 == 0x3fc and fm1 == 0x08574923b869f and fcsr == 0x0 and rm_val == 7
/* opcode: fcvt.s.d ; op1:f30; dest:f31; op1val:0xbfc08574923b869f; valaddr_reg:x3;
val_offset:75*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
fcsr_val: 0 */
TEST_FPSR_OP(fcvt.s.d, f31, f30, dyn, 0, 0, x3, 75*FLEN/8, x4, x1, x2)
inst_76:
// fs1 == 1 and fe1 == 0x3fc and fm1 == 0x08574923b869f and fcsr == 0x20 and rm_val == 7
/* opcode: fcvt.s.d ; op1:f30; dest:f31; op1val:0xbfc08574923b869f; valaddr_reg:x3;
val_offset:76*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
fcsr_val: 32 */
TEST_FPSR_OP(fcvt.s.d, f31, f30, dyn, 32, 0, x3, 76*FLEN/8, x4, x1, x2)
inst_77:
// fs1 == 1 and fe1 == 0x3fc and fm1 == 0x08574923b869f and fcsr == 0x40 and rm_val == 7
/* opcode: fcvt.s.d ; op1:f30; dest:f31; op1val:0xbfc08574923b869f; valaddr_reg:x3;
val_offset:77*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
fcsr_val: 64 */
TEST_FPSR_OP(fcvt.s.d, f31, f30, dyn, 64, 0, x3, 77*FLEN/8, x4, x1, x2)
inst_78:
// fs1 == 1 and fe1 == 0x3fc and fm1 == 0x08574923b869f and fcsr == 0x60 and rm_val == 7
/* opcode: fcvt.s.d ; op1:f30; dest:f31; op1val:0xbfc08574923b869f; valaddr_reg:x3;
val_offset:78*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
fcsr_val: 96 */
TEST_FPSR_OP(fcvt.s.d, f31, f30, dyn, 96, 0, x3, 78*FLEN/8, x4, x1, x2)
inst_79:
// fs1 == 1 and fe1 == 0x3fc and fm1 == 0x08574923b869f and fcsr == 0x80 and rm_val == 7
/* opcode: fcvt.s.d ; op1:f30; dest:f31; op1val:0xbfc08574923b869f; valaddr_reg:x3;
val_offset:79*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
fcsr_val: 128 */
TEST_FPSR_OP(fcvt.s.d, f31, f30, dyn, 128, 0, x3, 79*FLEN/8, x4, x1, x2)
inst_80:
// fs1 == 0 and fe1 == 0x3fc and fm1 == 0x08574923b8698 and fcsr == 0x20 and rm_val == 7
/* opcode: fcvt.s.d ; op1:f30; dest:f31; op1val:0x3fc08574923b8698; valaddr_reg:x3;
val_offset:80*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
fcsr_val: 32 */
TEST_FPSR_OP(fcvt.s.d, f31, f30, dyn, 32, 0, x3, 80*FLEN/8, x4, x1, x2)
#endif
RVTEST_CODE_END
RVMODEL_HALT
RVTEST_DATA_BEGIN
.align 4
rvtest_data:
.word 0xbabecafe
.word 0xabecafeb
.word 0xbecafeba
.word 0xecafebab
test_dataset_0:
NAN_BOXED(4593818355633981080,64,FLEN)
NAN_BOXED(4593818355633981080,64,FLEN)
NAN_BOXED(4593818355633981080,64,FLEN)
NAN_BOXED(4593818355633981080,64,FLEN)
NAN_BOXED(4593818355633981080,64,FLEN)
NAN_BOXED(4593818355633981081,64,FLEN)
NAN_BOXED(4593818355633981081,64,FLEN)
NAN_BOXED(4593818355633981081,64,FLEN)
NAN_BOXED(4593818355633981081,64,FLEN)
NAN_BOXED(4593818355633981081,64,FLEN)
NAN_BOXED(4593818355633981082,64,FLEN)
NAN_BOXED(4593818355633981082,64,FLEN)
NAN_BOXED(4593818355633981082,64,FLEN)
NAN_BOXED(4593818355633981082,64,FLEN)
NAN_BOXED(4593818355633981082,64,FLEN)
NAN_BOXED(4593818355633981083,64,FLEN)
NAN_BOXED(4593818355633981083,64,FLEN)
NAN_BOXED(4593818355633981083,64,FLEN)
NAN_BOXED(4593818355633981083,64,FLEN)
NAN_BOXED(4593818355633981083,64,FLEN)
NAN_BOXED(4593818355633981084,64,FLEN)
NAN_BOXED(4593818355633981084,64,FLEN)
NAN_BOXED(4593818355633981084,64,FLEN)
NAN_BOXED(4593818355633981084,64,FLEN)
NAN_BOXED(4593818355633981084,64,FLEN)
NAN_BOXED(4593818355633981085,64,FLEN)
NAN_BOXED(4593818355633981085,64,FLEN)
NAN_BOXED(4593818355633981085,64,FLEN)
NAN_BOXED(4593818355633981085,64,FLEN)
NAN_BOXED(4593818355633981085,64,FLEN)
NAN_BOXED(4593818355633981086,64,FLEN)
NAN_BOXED(4593818355633981086,64,FLEN)
NAN_BOXED(4593818355633981086,64,FLEN)
NAN_BOXED(4593818355633981086,64,FLEN)
NAN_BOXED(4593818355633981086,64,FLEN)
NAN_BOXED(4593818355633981087,64,FLEN)
NAN_BOXED(4593818355633981087,64,FLEN)
NAN_BOXED(4593818355633981087,64,FLEN)
NAN_BOXED(4593818355633981087,64,FLEN)
NAN_BOXED(4593818355633981087,64,FLEN)
NAN_BOXED(13817190392488756888,64,FLEN)
NAN_BOXED(13817190392488756888,64,FLEN)
NAN_BOXED(13817190392488756888,64,FLEN)
NAN_BOXED(13817190392488756888,64,FLEN)
NAN_BOXED(13817190392488756888,64,FLEN)
NAN_BOXED(13817190392488756889,64,FLEN)
NAN_BOXED(13817190392488756889,64,FLEN)
NAN_BOXED(13817190392488756889,64,FLEN)
NAN_BOXED(13817190392488756889,64,FLEN)
NAN_BOXED(13817190392488756889,64,FLEN)
NAN_BOXED(13817190392488756890,64,FLEN)
NAN_BOXED(13817190392488756890,64,FLEN)
NAN_BOXED(13817190392488756890,64,FLEN)
NAN_BOXED(13817190392488756890,64,FLEN)
NAN_BOXED(13817190392488756890,64,FLEN)
NAN_BOXED(13817190392488756891,64,FLEN)
NAN_BOXED(13817190392488756891,64,FLEN)
NAN_BOXED(13817190392488756891,64,FLEN)
NAN_BOXED(13817190392488756891,64,FLEN)
NAN_BOXED(13817190392488756891,64,FLEN)
NAN_BOXED(13817190392488756892,64,FLEN)
NAN_BOXED(13817190392488756892,64,FLEN)
NAN_BOXED(13817190392488756892,64,FLEN)
NAN_BOXED(13817190392488756892,64,FLEN)
NAN_BOXED(13817190392488756892,64,FLEN)
NAN_BOXED(13817190392488756893,64,FLEN)
NAN_BOXED(13817190392488756893,64,FLEN)
NAN_BOXED(13817190392488756893,64,FLEN)
NAN_BOXED(13817190392488756893,64,FLEN)
NAN_BOXED(13817190392488756893,64,FLEN)
NAN_BOXED(13817190392488756894,64,FLEN)
NAN_BOXED(13817190392488756894,64,FLEN)
NAN_BOXED(13817190392488756894,64,FLEN)
NAN_BOXED(13817190392488756894,64,FLEN)
NAN_BOXED(13817190392488756894,64,FLEN)
NAN_BOXED(13817190392488756895,64,FLEN)
NAN_BOXED(13817190392488756895,64,FLEN)
NAN_BOXED(13817190392488756895,64,FLEN)
NAN_BOXED(13817190392488756895,64,FLEN)
NAN_BOXED(13817190392488756895,64,FLEN)
NAN_BOXED(4593818355633981080,64,FLEN)
RVTEST_DATA_END
RVMODEL_DATA_BEGIN
rvtest_sig_begin:
sig_begin_canary:
CANARY;
signature_x1_0:
.fill 0*((SIGALIGN)/4),4,0xdeadbeef
signature_x1_1:
.fill 162*((SIGALIGN)/4),4,0xdeadbeef
#ifdef rvtest_mtrap_routine
tsig_begin_canary:
CANARY;
tsig_begin_canary:
CANARY;
mtrap_sigptr:
.fill 64*(XLEN/32),4,0xdeadbeef
tsig_end_canary:
CANARY;
tsig_end_canary:
CANARY;
#endif
#ifdef rvtest_gpr_save
gpr_save:
.fill 32*XLEN/32,4,0xdeadbeef
#endif
sig_end_canary:
CANARY;
rvtest_sig_end:
RVMODEL_DATA_END

330
vendor/riscv-arch-tests/riscv-test-suite/rv32i_m/D/src/fcvt.w.d_b1-01.S vendored
View file

@ -1,330 +0,0 @@
// -----------
// This file was generated by riscv_ctg (https://github.com/riscv-software-src/riscv-ctg)
// version : 0.7.1
// timestamp : Fri Jun 17 14:03:36 2022 GMT
// usage : riscv_ctg \
// -- cgf // --cgf /scratch/pawan/work/normalised/RV32D/fcvt.w.d.cgf \
\
// -- xlen 32 \
// --randomize \
// -----------
//
// -----------
// Copyright (c) 2020. RISC-V International. All rights reserved.
// SPDX-License-Identifier: BSD-3-Clause
// -----------
//
// This assembly file tests the fcvt.w.d instruction of the RISC-V RV32FD_Zicsr,RV64FD_Zicsr extension for the fcvt.w.d_b1 covergroup.
//
#include "model_test.h"
#include "arch_test.h"
RVTEST_ISA("RV32IFD_Zicsr,RV64IFD_Zicsr")
.section .text.init
.org 0x80
.globl rvtest_entry_point
rvtest_entry_point:
RVMODEL_BOOT
RVTEST_CODE_BEGIN
#ifdef TEST_CASE_1
RVTEST_CASE(0,"//check ISA:=regex(.*I.*D.*);def TEST_CASE_1=True;",fcvt.w.d_b1)
RVTEST_FP_ENABLE()
RVTEST_VALBASEUPD(x11,test_dataset_0)
RVTEST_SIGBASE(x8,signature_x8_1)
inst_0:// rs1==f7, rd==x29,fs1 == 0 and fe1 == 0x000 and fm1 == 0x0000000000000 and fcsr == 0x0 and rm_val == 7
/* opcode: fcvt.w.d ; op1:f7; dest:x29; op1val:0x0; valaddr_reg:x11;
val_offset:0*FLEN/8; rmval:dyn; correctval:??; testreg:x9;
fcsr_val:0*/
TEST_FPID_OP(fcvt.w.d, x29, f7, dyn, 0, 0, x11, 0*FLEN/8, x17, x8, x9,FLREG)
inst_1:// rs1==f15, rd==x28,fs1 == 0 and fe1 == 0x000 and fm1 == 0x0000000000001 and fcsr == 0x0 and rm_val == 7
/* opcode: fcvt.w.d ; op1:f15; dest:x28; op1val:0x1; valaddr_reg:x11;
val_offset:1*FLEN/8; rmval:dyn; correctval:??; testreg:x9;
fcsr_val:0*/
TEST_FPID_OP(fcvt.w.d, x28, f15, dyn, 0, 0, x11, 1*FLEN/8, x17, x8, x9,FLREG)
inst_2:// rs1==f31, rd==x1,fs1 == 0 and fe1 == 0x000 and fm1 == 0x0000000000002 and fcsr == 0x0 and rm_val == 7
/* opcode: fcvt.w.d ; op1:f31; dest:x1; op1val:0x2; valaddr_reg:x11;
val_offset:2*FLEN/8; rmval:dyn; correctval:??; testreg:x9;
fcsr_val:0*/
TEST_FPID_OP(fcvt.w.d, x1, f31, dyn, 0, 0, x11, 2*FLEN/8, x17, x8, x9,FLREG)
inst_3:// rs1==f1, rd==x14,fs1 == 0 and fe1 == 0x000 and fm1 == 0xfffffffffffff and fcsr == 0x0 and rm_val == 7
/* opcode: fcvt.w.d ; op1:f1; dest:x14; op1val:0xfffffffffffff; valaddr_reg:x11;
val_offset:3*FLEN/8; rmval:dyn; correctval:??; testreg:x9;
fcsr_val:0*/
TEST_FPID_OP(fcvt.w.d, x14, f1, dyn, 0, 0, x11, 3*FLEN/8, x17, x8, x9,FLREG)
inst_4:// rs1==f2, rd==x22,fs1 == 0 and fe1 == 0x001 and fm1 == 0x0000000000000 and fcsr == 0x0 and rm_val == 7
/* opcode: fcvt.w.d ; op1:f2; dest:x22; op1val:0x10000000000000; valaddr_reg:x11;
val_offset:4*FLEN/8; rmval:dyn; correctval:??; testreg:x9;
fcsr_val:0*/
TEST_FPID_OP(fcvt.w.d, x22, f2, dyn, 0, 0, x11, 4*FLEN/8, x17, x8, x9,FLREG)
inst_5:// rs1==f0, rd==x4,fs1 == 0 and fe1 == 0x001 and fm1 == 0x0000000000002 and fcsr == 0x0 and rm_val == 7
/* opcode: fcvt.w.d ; op1:f0; dest:x4; op1val:0x10000000000002; valaddr_reg:x11;
val_offset:5*FLEN/8; rmval:dyn; correctval:??; testreg:x9;
fcsr_val:0*/
TEST_FPID_OP(fcvt.w.d, x4, f0, dyn, 0, 0, x11, 5*FLEN/8, x17, x8, x9,FLREG)
inst_6:// rs1==f4, rd==x0,fs1 == 0 and fe1 == 0x3ff and fm1 == 0x0000000000000 and fcsr == 0x0 and rm_val == 7
/* opcode: fcvt.w.d ; op1:f4; dest:x0; op1val:0x3ff0000000000000; valaddr_reg:x11;
val_offset:6*FLEN/8; rmval:dyn; correctval:??; testreg:x9;
fcsr_val:0*/
TEST_FPID_OP(fcvt.w.d, x0, f4, dyn, 0, 0, x11, 6*FLEN/8, x17, x8, x9,FLREG)
inst_7:// rs1==f17, rd==x10,fs1 == 0 and fe1 == 0x7fe and fm1 == 0xfffffffffffff and fcsr == 0x0 and rm_val == 7
/* opcode: fcvt.w.d ; op1:f17; dest:x10; op1val:0x7fefffffffffffff; valaddr_reg:x11;
val_offset:7*FLEN/8; rmval:dyn; correctval:??; testreg:x9;
fcsr_val:0*/
TEST_FPID_OP(fcvt.w.d, x10, f17, dyn, 0, 0, x11, 7*FLEN/8, x17, x8, x9,FLREG)
inst_8:// rs1==f16, rd==x24,fs1 == 0 and fe1 == 0x7ff and fm1 == 0x0000000000000 and fcsr == 0x0 and rm_val == 7
/* opcode: fcvt.w.d ; op1:f16; dest:x24; op1val:0x7ff0000000000000; valaddr_reg:x11;
val_offset:8*FLEN/8; rmval:dyn; correctval:??; testreg:x9;
fcsr_val:0*/
TEST_FPID_OP(fcvt.w.d, x24, f16, dyn, 0, 0, x11, 8*FLEN/8, x17, x8, x9,FLREG)
inst_9:// rs1==f12, rd==x20,fs1 == 0 and fe1 == 0x7ff and fm1 == 0x0000000000001 and fcsr == 0x0 and rm_val == 7
/* opcode: fcvt.w.d ; op1:f12; dest:x20; op1val:0x7ff0000000000001; valaddr_reg:x11;
val_offset:9*FLEN/8; rmval:dyn; correctval:??; testreg:x9;
fcsr_val:0*/
TEST_FPID_OP(fcvt.w.d, x20, f12, dyn, 0, 0, x11, 9*FLEN/8, x17, x8, x9,FLREG)
inst_10:// rs1==f6, rd==x26,fs1 == 0 and fe1 == 0x7ff and fm1 == 0x8000000000000 and fcsr == 0x0 and rm_val == 7
/* opcode: fcvt.w.d ; op1:f6; dest:x26; op1val:0x7ff8000000000000; valaddr_reg:x11;
val_offset:10*FLEN/8; rmval:dyn; correctval:??; testreg:x9;
fcsr_val:0*/
TEST_FPID_OP(fcvt.w.d, x26, f6, dyn, 0, 0, x11, 10*FLEN/8, x17, x8, x9,FLREG)
inst_11:// rs1==f28, rd==x13,fs1 == 0 and fe1 == 0x7ff and fm1 == 0x8000000000001 and fcsr == 0x0 and rm_val == 7
/* opcode: fcvt.w.d ; op1:f28; dest:x13; op1val:0x7ff8000000000001; valaddr_reg:x11;
val_offset:11*FLEN/8; rmval:dyn; correctval:??; testreg:x9;
fcsr_val:0*/
TEST_FPID_OP(fcvt.w.d, x13, f28, dyn, 0, 0, x11, 11*FLEN/8, x17, x8, x9,FLREG)
inst_12:// rs1==f21, rd==x2,fs1 == 1 and fe1 == 0x000 and fm1 == 0x0000000000000 and fcsr == 0x0 and rm_val == 7
/* opcode: fcvt.w.d ; op1:f21; dest:x2; op1val:0x8000000000000000; valaddr_reg:x11;
val_offset:12*FLEN/8; rmval:dyn; correctval:??; testreg:x9;
fcsr_val:0*/
TEST_FPID_OP(fcvt.w.d, x2, f21, dyn, 0, 0, x11, 12*FLEN/8, x17, x8, x9,FLREG)
inst_13:// rs1==f3, rd==x15,fs1 == 1 and fe1 == 0x000 and fm1 == 0x0000000000001 and fcsr == 0x0 and rm_val == 7
/* opcode: fcvt.w.d ; op1:f3; dest:x15; op1val:0x8000000000000001; valaddr_reg:x11;
val_offset:13*FLEN/8; rmval:dyn; correctval:??; testreg:x9;
fcsr_val:0*/
TEST_FPID_OP(fcvt.w.d, x15, f3, dyn, 0, 0, x11, 13*FLEN/8, x17, x8, x9,FLREG)
inst_14:// rs1==f22, rd==x16,fs1 == 1 and fe1 == 0x000 and fm1 == 0x0000000000002 and fcsr == 0x0 and rm_val == 7
/* opcode: fcvt.w.d ; op1:f22; dest:x16; op1val:0x8000000000000002; valaddr_reg:x11;
val_offset:14*FLEN/8; rmval:dyn; correctval:??; testreg:x9;
fcsr_val:0*/
TEST_FPID_OP(fcvt.w.d, x16, f22, dyn, 0, 0, x11, 14*FLEN/8, x17, x8, x9,FLREG)
inst_15:// rs1==f9, rd==x18,fs1 == 1 and fe1 == 0x000 and fm1 == 0xfffffffffffff and fcsr == 0x0 and rm_val == 7
/* opcode: fcvt.w.d ; op1:f9; dest:x18; op1val:0x800fffffffffffff; valaddr_reg:x11;
val_offset:15*FLEN/8; rmval:dyn; correctval:??; testreg:x9;
fcsr_val:0*/
TEST_FPID_OP(fcvt.w.d, x18, f9, dyn, 0, 0, x11, 15*FLEN/8, x17, x8, x9,FLREG)
inst_16:// rs1==f20, rd==x6,fs1 == 1 and fe1 == 0x001 and fm1 == 0x0000000000000 and fcsr == 0x0 and rm_val == 7
/* opcode: fcvt.w.d ; op1:f20; dest:x6; op1val:0x8010000000000000; valaddr_reg:x11;
val_offset:16*FLEN/8; rmval:dyn; correctval:??; testreg:x9;
fcsr_val:0*/
TEST_FPID_OP(fcvt.w.d, x6, f20, dyn, 0, 0, x11, 16*FLEN/8, x17, x8, x9,FLREG)
inst_17:// rs1==f27, rd==x31,fs1 == 1 and fe1 == 0x001 and fm1 == 0x0000000000002 and fcsr == 0x0 and rm_val == 7
/* opcode: fcvt.w.d ; op1:f27; dest:x31; op1val:0x8010000000000002; valaddr_reg:x11;
val_offset:17*FLEN/8; rmval:dyn; correctval:??; testreg:x9;
fcsr_val:0*/
TEST_FPID_OP(fcvt.w.d, x31, f27, dyn, 0, 0, x11, 17*FLEN/8, x17, x8, x9,FLREG)
inst_18:// rs1==f11, rd==x3,fs1 == 1 and fe1 == 0x3f8 and fm1 == 0x0000000000000 and fcsr == 0x0 and rm_val == 7
/* opcode: fcvt.w.d ; op1:f11; dest:x3; op1val:0xbf80000000000000; valaddr_reg:x11;
val_offset:18*FLEN/8; rmval:dyn; correctval:??; testreg:x9;
fcsr_val:0*/
TEST_FPID_OP(fcvt.w.d, x3, f11, dyn, 0, 0, x11, 18*FLEN/8, x17, x8, x9,FLREG)
inst_19:// rs1==f19, rd==x12,fs1 == 1 and fe1 == 0x7fe and fm1 == 0xfffffffffffff and fcsr == 0x0 and rm_val == 7
/* opcode: fcvt.w.d ; op1:f19; dest:x12; op1val:0xffefffffffffffff; valaddr_reg:x11;
val_offset:19*FLEN/8; rmval:dyn; correctval:??; testreg:x9;
fcsr_val:0*/
TEST_FPID_OP(fcvt.w.d, x12, f19, dyn, 0, 0, x11, 19*FLEN/8, x17, x8, x9,FLREG)
inst_20:// rs1==f8, rd==x30,fs1 == 1 and fe1 == 0x7ff and fm1 == 0x0000000000000 and fcsr == 0x0 and rm_val == 7
/* opcode: fcvt.w.d ; op1:f8; dest:x30; op1val:0xfff0000000000000; valaddr_reg:x11;
val_offset:20*FLEN/8; rmval:dyn; correctval:??; testreg:x9;
fcsr_val:0*/
TEST_FPID_OP(fcvt.w.d, x30, f8, dyn, 0, 0, x11, 20*FLEN/8, x17, x8, x9,FLREG)
inst_21:// rs1==f23, rd==x19,fs1 == 1 and fe1 == 0x7ff and fm1 == 0x0000000000001 and fcsr == 0x0 and rm_val == 7
/* opcode: fcvt.w.d ; op1:f23; dest:x19; op1val:0xfff0000000000001; valaddr_reg:x11;
val_offset:21*FLEN/8; rmval:dyn; correctval:??; testreg:x9;
fcsr_val:0*/
TEST_FPID_OP(fcvt.w.d, x19, f23, dyn, 0, 0, x11, 21*FLEN/8, x17, x8, x9,FLREG)
inst_22:// rs1==f5, rd==x7,fs1 == 1 and fe1 == 0x7ff and fm1 == 0x8000000000000 and fcsr == 0x0 and rm_val == 7
/* opcode: fcvt.w.d ; op1:f5; dest:x7; op1val:0xfff8000000000000; valaddr_reg:x11;
val_offset:22*FLEN/8; rmval:dyn; correctval:??; testreg:x9;
fcsr_val:0*/
TEST_FPID_OP(fcvt.w.d, x7, f5, dyn, 0, 0, x11, 22*FLEN/8, x17, x8, x9,FLREG)
inst_23:// rs1==f24, rd==x25,fs1 == 1 and fe1 == 0x7ff and fm1 == 0x8000000000001 and fcsr == 0x0 and rm_val == 7
/* opcode: fcvt.w.d ; op1:f24; dest:x25; op1val:0xfff8000000000001; valaddr_reg:x11;
val_offset:23*FLEN/8; rmval:dyn; correctval:??; testreg:x9;
fcsr_val:0*/
TEST_FPID_OP(fcvt.w.d, x25, f24, dyn, 0, 0, x11, 23*FLEN/8, x17, x8, x9,FLREG)
inst_24:// rs1==f13, rd==x5,
/* opcode: fcvt.w.d ; op1:f13; dest:x5; op1val:0x0; valaddr_reg:x11;
val_offset:24*FLEN/8; rmval:dyn; correctval:??; testreg:x9;
fcsr_val:0*/
TEST_FPID_OP(fcvt.w.d, x5, f13, dyn, 0, 0, x11, 24*FLEN/8, x17, x8, x9,FLREG)
RVTEST_VALBASEUPD(x3,test_dataset_1)
inst_25:// rs1==f10, rd==x17,
/* opcode: fcvt.w.d ; op1:f10; dest:x17; op1val:0x0; valaddr_reg:x3;
val_offset:0*FLEN/8; rmval:dyn; correctval:??; testreg:x9;
fcsr_val:0*/
TEST_FPID_OP(fcvt.w.d, x17, f10, dyn, 0, 0, x3, 0*FLEN/8, x4, x8, x9,FLREG)
inst_26:// rs1==f29, rd==x23,
/* opcode: fcvt.w.d ; op1:f29; dest:x23; op1val:0x0; valaddr_reg:x3;
val_offset:1*FLEN/8; rmval:dyn; correctval:??; testreg:x9;
fcsr_val:0*/
TEST_FPID_OP(fcvt.w.d, x23, f29, dyn, 0, 0, x3, 1*FLEN/8, x4, x8, x9,FLREG)
inst_27:// rs1==f18, rd==x9,
/* opcode: fcvt.w.d ; op1:f18; dest:x9; op1val:0x0; valaddr_reg:x3;
val_offset:2*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
fcsr_val:0*/
TEST_FPID_OP(fcvt.w.d, x9, f18, dyn, 0, 0, x3, 2*FLEN/8, x4, x8, x2,FLREG)
RVTEST_SIGBASE(x1,signature_x1_0)
inst_28:// rs1==f30, rd==x8,
/* opcode: fcvt.w.d ; op1:f30; dest:x8; op1val:0x0; valaddr_reg:x3;
val_offset:3*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
fcsr_val:0*/
TEST_FPID_OP(fcvt.w.d, x8, f30, dyn, 0, 0, x3, 3*FLEN/8, x4, x1, x2,FLREG)
inst_29:// rs1==f14, rd==x27,
/* opcode: fcvt.w.d ; op1:f14; dest:x27; op1val:0x0; valaddr_reg:x3;
val_offset:4*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
fcsr_val:0*/
TEST_FPID_OP(fcvt.w.d, x27, f14, dyn, 0, 0, x3, 4*FLEN/8, x4, x1, x2,FLREG)
inst_30:// rs1==f26, rd==x21,
/* opcode: fcvt.w.d ; op1:f26; dest:x21; op1val:0x0; valaddr_reg:x3;
val_offset:5*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
fcsr_val:0*/
TEST_FPID_OP(fcvt.w.d, x21, f26, dyn, 0, 0, x3, 5*FLEN/8, x4, x1, x2,FLREG)
inst_31:// rs1==f25, rd==x11,
/* opcode: fcvt.w.d ; op1:f25; dest:x11; op1val:0x0; valaddr_reg:x3;
val_offset:6*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
fcsr_val:0*/
TEST_FPID_OP(fcvt.w.d, x11, f25, dyn, 0, 0, x3, 6*FLEN/8, x4, x1, x2,FLREG)
inst_32:// fs1 == 0 and fe1 == 0x3ff and fm1 == 0x0000000000000 and fcsr == 0x0 and rm_val == 7
/* opcode: fcvt.w.d ; op1:f31; dest:x31; op1val:0x3ff0000000000000; valaddr_reg:x3;
val_offset:7*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
fcsr_val:0*/
TEST_FPID_OP(fcvt.w.d, x31, f31, dyn, 0, 0, x3, 7*FLEN/8, x4, x1, x2,FLREG)
#endif
RVTEST_CODE_END
RVMODEL_HALT
RVTEST_DATA_BEGIN
.align 4
rvtest_data:
.word 0xbabecafe
.word 0xabecafeb
.word 0xbecafeba
.word 0xecafebab
test_dataset_0:
NAN_BOXED(0,64,FLEN)
NAN_BOXED(1,64,FLEN)
NAN_BOXED(2,64,FLEN)
NAN_BOXED(4503599627370495,64,FLEN)
NAN_BOXED(4503599627370496,64,FLEN)
NAN_BOXED(4503599627370498,64,FLEN)
NAN_BOXED(4607182418800017408,64,FLEN)
NAN_BOXED(9218868437227405311,64,FLEN)
NAN_BOXED(9218868437227405312,64,FLEN)
NAN_BOXED(9218868437227405313,64,FLEN)
NAN_BOXED(9221120237041090560,64,FLEN)
NAN_BOXED(9221120237041090561,64,FLEN)
NAN_BOXED(9223372036854775808,64,FLEN)
NAN_BOXED(9223372036854775809,64,FLEN)
NAN_BOXED(9223372036854775810,64,FLEN)
NAN_BOXED(9227875636482146303,64,FLEN)
NAN_BOXED(9227875636482146304,64,FLEN)
NAN_BOXED(9227875636482146306,64,FLEN)
NAN_BOXED(13799029258263199744,64,FLEN)
NAN_BOXED(18442240474082181119,64,FLEN)
NAN_BOXED(18442240474082181120,64,FLEN)
NAN_BOXED(18442240474082181121,64,FLEN)
NAN_BOXED(18444492273895866368,64,FLEN)
NAN_BOXED(18444492273895866369,64,FLEN)
NAN_BOXED(0,64,FLEN)
test_dataset_1:
NAN_BOXED(0,64,FLEN)
NAN_BOXED(0,64,FLEN)
NAN_BOXED(0,64,FLEN)
NAN_BOXED(0,64,FLEN)
NAN_BOXED(0,64,FLEN)
NAN_BOXED(0,64,FLEN)
NAN_BOXED(0,64,FLEN)
NAN_BOXED(4607182418800017408,64,FLEN)
RVTEST_DATA_END
RVMODEL_DATA_BEGIN
rvtest_sig_begin:
sig_begin_canary:
CANARY;
signature_x8_0:
.fill 0*((SIGALIGN)/4),4,0xdeadbeef
signature_x8_1:
.fill 56*((SIGALIGN)/4),4,0xdeadbeef
signature_x1_0:
.fill 10*((SIGALIGN)/4),4,0xdeadbeef
#ifdef rvtest_mtrap_routine
tsig_begin_canary:
CANARY;
tsig_begin_canary:
CANARY;
mtrap_sigptr:
.fill 64*(XLEN/32),4,0xdeadbeef
tsig_end_canary:
CANARY;
tsig_end_canary:
CANARY;
#endif
#ifdef rvtest_gpr_save
gpr_save:
.fill 32*XLEN/32,4,0xdeadbeef
#endif
sig_end_canary:
CANARY;
rvtest_sig_end:
RVMODEL_DATA_END

386
vendor/riscv-arch-tests/riscv-test-suite/rv32i_m/D/src/fcvt.w.d_b22-01.S vendored
View file

@ -1,386 +0,0 @@
// -----------
// This file was generated by riscv_ctg (https://github.com/riscv-software-src/riscv-ctg)
// version : 0.7.1
// timestamp : Fri Jun 17 14:03:36 2022 GMT
// usage : riscv_ctg \
// -- cgf // --cgf /scratch/pawan/work/normalised/RV32D/fcvt.w.d.cgf \
\
// -- xlen 32 \
// --randomize \
// -----------
//
// -----------
// Copyright (c) 2020. RISC-V International. All rights reserved.
// SPDX-License-Identifier: BSD-3-Clause
// -----------
//
// This assembly file tests the fcvt.w.d instruction of the RISC-V RV32FD_Zicsr,RV64FD_Zicsr extension for the fcvt.w.d_b22 covergroup.
//
#include "model_test.h"
#include "arch_test.h"
RVTEST_ISA("RV32IFD_Zicsr,RV64IFD_Zicsr")
.section .text.init
.org 0x80
.globl rvtest_entry_point
rvtest_entry_point:
RVMODEL_BOOT
RVTEST_CODE_BEGIN
#ifdef TEST_CASE_1
RVTEST_CASE(0,"//check ISA:=regex(.*I.*D.*);def TEST_CASE_1=True;",fcvt.w.d_b22)
RVTEST_FP_ENABLE()
RVTEST_VALBASEUPD(x7,test_dataset_0)
RVTEST_SIGBASE(x2,signature_x2_1)
inst_0:// rs1==f15, rd==x16,fs1 == 0 and fe1 == 0x3ca and fm1 == 0x30e08ceb506f6 and fcsr == 0x0 and rm_val == 7
/* opcode: fcvt.w.d ; op1:f15; dest:x16; op1val:0x3ca30e08ceb506f6; valaddr_reg:x7;
val_offset:0*FLEN/8; rmval:dyn; correctval:??; testreg:x6;
fcsr_val:0*/
TEST_FPID_OP(fcvt.w.d, x16, f15, dyn, 0, 0, x7, 0*FLEN/8, x12, x2, x6,FLREG)
inst_1:// rs1==f23, rd==x30,fs1 == 0 and fe1 == 0x3fc and fm1 == 0x08577924770d3 and fcsr == 0x0 and rm_val == 7
/* opcode: fcvt.w.d ; op1:f23; dest:x30; op1val:0x3fc08577924770d3; valaddr_reg:x7;
val_offset:1*FLEN/8; rmval:dyn; correctval:??; testreg:x6;
fcsr_val:0*/
TEST_FPID_OP(fcvt.w.d, x30, f23, dyn, 0, 0, x7, 1*FLEN/8, x12, x2, x6,FLREG)
inst_2:// rs1==f5, rd==x18,fs1 == 0 and fe1 == 0x3fd and fm1 == 0x93fdc7b89296c and fcsr == 0x0 and rm_val == 7
/* opcode: fcvt.w.d ; op1:f5; dest:x18; op1val:0x3fd93fdc7b89296c; valaddr_reg:x7;
val_offset:2*FLEN/8; rmval:dyn; correctval:??; testreg:x6;
fcsr_val:0*/
TEST_FPID_OP(fcvt.w.d, x18, f5, dyn, 0, 0, x7, 2*FLEN/8, x12, x2, x6,FLREG)
inst_3:// rs1==f27, rd==x5,fs1 == 0 and fe1 == 0x3ff and fm1 == 0xd2d6b7dc59a3a and fcsr == 0x0 and rm_val == 7
/* opcode: fcvt.w.d ; op1:f27; dest:x5; op1val:0x3ffd2d6b7dc59a3a; valaddr_reg:x7;
val_offset:3*FLEN/8; rmval:dyn; correctval:??; testreg:x6;
fcsr_val:0*/
TEST_FPID_OP(fcvt.w.d, x5, f27, dyn, 0, 0, x7, 3*FLEN/8, x12, x2, x6,FLREG)
inst_4:// rs1==f1, rd==x21,fs1 == 0 and fe1 == 0x400 and fm1 == 0xcf84ba749f9c5 and fcsr == 0x0 and rm_val == 7
/* opcode: fcvt.w.d ; op1:f1; dest:x21; op1val:0x400cf84ba749f9c5; valaddr_reg:x7;
val_offset:4*FLEN/8; rmval:dyn; correctval:??; testreg:x6;
fcsr_val:0*/
TEST_FPID_OP(fcvt.w.d, x21, f1, dyn, 0, 0, x7, 4*FLEN/8, x12, x2, x6,FLREG)
inst_5:// rs1==f8, rd==x24,fs1 == 0 and fe1 == 0x401 and fm1 == 0x854a908ceac39 and fcsr == 0x0 and rm_val == 7
/* opcode: fcvt.w.d ; op1:f8; dest:x24; op1val:0x401854a908ceac39; valaddr_reg:x7;
val_offset:5*FLEN/8; rmval:dyn; correctval:??; testreg:x6;
fcsr_val:0*/
TEST_FPID_OP(fcvt.w.d, x24, f8, dyn, 0, 0, x7, 5*FLEN/8, x12, x2, x6,FLREG)
inst_6:// rs1==f24, rd==x17,fs1 == 0 and fe1 == 0x402 and fm1 == 0x137a953e8eb43 and fcsr == 0x0 and rm_val == 7
/* opcode: fcvt.w.d ; op1:f24; dest:x17; op1val:0x402137a953e8eb43; valaddr_reg:x7;
val_offset:6*FLEN/8; rmval:dyn; correctval:??; testreg:x6;
fcsr_val:0*/
TEST_FPID_OP(fcvt.w.d, x17, f24, dyn, 0, 0, x7, 6*FLEN/8, x12, x2, x6,FLREG)
inst_7:// rs1==f22, rd==x19,fs1 == 0 and fe1 == 0x404 and fm1 == 0x5c74eff1e5bef and fcsr == 0x0 and rm_val == 7
/* opcode: fcvt.w.d ; op1:f22; dest:x19; op1val:0x4045c74eff1e5bef; valaddr_reg:x7;
val_offset:7*FLEN/8; rmval:dyn; correctval:??; testreg:x6;
fcsr_val:0*/
TEST_FPID_OP(fcvt.w.d, x19, f22, dyn, 0, 0, x7, 7*FLEN/8, x12, x2, x6,FLREG)
inst_8:// rs1==f14, rd==x27,fs1 == 0 and fe1 == 0x405 and fm1 == 0xdc3386b9f15c4 and fcsr == 0x0 and rm_val == 7
/* opcode: fcvt.w.d ; op1:f14; dest:x27; op1val:0x405dc3386b9f15c4; valaddr_reg:x7;
val_offset:8*FLEN/8; rmval:dyn; correctval:??; testreg:x6;
fcsr_val:0*/
TEST_FPID_OP(fcvt.w.d, x27, f14, dyn, 0, 0, x7, 8*FLEN/8, x12, x2, x6,FLREG)
inst_9:// rs1==f31, rd==x4,fs1 == 0 and fe1 == 0x406 and fm1 == 0x5ae6a9a6ab329 and fcsr == 0x0 and rm_val == 7
/* opcode: fcvt.w.d ; op1:f31; dest:x4; op1val:0x4065ae6a9a6ab329; valaddr_reg:x7;
val_offset:9*FLEN/8; rmval:dyn; correctval:??; testreg:x6;
fcsr_val:0*/
TEST_FPID_OP(fcvt.w.d, x4, f31, dyn, 0, 0, x7, 9*FLEN/8, x12, x2, x6,FLREG)
inst_10:// rs1==f13, rd==x11,fs1 == 0 and fe1 == 0x408 and fm1 == 0x43277acca7f0d and fcsr == 0x0 and rm_val == 7
/* opcode: fcvt.w.d ; op1:f13; dest:x11; op1val:0x40843277acca7f0d; valaddr_reg:x7;
val_offset:10*FLEN/8; rmval:dyn; correctval:??; testreg:x6;
fcsr_val:0*/
TEST_FPID_OP(fcvt.w.d, x11, f13, dyn, 0, 0, x7, 10*FLEN/8, x12, x2, x6,FLREG)
inst_11:// rs1==f17, rd==x3,fs1 == 0 and fe1 == 0x409 and fm1 == 0xaf9492cb7362c and fcsr == 0x0 and rm_val == 7
/* opcode: fcvt.w.d ; op1:f17; dest:x3; op1val:0x409af9492cb7362c; valaddr_reg:x7;
val_offset:11*FLEN/8; rmval:dyn; correctval:??; testreg:x6;
fcsr_val:0*/
TEST_FPID_OP(fcvt.w.d, x3, f17, dyn, 0, 0, x7, 11*FLEN/8, x12, x2, x6,FLREG)
inst_12:// rs1==f28, rd==x8,fs1 == 0 and fe1 == 0x40a and fm1 == 0x5cd28a96ec2b3 and fcsr == 0x0 and rm_val == 7
/* opcode: fcvt.w.d ; op1:f28; dest:x8; op1val:0x40a5cd28a96ec2b3; valaddr_reg:x7;
val_offset:12*FLEN/8; rmval:dyn; correctval:??; testreg:x6;
fcsr_val:0*/
TEST_FPID_OP(fcvt.w.d, x8, f28, dyn, 0, 0, x7, 12*FLEN/8, x12, x2, x6,FLREG)
inst_13:// rs1==f9, rd==x25,fs1 == 0 and fe1 == 0x40d and fm1 == 0x9d02f708cc1b6 and fcsr == 0x0 and rm_val == 7
/* opcode: fcvt.w.d ; op1:f9; dest:x25; op1val:0x40d9d02f708cc1b6; valaddr_reg:x7;
val_offset:13*FLEN/8; rmval:dyn; correctval:??; testreg:x6;
fcsr_val:0*/
TEST_FPID_OP(fcvt.w.d, x25, f9, dyn, 0, 0, x7, 13*FLEN/8, x12, x2, x6,FLREG)
inst_14:// rs1==f0, rd==x28,fs1 == 0 and fe1 == 0x40e and fm1 == 0x953b00b54aa22 and fcsr == 0x0 and rm_val == 7
/* opcode: fcvt.w.d ; op1:f0; dest:x28; op1val:0x40e953b00b54aa22; valaddr_reg:x7;
val_offset:14*FLEN/8; rmval:dyn; correctval:??; testreg:x6;
fcsr_val:0*/
TEST_FPID_OP(fcvt.w.d, x28, f0, dyn, 0, 0, x7, 14*FLEN/8, x12, x2, x6,FLREG)
inst_15:// rs1==f11, rd==x10,fs1 == 0 and fe1 == 0x40f and fm1 == 0x224c03c53d0e3 and fcsr == 0x0 and rm_val == 7
/* opcode: fcvt.w.d ; op1:f11; dest:x10; op1val:0x40f224c03c53d0e3; valaddr_reg:x7;
val_offset:15*FLEN/8; rmval:dyn; correctval:??; testreg:x6;
fcsr_val:0*/
TEST_FPID_OP(fcvt.w.d, x10, f11, dyn, 0, 0, x7, 15*FLEN/8, x12, x2, x6,FLREG)
inst_16:// rs1==f6, rd==x26,fs1 == 0 and fe1 == 0x410 and fm1 == 0xe8dacf0e58650 and fcsr == 0x0 and rm_val == 7
/* opcode: fcvt.w.d ; op1:f6; dest:x26; op1val:0x410e8dacf0e58650; valaddr_reg:x7;
val_offset:16*FLEN/8; rmval:dyn; correctval:??; testreg:x6;
fcsr_val:0*/
TEST_FPID_OP(fcvt.w.d, x26, f6, dyn, 0, 0, x7, 16*FLEN/8, x12, x2, x6,FLREG)
inst_17:// rs1==f12, rd==x0,fs1 == 0 and fe1 == 0x412 and fm1 == 0x3d7c9e5f0307e and fcsr == 0x0 and rm_val == 7
/* opcode: fcvt.w.d ; op1:f12; dest:x0; op1val:0x4123d7c9e5f0307e; valaddr_reg:x7;
val_offset:17*FLEN/8; rmval:dyn; correctval:??; testreg:x6;
fcsr_val:0*/
TEST_FPID_OP(fcvt.w.d, x0, f12, dyn, 0, 0, x7, 17*FLEN/8, x12, x2, x6,FLREG)
inst_18:// rs1==f4, rd==x31,fs1 == 0 and fe1 == 0x413 and fm1 == 0x8c8a1aaac3142 and fcsr == 0x0 and rm_val == 7
/* opcode: fcvt.w.d ; op1:f4; dest:x31; op1val:0x4138c8a1aaac3142; valaddr_reg:x7;
val_offset:18*FLEN/8; rmval:dyn; correctval:??; testreg:x6;
fcsr_val:0*/
TEST_FPID_OP(fcvt.w.d, x31, f4, dyn, 0, 0, x7, 18*FLEN/8, x12, x2, x6,FLREG)
inst_19:// rs1==f20, rd==x29,fs1 == 0 and fe1 == 0x414 and fm1 == 0x785036f9fb997 and fcsr == 0x0 and rm_val == 7
/* opcode: fcvt.w.d ; op1:f20; dest:x29; op1val:0x414785036f9fb997; valaddr_reg:x7;
val_offset:19*FLEN/8; rmval:dyn; correctval:??; testreg:x6;
fcsr_val:0*/
TEST_FPID_OP(fcvt.w.d, x29, f20, dyn, 0, 0, x7, 19*FLEN/8, x12, x2, x6,FLREG)
inst_20:// rs1==f29, rd==x15,fs1 == 0 and fe1 == 0x415 and fm1 == 0x95a4da7298c66 and fcsr == 0x0 and rm_val == 7
/* opcode: fcvt.w.d ; op1:f29; dest:x15; op1val:0x41595a4da7298c66; valaddr_reg:x7;
val_offset:20*FLEN/8; rmval:dyn; correctval:??; testreg:x6;
fcsr_val:0*/
TEST_FPID_OP(fcvt.w.d, x15, f29, dyn, 0, 0, x7, 20*FLEN/8, x12, x2, x6,FLREG)
inst_21:// rs1==f18, rd==x1,fs1 == 0 and fe1 == 0x416 and fm1 == 0x807dad814d575 and fcsr == 0x0 and rm_val == 7
/* opcode: fcvt.w.d ; op1:f18; dest:x1; op1val:0x416807dad814d575; valaddr_reg:x7;
val_offset:21*FLEN/8; rmval:dyn; correctval:??; testreg:x6;
fcsr_val:0*/
TEST_FPID_OP(fcvt.w.d, x1, f18, dyn, 0, 0, x7, 21*FLEN/8, x12, x2, x6,FLREG)
inst_22:// rs1==f2, rd==x13,fs1 == 0 and fe1 == 0x418 and fm1 == 0x3d06169b1dcbf and fcsr == 0x0 and rm_val == 7
/* opcode: fcvt.w.d ; op1:f2; dest:x13; op1val:0x4183d06169b1dcbf; valaddr_reg:x7;
val_offset:22*FLEN/8; rmval:dyn; correctval:??; testreg:x6;
fcsr_val:0*/
TEST_FPID_OP(fcvt.w.d, x13, f2, dyn, 0, 0, x7, 22*FLEN/8, x12, x2, x6,FLREG)
inst_23:// rs1==f19, rd==x22,fs1 == 0 and fe1 == 0x419 and fm1 == 0x7f21608208d09 and fcsr == 0x0 and rm_val == 7
/* opcode: fcvt.w.d ; op1:f19; dest:x22; op1val:0x4197f21608208d09; valaddr_reg:x7;
val_offset:23*FLEN/8; rmval:dyn; correctval:??; testreg:x6;
fcsr_val:0*/
TEST_FPID_OP(fcvt.w.d, x22, f19, dyn, 0, 0, x7, 23*FLEN/8, x12, x2, x6,FLREG)
inst_24:// rs1==f25, rd==x9,fs1 == 0 and fe1 == 0x41c and fm1 == 0x14b91dae98554 and fcsr == 0x0 and rm_val == 7
/* opcode: fcvt.w.d ; op1:f25; dest:x9; op1val:0x41c14b91dae98554; valaddr_reg:x7;
val_offset:24*FLEN/8; rmval:dyn; correctval:??; testreg:x6;
fcsr_val:0*/
TEST_FPID_OP(fcvt.w.d, x9, f25, dyn, 0, 0, x7, 24*FLEN/8, x12, x2, x6,FLREG)
RVTEST_VALBASEUPD(x4,test_dataset_1)
inst_25:// rs1==f10, rd==x20,fs1 == 0 and fe1 == 0x420 and fm1 == 0xc5ec6c6880007 and fcsr == 0x0 and rm_val == 7
/* opcode: fcvt.w.d ; op1:f10; dest:x20; op1val:0x420c5ec6c6880007; valaddr_reg:x4;
val_offset:0*FLEN/8; rmval:dyn; correctval:??; testreg:x6;
fcsr_val:0*/
TEST_FPID_OP(fcvt.w.d, x20, f10, dyn, 0, 0, x4, 0*FLEN/8, x5, x2, x6,FLREG)
inst_26:// rs1==f21, rd==x23,fs1 == 0 and fe1 == 0x5ca and fm1 == 0xf871c6ee84270 and fcsr == 0x0 and rm_val == 7
/* opcode: fcvt.w.d ; op1:f21; dest:x23; op1val:0x5caf871c6ee84270; valaddr_reg:x4;
val_offset:1*FLEN/8; rmval:dyn; correctval:??; testreg:x6;
fcsr_val:0*/
TEST_FPID_OP(fcvt.w.d, x23, f21, dyn, 0, 0, x4, 1*FLEN/8, x5, x2, x6,FLREG)
inst_27:// rs1==f30, rd==x14,fs1 == 1 and fe1 == 0x3fe and fm1 == 0x766ba34c2da80 and fcsr == 0x0 and rm_val == 7
/* opcode: fcvt.w.d ; op1:f30; dest:x14; op1val:0xbfe766ba34c2da80; valaddr_reg:x4;
val_offset:2*FLEN/8; rmval:dyn; correctval:??; testreg:x3;
fcsr_val:0*/
TEST_FPID_OP(fcvt.w.d, x14, f30, dyn, 0, 0, x4, 2*FLEN/8, x5, x2, x3,FLREG)
RVTEST_SIGBASE(x1,signature_x1_0)
inst_28:// rs1==f16, rd==x7,fs1 == 1 and fe1 == 0x403 and fm1 == 0xf3ebcf3d06f86 and fcsr == 0x0 and rm_val == 7
/* opcode: fcvt.w.d ; op1:f16; dest:x7; op1val:0xc03f3ebcf3d06f86; valaddr_reg:x4;
val_offset:3*FLEN/8; rmval:dyn; correctval:??; testreg:x3;
fcsr_val:0*/
TEST_FPID_OP(fcvt.w.d, x7, f16, dyn, 0, 0, x4, 3*FLEN/8, x5, x1, x3,FLREG)
inst_29:// rs1==f7, rd==x6,fs1 == 1 and fe1 == 0x407 and fm1 == 0x489b36bd7f503 and fcsr == 0x0 and rm_val == 7
/* opcode: fcvt.w.d ; op1:f7; dest:x6; op1val:0xc07489b36bd7f503; valaddr_reg:x4;
val_offset:4*FLEN/8; rmval:dyn; correctval:??; testreg:x3;
fcsr_val:0*/
TEST_FPID_OP(fcvt.w.d, x6, f7, dyn, 0, 0, x4, 4*FLEN/8, x5, x1, x3,FLREG)
inst_30:// rs1==f3, rd==x12,fs1 == 1 and fe1 == 0x40b and fm1 == 0xc491074f942cb and fcsr == 0x0 and rm_val == 7
/* opcode: fcvt.w.d ; op1:f3; dest:x12; op1val:0xc0bc491074f942cb; valaddr_reg:x4;
val_offset:5*FLEN/8; rmval:dyn; correctval:??; testreg:x3;
fcsr_val:0*/
TEST_FPID_OP(fcvt.w.d, x12, f3, dyn, 0, 0, x4, 5*FLEN/8, x5, x1, x3,FLREG)
inst_31:// rs1==f26, rd==x2,fs1 == 1 and fe1 == 0x40c and fm1 == 0x3d480fb7f6f5d and fcsr == 0x0 and rm_val == 7
/* opcode: fcvt.w.d ; op1:f26; dest:x2; op1val:0xc0c3d480fb7f6f5d; valaddr_reg:x4;
val_offset:6*FLEN/8; rmval:dyn; correctval:??; testreg:x3;
fcsr_val:0*/
TEST_FPID_OP(fcvt.w.d, x2, f26, dyn, 0, 0, x4, 6*FLEN/8, x5, x1, x3,FLREG)
inst_32:// fs1 == 1 and fe1 == 0x411 and fm1 == 0x5dbbb894deab4 and fcsr == 0x0 and rm_val == 7
/* opcode: fcvt.w.d ; op1:f31; dest:x31; op1val:0xc115dbbb894deab4; valaddr_reg:x4;
val_offset:7*FLEN/8; rmval:dyn; correctval:??; testreg:x3;
fcsr_val:0*/
TEST_FPID_OP(fcvt.w.d, x31, f31, dyn, 0, 0, x4, 7*FLEN/8, x5, x1, x3,FLREG)
inst_33:// fs1 == 1 and fe1 == 0x417 and fm1 == 0x396bad798c9cf and fcsr == 0x0 and rm_val == 7
/* opcode: fcvt.w.d ; op1:f31; dest:x31; op1val:0xc17396bad798c9cf; valaddr_reg:x4;
val_offset:8*FLEN/8; rmval:dyn; correctval:??; testreg:x3;
fcsr_val:0*/
TEST_FPID_OP(fcvt.w.d, x31, f31, dyn, 0, 0, x4, 8*FLEN/8, x5, x1, x3,FLREG)
inst_34:// fs1 == 1 and fe1 == 0x41a and fm1 == 0x9b4f3d167533a and fcsr == 0x0 and rm_val == 7
/* opcode: fcvt.w.d ; op1:f31; dest:x31; op1val:0xc1a9b4f3d167533a; valaddr_reg:x4;
val_offset:9*FLEN/8; rmval:dyn; correctval:??; testreg:x3;
fcsr_val:0*/
TEST_FPID_OP(fcvt.w.d, x31, f31, dyn, 0, 0, x4, 9*FLEN/8, x5, x1, x3,FLREG)
inst_35:// fs1 == 1 and fe1 == 0x41b and fm1 == 0x889261270dee2 and fcsr == 0x0 and rm_val == 7
/* opcode: fcvt.w.d ; op1:f31; dest:x31; op1val:0xc1b889261270dee2; valaddr_reg:x4;
val_offset:10*FLEN/8; rmval:dyn; correctval:??; testreg:x3;
fcsr_val:0*/
TEST_FPID_OP(fcvt.w.d, x31, f31, dyn, 0, 0, x4, 10*FLEN/8, x5, x1, x3,FLREG)
inst_36:// fs1 == 1 and fe1 == 0x41d and fm1 == 0x9136562694646 and fcsr == 0x0 and rm_val == 7
/* opcode: fcvt.w.d ; op1:f31; dest:x31; op1val:0xc1d9136562694646; valaddr_reg:x4;
val_offset:11*FLEN/8; rmval:dyn; correctval:??; testreg:x3;
fcsr_val:0*/
TEST_FPID_OP(fcvt.w.d, x31, f31, dyn, 0, 0, x4, 11*FLEN/8, x5, x1, x3,FLREG)
inst_37:// fs1 == 1 and fe1 == 0x41e and fm1 == 0xe9b7e5fc9eba4 and fcsr == 0x0 and rm_val == 7
/* opcode: fcvt.w.d ; op1:f31; dest:x31; op1val:0xc1ee9b7e5fc9eba4; valaddr_reg:x4;
val_offset:12*FLEN/8; rmval:dyn; correctval:??; testreg:x3;
fcsr_val:0*/
TEST_FPID_OP(fcvt.w.d, x31, f31, dyn, 0, 0, x4, 12*FLEN/8, x5, x1, x3,FLREG)
inst_38:// fs1 == 1 and fe1 == 0x41f and fm1 == 0x1ce80265039f6 and fcsr == 0x0 and rm_val == 7
/* opcode: fcvt.w.d ; op1:f31; dest:x31; op1val:0xc1f1ce80265039f6; valaddr_reg:x4;
val_offset:13*FLEN/8; rmval:dyn; correctval:??; testreg:x3;
fcsr_val:0*/
TEST_FPID_OP(fcvt.w.d, x31, f31, dyn, 0, 0, x4, 13*FLEN/8, x5, x1, x3,FLREG)
inst_39:// fs1 == 1 and fe1 == 0x421 and fm1 == 0x2a96d71097999 and fcsr == 0x0 and rm_val == 7
/* opcode: fcvt.w.d ; op1:f31; dest:x31; op1val:0xc212a96d71097999; valaddr_reg:x4;
val_offset:14*FLEN/8; rmval:dyn; correctval:??; testreg:x3;
fcsr_val:0*/
TEST_FPID_OP(fcvt.w.d, x31, f31, dyn, 0, 0, x4, 14*FLEN/8, x5, x1, x3,FLREG)
inst_40:// fs1 == 0 and fe1 == 0x412 and fm1 == 0x3d7c9e5f0307e and fcsr == 0x0 and rm_val == 7
/* opcode: fcvt.w.d ; op1:f31; dest:x31; op1val:0x4123d7c9e5f0307e; valaddr_reg:x4;
val_offset:15*FLEN/8; rmval:dyn; correctval:??; testreg:x3;
fcsr_val:0*/
TEST_FPID_OP(fcvt.w.d, x31, f31, dyn, 0, 0, x4, 15*FLEN/8, x5, x1, x3,FLREG)
#endif
RVTEST_CODE_END
RVMODEL_HALT
RVTEST_DATA_BEGIN
.align 4
rvtest_data:
.word 0xbabecafe
.word 0xabecafeb
.word 0xbecafeba
.word 0xecafebab
test_dataset_0:
NAN_BOXED(4369351494470010614,64,FLEN)
NAN_BOXED(4593818368519663827,64,FLEN)
NAN_BOXED(4600778710533613932,64,FLEN)
NAN_BOXED(4610891533192108602,64,FLEN)
NAN_BOXED(4615336721960794565,64,FLEN)
NAN_BOXED(4618534502842412089,64,FLEN)
NAN_BOXED(4621035893055613763,64,FLEN)
NAN_BOXED(4631326933921979375,64,FLEN)
NAN_BOXED(4638077838352651716,64,FLEN)
NAN_BOXED(4640306763955614505,64,FLEN)
NAN_BOXED(4648896204934643469,64,FLEN)
NAN_BOXED(4655307257518962220,64,FLEN)
NAN_BOXED(4658354964109640371,64,FLEN)
NAN_BOXED(4672994990543913398,64,FLEN)
NAN_BOXED(4677361703570418210,64,FLEN)
NAN_BOXED(4679843370855813347,64,FLEN)
NAN_BOXED(4687840036054730320,64,FLEN)
NAN_BOXED(4693832498796310654,64,FLEN)
NAN_BOXED(4699726807839813954,64,FLEN)
NAN_BOXED(4703874585615907223,64,FLEN)
NAN_BOXED(4708894174956063846,64,FLEN)
NAN_BOXED(4713025646552733045,64,FLEN)
NAN_BOXED(4720845951218080959,64,FLEN)
NAN_BOXED(4726512510388178185,64,FLEN)
NAN_BOXED(4738151372785550676,64,FLEN)
test_dataset_1:
NAN_BOXED(4759283114051108871,64,FLEN)
NAN_BOXED(6678705328603284080,64,FLEN)
NAN_BOXED(13828134130799532672,64,FLEN)
NAN_BOXED(13852859960080232326,64,FLEN)
NAN_BOXED(13867860556282066179,64,FLEN)
NAN_BOXED(13888055685934564043,64,FLEN)
NAN_BOXED(13890179326181076829,64,FLEN)
NAN_BOXED(13913268222339967668,64,FLEN)
NAN_BOXED(13939651000867015119,64,FLEN)
NAN_BOXED(13954883879667454778,64,FLEN)
NAN_BOXED(13959057841646001890,64,FLEN)
NAN_BOXED(13968217045429995078,64,FLEN)
NAN_BOXED(13974277660852480932,64,FLEN)
NAN_BOXED(13975178168501287414,64,FLEN)
NAN_BOXED(13984426080451787161,64,FLEN)
NAN_BOXED(4693832498796310654,64,FLEN)
RVTEST_DATA_END
RVMODEL_DATA_BEGIN
rvtest_sig_begin:
sig_begin_canary:
CANARY;
signature_x2_0:
.fill 0*((SIGALIGN)/4),4,0xdeadbeef
signature_x2_1:
.fill 56*((SIGALIGN)/4),4,0xdeadbeef
signature_x1_0:
.fill 26*((SIGALIGN)/4),4,0xdeadbeef
#ifdef rvtest_mtrap_routine
tsig_begin_canary:
CANARY;
tsig_begin_canary:
CANARY;
mtrap_sigptr:
.fill 64*(XLEN/32),4,0xdeadbeef
tsig_end_canary:
CANARY;
tsig_end_canary:
CANARY;
#endif
#ifdef rvtest_gpr_save
gpr_save:
.fill 32*XLEN/32,4,0xdeadbeef
#endif
sig_end_canary:
CANARY;
rvtest_sig_end:
RVMODEL_DATA_END

421
vendor/riscv-arch-tests/riscv-test-suite/rv32i_m/D/src/fcvt.w.d_b23-01.S vendored
View file

@ -1,421 +0,0 @@
// -----------
// This file was generated by riscv_ctg (https://github.com/riscv-software-src/riscv-ctg)
// version : 0.7.1
// timestamp : Fri Jun 17 14:03:36 2022 GMT
// usage : riscv_ctg \
// -- cgf // --cgf /scratch/pawan/work/normalised/RV32D/fcvt.w.d.cgf \
\
// -- xlen 32 \
// --randomize \
// -----------
//
// -----------
// Copyright (c) 2020. RISC-V International. All rights reserved.
// SPDX-License-Identifier: BSD-3-Clause
// -----------
//
// This assembly file tests the fcvt.w.d instruction of the RISC-V RV32FD_Zicsr,RV64FD_Zicsr extension for the fcvt.w.d_b23 covergroup.
//
#include "model_test.h"
#include "arch_test.h"
RVTEST_ISA("RV32IFD_Zicsr,RV64IFD_Zicsr")
.section .text.init
.org 0x80
.globl rvtest_entry_point
rvtest_entry_point:
RVMODEL_BOOT
RVTEST_CODE_BEGIN
#ifdef TEST_CASE_1
RVTEST_CASE(0,"//check ISA:=regex(.*I.*D.*);def TEST_CASE_1=True;",fcvt.w.d_b23)
RVTEST_FP_ENABLE()
RVTEST_VALBASEUPD(x1,test_dataset_0)
RVTEST_SIGBASE(x3,signature_x3_1)
inst_0:// rs1==f26, rd==x6,fs1 == 0 and fe1 == 0x43d and fm1 == 0xffffffffffffc and fcsr == 0x0 and rm_val == 7
/* opcode: fcvt.w.d ; op1:f26; dest:x6; op1val:0x43dffffffffffffc; valaddr_reg:x1;
val_offset:0*FLEN/8; rmval:dyn; correctval:??; testreg:x7;
fcsr_val:0*/
TEST_FPID_OP(fcvt.w.d, x6, f26, dyn, 0, 0, x1, 0*FLEN/8, x16, x3, x7,FLREG)
inst_1:// rs1==f17, rd==x12,fs1 == 0 and fe1 == 0x43d and fm1 == 0xffffffffffffc and fcsr == 0x20 and rm_val == 7
/* opcode: fcvt.w.d ; op1:f17; dest:x12; op1val:0x43dffffffffffffc; valaddr_reg:x1;
val_offset:1*FLEN/8; rmval:dyn; correctval:??; testreg:x7;
fcsr_val:32*/
TEST_FPID_OP(fcvt.w.d, x12, f17, dyn, 32, 0, x1, 1*FLEN/8, x16, x3, x7,FLREG)
inst_2:// rs1==f18, rd==x27,fs1 == 0 and fe1 == 0x43d and fm1 == 0xffffffffffffc and fcsr == 0x40 and rm_val == 7
/* opcode: fcvt.w.d ; op1:f18; dest:x27; op1val:0x43dffffffffffffc; valaddr_reg:x1;
val_offset:2*FLEN/8; rmval:dyn; correctval:??; testreg:x7;
fcsr_val:64*/
TEST_FPID_OP(fcvt.w.d, x27, f18, dyn, 64, 0, x1, 2*FLEN/8, x16, x3, x7,FLREG)
inst_3:// rs1==f25, rd==x11,fs1 == 0 and fe1 == 0x43d and fm1 == 0xffffffffffffc and fcsr == 0x60 and rm_val == 7
/* opcode: fcvt.w.d ; op1:f25; dest:x11; op1val:0x43dffffffffffffc; valaddr_reg:x1;
val_offset:3*FLEN/8; rmval:dyn; correctval:??; testreg:x7;
fcsr_val:96*/
TEST_FPID_OP(fcvt.w.d, x11, f25, dyn, 96, 0, x1, 3*FLEN/8, x16, x3, x7,FLREG)
inst_4:// rs1==f31, rd==x25,fs1 == 0 and fe1 == 0x43d and fm1 == 0xffffffffffffc and fcsr == 0x80 and rm_val == 7
/* opcode: fcvt.w.d ; op1:f31; dest:x25; op1val:0x43dffffffffffffc; valaddr_reg:x1;
val_offset:4*FLEN/8; rmval:dyn; correctval:??; testreg:x7;
fcsr_val:128*/
TEST_FPID_OP(fcvt.w.d, x25, f31, dyn, 128, 0, x1, 4*FLEN/8, x16, x3, x7,FLREG)
inst_5:// rs1==f6, rd==x14,fs1 == 0 and fe1 == 0x43d and fm1 == 0xffffffffffffd and fcsr == 0x0 and rm_val == 7
/* opcode: fcvt.w.d ; op1:f6; dest:x14; op1val:0x43dffffffffffffd; valaddr_reg:x1;
val_offset:5*FLEN/8; rmval:dyn; correctval:??; testreg:x7;
fcsr_val:0*/
TEST_FPID_OP(fcvt.w.d, x14, f6, dyn, 0, 0, x1, 5*FLEN/8, x16, x3, x7,FLREG)
inst_6:// rs1==f24, rd==x28,fs1 == 0 and fe1 == 0x43d and fm1 == 0xffffffffffffd and fcsr == 0x20 and rm_val == 7
/* opcode: fcvt.w.d ; op1:f24; dest:x28; op1val:0x43dffffffffffffd; valaddr_reg:x1;
val_offset:6*FLEN/8; rmval:dyn; correctval:??; testreg:x7;
fcsr_val:32*/
TEST_FPID_OP(fcvt.w.d, x28, f24, dyn, 32, 0, x1, 6*FLEN/8, x16, x3, x7,FLREG)
inst_7:// rs1==f12, rd==x18,fs1 == 0 and fe1 == 0x43d and fm1 == 0xffffffffffffd and fcsr == 0x40 and rm_val == 7
/* opcode: fcvt.w.d ; op1:f12; dest:x18; op1val:0x43dffffffffffffd; valaddr_reg:x1;
val_offset:7*FLEN/8; rmval:dyn; correctval:??; testreg:x7;
fcsr_val:64*/
TEST_FPID_OP(fcvt.w.d, x18, f12, dyn, 64, 0, x1, 7*FLEN/8, x16, x3, x7,FLREG)
inst_8:// rs1==f20, rd==x31,fs1 == 0 and fe1 == 0x43d and fm1 == 0xffffffffffffd and fcsr == 0x60 and rm_val == 7
/* opcode: fcvt.w.d ; op1:f20; dest:x31; op1val:0x43dffffffffffffd; valaddr_reg:x1;
val_offset:8*FLEN/8; rmval:dyn; correctval:??; testreg:x7;
fcsr_val:96*/
TEST_FPID_OP(fcvt.w.d, x31, f20, dyn, 96, 0, x1, 8*FLEN/8, x16, x3, x7,FLREG)
inst_9:// rs1==f9, rd==x20,fs1 == 0 and fe1 == 0x43d and fm1 == 0xffffffffffffd and fcsr == 0x80 and rm_val == 7
/* opcode: fcvt.w.d ; op1:f9; dest:x20; op1val:0x43dffffffffffffd; valaddr_reg:x1;
val_offset:9*FLEN/8; rmval:dyn; correctval:??; testreg:x7;
fcsr_val:128*/
TEST_FPID_OP(fcvt.w.d, x20, f9, dyn, 128, 0, x1, 9*FLEN/8, x16, x3, x7,FLREG)
inst_10:// rs1==f27, rd==x5,fs1 == 0 and fe1 == 0x43d and fm1 == 0xffffffffffffe and fcsr == 0x0 and rm_val == 7
/* opcode: fcvt.w.d ; op1:f27; dest:x5; op1val:0x43dffffffffffffe; valaddr_reg:x1;
val_offset:10*FLEN/8; rmval:dyn; correctval:??; testreg:x7;
fcsr_val:0*/
TEST_FPID_OP(fcvt.w.d, x5, f27, dyn, 0, 0, x1, 10*FLEN/8, x16, x3, x7,FLREG)
inst_11:// rs1==f10, rd==x9,fs1 == 0 and fe1 == 0x43d and fm1 == 0xffffffffffffe and fcsr == 0x20 and rm_val == 7
/* opcode: fcvt.w.d ; op1:f10; dest:x9; op1val:0x43dffffffffffffe; valaddr_reg:x1;
val_offset:11*FLEN/8; rmval:dyn; correctval:??; testreg:x7;
fcsr_val:32*/
TEST_FPID_OP(fcvt.w.d, x9, f10, dyn, 32, 0, x1, 11*FLEN/8, x16, x3, x7,FLREG)
inst_12:// rs1==f0, rd==x17,fs1 == 0 and fe1 == 0x43d and fm1 == 0xffffffffffffe and fcsr == 0x40 and rm_val == 7
/* opcode: fcvt.w.d ; op1:f0; dest:x17; op1val:0x43dffffffffffffe; valaddr_reg:x1;
val_offset:12*FLEN/8; rmval:dyn; correctval:??; testreg:x7;
fcsr_val:64*/
TEST_FPID_OP(fcvt.w.d, x17, f0, dyn, 64, 0, x1, 12*FLEN/8, x16, x3, x7,FLREG)
inst_13:// rs1==f14, rd==x24,fs1 == 0 and fe1 == 0x43d and fm1 == 0xffffffffffffe and fcsr == 0x60 and rm_val == 7
/* opcode: fcvt.w.d ; op1:f14; dest:x24; op1val:0x43dffffffffffffe; valaddr_reg:x1;
val_offset:13*FLEN/8; rmval:dyn; correctval:??; testreg:x7;
fcsr_val:96*/
TEST_FPID_OP(fcvt.w.d, x24, f14, dyn, 96, 0, x1, 13*FLEN/8, x16, x3, x7,FLREG)
inst_14:// rs1==f1, rd==x4,fs1 == 0 and fe1 == 0x43d and fm1 == 0xffffffffffffe and fcsr == 0x80 and rm_val == 7
/* opcode: fcvt.w.d ; op1:f1; dest:x4; op1val:0x43dffffffffffffe; valaddr_reg:x1;
val_offset:14*FLEN/8; rmval:dyn; correctval:??; testreg:x7;
fcsr_val:128*/
TEST_FPID_OP(fcvt.w.d, x4, f1, dyn, 128, 0, x1, 14*FLEN/8, x16, x3, x7,FLREG)
inst_15:// rs1==f30, rd==x13,fs1 == 0 and fe1 == 0x43d and fm1 == 0xfffffffffffff and fcsr == 0x0 and rm_val == 7
/* opcode: fcvt.w.d ; op1:f30; dest:x13; op1val:0x43dfffffffffffff; valaddr_reg:x1;
val_offset:15*FLEN/8; rmval:dyn; correctval:??; testreg:x7;
fcsr_val:0*/
TEST_FPID_OP(fcvt.w.d, x13, f30, dyn, 0, 0, x1, 15*FLEN/8, x16, x3, x7,FLREG)
inst_16:// rs1==f4, rd==x22,fs1 == 0 and fe1 == 0x43d and fm1 == 0xfffffffffffff and fcsr == 0x20 and rm_val == 7
/* opcode: fcvt.w.d ; op1:f4; dest:x22; op1val:0x43dfffffffffffff; valaddr_reg:x1;
val_offset:16*FLEN/8; rmval:dyn; correctval:??; testreg:x7;
fcsr_val:32*/
TEST_FPID_OP(fcvt.w.d, x22, f4, dyn, 32, 0, x1, 16*FLEN/8, x16, x3, x7,FLREG)
inst_17:// rs1==f19, rd==x30,fs1 == 0 and fe1 == 0x43d and fm1 == 0xfffffffffffff and fcsr == 0x40 and rm_val == 7
/* opcode: fcvt.w.d ; op1:f19; dest:x30; op1val:0x43dfffffffffffff; valaddr_reg:x1;
val_offset:17*FLEN/8; rmval:dyn; correctval:??; testreg:x7;
fcsr_val:64*/
TEST_FPID_OP(fcvt.w.d, x30, f19, dyn, 64, 0, x1, 17*FLEN/8, x16, x3, x7,FLREG)
inst_18:// rs1==f28, rd==x2,fs1 == 0 and fe1 == 0x43d and fm1 == 0xfffffffffffff and fcsr == 0x60 and rm_val == 7
/* opcode: fcvt.w.d ; op1:f28; dest:x2; op1val:0x43dfffffffffffff; valaddr_reg:x1;
val_offset:18*FLEN/8; rmval:dyn; correctval:??; testreg:x7;
fcsr_val:96*/
TEST_FPID_OP(fcvt.w.d, x2, f28, dyn, 96, 0, x1, 18*FLEN/8, x16, x3, x7,FLREG)
inst_19:// rs1==f5, rd==x21,fs1 == 0 and fe1 == 0x43d and fm1 == 0xfffffffffffff and fcsr == 0x80 and rm_val == 7
/* opcode: fcvt.w.d ; op1:f5; dest:x21; op1val:0x43dfffffffffffff; valaddr_reg:x1;
val_offset:19*FLEN/8; rmval:dyn; correctval:??; testreg:x7;
fcsr_val:128*/
TEST_FPID_OP(fcvt.w.d, x21, f5, dyn, 128, 0, x1, 19*FLEN/8, x16, x3, x7,FLREG)
inst_20:// rs1==f16, rd==x15,fs1 == 0 and fe1 == 0x43e and fm1 == 0x0000000000000 and fcsr == 0x0 and rm_val == 7
/* opcode: fcvt.w.d ; op1:f16; dest:x15; op1val:0x43e0000000000000; valaddr_reg:x1;
val_offset:20*FLEN/8; rmval:dyn; correctval:??; testreg:x7;
fcsr_val:0*/
TEST_FPID_OP(fcvt.w.d, x15, f16, dyn, 0, 0, x1, 20*FLEN/8, x16, x3, x7,FLREG)
inst_21:// rs1==f21, rd==x0,fs1 == 0 and fe1 == 0x43e and fm1 == 0x0000000000000 and fcsr == 0x20 and rm_val == 7
/* opcode: fcvt.w.d ; op1:f21; dest:x0; op1val:0x43e0000000000000; valaddr_reg:x1;
val_offset:21*FLEN/8; rmval:dyn; correctval:??; testreg:x7;
fcsr_val:32*/
TEST_FPID_OP(fcvt.w.d, x0, f21, dyn, 32, 0, x1, 21*FLEN/8, x16, x3, x7,FLREG)
inst_22:// rs1==f23, rd==x8,fs1 == 0 and fe1 == 0x43e and fm1 == 0x0000000000000 and fcsr == 0x40 and rm_val == 7
/* opcode: fcvt.w.d ; op1:f23; dest:x8; op1val:0x43e0000000000000; valaddr_reg:x1;
val_offset:22*FLEN/8; rmval:dyn; correctval:??; testreg:x7;
fcsr_val:64*/
TEST_FPID_OP(fcvt.w.d, x8, f23, dyn, 64, 0, x1, 22*FLEN/8, x16, x3, x7,FLREG)
inst_23:// rs1==f3, rd==x10,fs1 == 0 and fe1 == 0x43e and fm1 == 0x0000000000000 and fcsr == 0x60 and rm_val == 7
/* opcode: fcvt.w.d ; op1:f3; dest:x10; op1val:0x43e0000000000000; valaddr_reg:x1;
val_offset:23*FLEN/8; rmval:dyn; correctval:??; testreg:x7;
fcsr_val:96*/
TEST_FPID_OP(fcvt.w.d, x10, f3, dyn, 96, 0, x1, 23*FLEN/8, x16, x3, x7,FLREG)
inst_24:// rs1==f13, rd==x23,fs1 == 0 and fe1 == 0x43e and fm1 == 0x0000000000000 and fcsr == 0x80 and rm_val == 7
/* opcode: fcvt.w.d ; op1:f13; dest:x23; op1val:0x43e0000000000000; valaddr_reg:x1;
val_offset:24*FLEN/8; rmval:dyn; correctval:??; testreg:x7;
fcsr_val:128*/
TEST_FPID_OP(fcvt.w.d, x23, f13, dyn, 128, 0, x1, 24*FLEN/8, x16, x3, x7,FLREG)
RVTEST_VALBASEUPD(x4,test_dataset_1)
inst_25:// rs1==f15, rd==x1,fs1 == 0 and fe1 == 0x43e and fm1 == 0x0000000000001 and fcsr == 0x0 and rm_val == 7
/* opcode: fcvt.w.d ; op1:f15; dest:x1; op1val:0x43e0000000000001; valaddr_reg:x4;
val_offset:0*FLEN/8; rmval:dyn; correctval:??; testreg:x7;
fcsr_val:0*/
TEST_FPID_OP(fcvt.w.d, x1, f15, dyn, 0, 0, x4, 0*FLEN/8, x5, x3, x7,FLREG)
inst_26:// rs1==f11, rd==x16,fs1 == 0 and fe1 == 0x43e and fm1 == 0x0000000000001 and fcsr == 0x20 and rm_val == 7
/* opcode: fcvt.w.d ; op1:f11; dest:x16; op1val:0x43e0000000000001; valaddr_reg:x4;
val_offset:1*FLEN/8; rmval:dyn; correctval:??; testreg:x7;
fcsr_val:32*/
TEST_FPID_OP(fcvt.w.d, x16, f11, dyn, 32, 0, x4, 1*FLEN/8, x5, x3, x7,FLREG)
inst_27:// rs1==f8, rd==x19,fs1 == 0 and fe1 == 0x43e and fm1 == 0x0000000000001 and fcsr == 0x40 and rm_val == 7
/* opcode: fcvt.w.d ; op1:f8; dest:x19; op1val:0x43e0000000000001; valaddr_reg:x4;
val_offset:2*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
fcsr_val:64*/
TEST_FPID_OP(fcvt.w.d, x19, f8, dyn, 64, 0, x4, 2*FLEN/8, x5, x3, x2,FLREG)
RVTEST_SIGBASE(x1,signature_x1_0)
inst_28:// rs1==f7, rd==x26,fs1 == 0 and fe1 == 0x43e and fm1 == 0x0000000000001 and fcsr == 0x60 and rm_val == 7
/* opcode: fcvt.w.d ; op1:f7; dest:x26; op1val:0x43e0000000000001; valaddr_reg:x4;
val_offset:3*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
fcsr_val:96*/
TEST_FPID_OP(fcvt.w.d, x26, f7, dyn, 96, 0, x4, 3*FLEN/8, x5, x1, x2,FLREG)
inst_29:// rs1==f29, rd==x7,fs1 == 0 and fe1 == 0x43e and fm1 == 0x0000000000001 and fcsr == 0x80 and rm_val == 7
/* opcode: fcvt.w.d ; op1:f29; dest:x7; op1val:0x43e0000000000001; valaddr_reg:x4;
val_offset:4*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
fcsr_val:128*/
TEST_FPID_OP(fcvt.w.d, x7, f29, dyn, 128, 0, x4, 4*FLEN/8, x5, x1, x2,FLREG)
inst_30:// rs1==f22, rd==x3,fs1 == 0 and fe1 == 0x43e and fm1 == 0x0000000000002 and fcsr == 0x0 and rm_val == 7
/* opcode: fcvt.w.d ; op1:f22; dest:x3; op1val:0x43e0000000000002; valaddr_reg:x4;
val_offset:5*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
fcsr_val:0*/
TEST_FPID_OP(fcvt.w.d, x3, f22, dyn, 0, 0, x4, 5*FLEN/8, x5, x1, x2,FLREG)
inst_31:// rs1==f2, rd==x29,fs1 == 0 and fe1 == 0x43e and fm1 == 0x0000000000002 and fcsr == 0x20 and rm_val == 7
/* opcode: fcvt.w.d ; op1:f2; dest:x29; op1val:0x43e0000000000002; valaddr_reg:x4;
val_offset:6*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
fcsr_val:32*/
TEST_FPID_OP(fcvt.w.d, x29, f2, dyn, 32, 0, x4, 6*FLEN/8, x5, x1, x2,FLREG)
inst_32:// fs1 == 0 and fe1 == 0x43e and fm1 == 0x0000000000002 and fcsr == 0x40 and rm_val == 7
/* opcode: fcvt.w.d ; op1:f31; dest:x31; op1val:0x43e0000000000002; valaddr_reg:x4;
val_offset:7*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
fcsr_val:64*/
TEST_FPID_OP(fcvt.w.d, x31, f31, dyn, 64, 0, x4, 7*FLEN/8, x5, x1, x2,FLREG)
inst_33:// fs1 == 0 and fe1 == 0x43e and fm1 == 0x0000000000002 and fcsr == 0x60 and rm_val == 7
/* opcode: fcvt.w.d ; op1:f31; dest:x31; op1val:0x43e0000000000002; valaddr_reg:x4;
val_offset:8*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
fcsr_val:96*/
TEST_FPID_OP(fcvt.w.d, x31, f31, dyn, 96, 0, x4, 8*FLEN/8, x5, x1, x2,FLREG)
inst_34:// fs1 == 0 and fe1 == 0x43e and fm1 == 0x0000000000002 and fcsr == 0x80 and rm_val == 7
/* opcode: fcvt.w.d ; op1:f31; dest:x31; op1val:0x43e0000000000002; valaddr_reg:x4;
val_offset:9*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
fcsr_val:128*/
TEST_FPID_OP(fcvt.w.d, x31, f31, dyn, 128, 0, x4, 9*FLEN/8, x5, x1, x2,FLREG)
inst_35:// fs1 == 0 and fe1 == 0x43e and fm1 == 0x0000000000003 and fcsr == 0x0 and rm_val == 7
/* opcode: fcvt.w.d ; op1:f31; dest:x31; op1val:0x43e0000000000003; valaddr_reg:x4;
val_offset:10*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
fcsr_val:0*/
TEST_FPID_OP(fcvt.w.d, x31, f31, dyn, 0, 0, x4, 10*FLEN/8, x5, x1, x2,FLREG)
inst_36:// fs1 == 0 and fe1 == 0x43e and fm1 == 0x0000000000003 and fcsr == 0x20 and rm_val == 7
/* opcode: fcvt.w.d ; op1:f31; dest:x31; op1val:0x43e0000000000003; valaddr_reg:x4;
val_offset:11*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
fcsr_val:32*/
TEST_FPID_OP(fcvt.w.d, x31, f31, dyn, 32, 0, x4, 11*FLEN/8, x5, x1, x2,FLREG)
inst_37:// fs1 == 0 and fe1 == 0x43e and fm1 == 0x0000000000003 and fcsr == 0x40 and rm_val == 7
/* opcode: fcvt.w.d ; op1:f31; dest:x31; op1val:0x43e0000000000003; valaddr_reg:x4;
val_offset:12*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
fcsr_val:64*/
TEST_FPID_OP(fcvt.w.d, x31, f31, dyn, 64, 0, x4, 12*FLEN/8, x5, x1, x2,FLREG)
inst_38:// fs1 == 0 and fe1 == 0x43e and fm1 == 0x0000000000003 and fcsr == 0x60 and rm_val == 7
/* opcode: fcvt.w.d ; op1:f31; dest:x31; op1val:0x43e0000000000003; valaddr_reg:x4;
val_offset:13*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
fcsr_val:96*/
TEST_FPID_OP(fcvt.w.d, x31, f31, dyn, 96, 0, x4, 13*FLEN/8, x5, x1, x2,FLREG)
inst_39:// fs1 == 0 and fe1 == 0x43e and fm1 == 0x0000000000003 and fcsr == 0x80 and rm_val == 7
/* opcode: fcvt.w.d ; op1:f31; dest:x31; op1val:0x43e0000000000003; valaddr_reg:x4;
val_offset:14*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
fcsr_val:128*/
TEST_FPID_OP(fcvt.w.d, x31, f31, dyn, 128, 0, x4, 14*FLEN/8, x5, x1, x2,FLREG)
inst_40:// fs1 == 0 and fe1 == 0x43e and fm1 == 0x0000000000004 and fcsr == 0x0 and rm_val == 7
/* opcode: fcvt.w.d ; op1:f31; dest:x31; op1val:0x43e0000000000004; valaddr_reg:x4;
val_offset:15*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
fcsr_val:0*/
TEST_FPID_OP(fcvt.w.d, x31, f31, dyn, 0, 0, x4, 15*FLEN/8, x5, x1, x2,FLREG)
inst_41:// fs1 == 0 and fe1 == 0x43e and fm1 == 0x0000000000004 and fcsr == 0x20 and rm_val == 7
/* opcode: fcvt.w.d ; op1:f31; dest:x31; op1val:0x43e0000000000004; valaddr_reg:x4;
val_offset:16*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
fcsr_val:32*/
TEST_FPID_OP(fcvt.w.d, x31, f31, dyn, 32, 0, x4, 16*FLEN/8, x5, x1, x2,FLREG)
inst_42:// fs1 == 0 and fe1 == 0x43e and fm1 == 0x0000000000004 and fcsr == 0x40 and rm_val == 7
/* opcode: fcvt.w.d ; op1:f31; dest:x31; op1val:0x43e0000000000004; valaddr_reg:x4;
val_offset:17*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
fcsr_val:64*/
TEST_FPID_OP(fcvt.w.d, x31, f31, dyn, 64, 0, x4, 17*FLEN/8, x5, x1, x2,FLREG)
inst_43:// fs1 == 0 and fe1 == 0x43e and fm1 == 0x0000000000004 and fcsr == 0x60 and rm_val == 7
/* opcode: fcvt.w.d ; op1:f31; dest:x31; op1val:0x43e0000000000004; valaddr_reg:x4;
val_offset:18*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
fcsr_val:96*/
TEST_FPID_OP(fcvt.w.d, x31, f31, dyn, 96, 0, x4, 18*FLEN/8, x5, x1, x2,FLREG)
inst_44:// fs1 == 0 and fe1 == 0x43e and fm1 == 0x0000000000004 and fcsr == 0x80 and rm_val == 7
/* opcode: fcvt.w.d ; op1:f31; dest:x31; op1val:0x43e0000000000004; valaddr_reg:x4;
val_offset:19*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
fcsr_val:128*/
TEST_FPID_OP(fcvt.w.d, x31, f31, dyn, 128, 0, x4, 19*FLEN/8, x5, x1, x2,FLREG)
inst_45:// fs1 == 0 and fe1 == 0x43e and fm1 == 0x0000000000000 and fcsr == 0x20 and rm_val == 7
/* opcode: fcvt.w.d ; op1:f31; dest:x31; op1val:0x43e0000000000000; valaddr_reg:x4;
val_offset:20*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
fcsr_val:32*/
TEST_FPID_OP(fcvt.w.d, x31, f31, dyn, 32, 0, x4, 20*FLEN/8, x5, x1, x2,FLREG)
#endif
RVTEST_CODE_END
RVMODEL_HALT
RVTEST_DATA_BEGIN
.align 4
rvtest_data:
.word 0xbabecafe
.word 0xabecafeb
.word 0xbecafeba
.word 0xecafebab
test_dataset_0:
NAN_BOXED(4890909195324358652,64,FLEN)
NAN_BOXED(4890909195324358652,64,FLEN)
NAN_BOXED(4890909195324358652,64,FLEN)
NAN_BOXED(4890909195324358652,64,FLEN)
NAN_BOXED(4890909195324358652,64,FLEN)
NAN_BOXED(4890909195324358653,64,FLEN)
NAN_BOXED(4890909195324358653,64,FLEN)
NAN_BOXED(4890909195324358653,64,FLEN)
NAN_BOXED(4890909195324358653,64,FLEN)
NAN_BOXED(4890909195324358653,64,FLEN)
NAN_BOXED(4890909195324358654,64,FLEN)
NAN_BOXED(4890909195324358654,64,FLEN)
NAN_BOXED(4890909195324358654,64,FLEN)
NAN_BOXED(4890909195324358654,64,FLEN)
NAN_BOXED(4890909195324358654,64,FLEN)
NAN_BOXED(4890909195324358655,64,FLEN)
NAN_BOXED(4890909195324358655,64,FLEN)
NAN_BOXED(4890909195324358655,64,FLEN)
NAN_BOXED(4890909195324358655,64,FLEN)
NAN_BOXED(4890909195324358655,64,FLEN)
NAN_BOXED(4890909195324358656,64,FLEN)
NAN_BOXED(4890909195324358656,64,FLEN)
NAN_BOXED(4890909195324358656,64,FLEN)
NAN_BOXED(4890909195324358656,64,FLEN)
NAN_BOXED(4890909195324358656,64,FLEN)
test_dataset_1:
NAN_BOXED(4890909195324358657,64,FLEN)
NAN_BOXED(4890909195324358657,64,FLEN)
NAN_BOXED(4890909195324358657,64,FLEN)
NAN_BOXED(4890909195324358657,64,FLEN)
NAN_BOXED(4890909195324358657,64,FLEN)
NAN_BOXED(4890909195324358658,64,FLEN)
NAN_BOXED(4890909195324358658,64,FLEN)
NAN_BOXED(4890909195324358658,64,FLEN)
NAN_BOXED(4890909195324358658,64,FLEN)
NAN_BOXED(4890909195324358658,64,FLEN)
NAN_BOXED(4890909195324358659,64,FLEN)
NAN_BOXED(4890909195324358659,64,FLEN)
NAN_BOXED(4890909195324358659,64,FLEN)
NAN_BOXED(4890909195324358659,64,FLEN)
NAN_BOXED(4890909195324358659,64,FLEN)
NAN_BOXED(4890909195324358660,64,FLEN)
NAN_BOXED(4890909195324358660,64,FLEN)
NAN_BOXED(4890909195324358660,64,FLEN)
NAN_BOXED(4890909195324358660,64,FLEN)
NAN_BOXED(4890909195324358660,64,FLEN)
NAN_BOXED(4890909195324358656,64,FLEN)
RVTEST_DATA_END
RVMODEL_DATA_BEGIN
rvtest_sig_begin:
sig_begin_canary:
CANARY;
signature_x3_0:
.fill 0*((SIGALIGN)/4),4,0xdeadbeef
signature_x3_1:
.fill 56*((SIGALIGN)/4),4,0xdeadbeef
signature_x1_0:
.fill 36*((SIGALIGN)/4),4,0xdeadbeef
#ifdef rvtest_mtrap_routine
tsig_begin_canary:
CANARY;
tsig_begin_canary:
CANARY;
mtrap_sigptr:
.fill 64*(XLEN/32),4,0xdeadbeef
tsig_end_canary:
CANARY;
tsig_end_canary:
CANARY;
#endif
#ifdef rvtest_gpr_save
gpr_save:
.fill 32*XLEN/32,4,0xdeadbeef
#endif
sig_end_canary:
CANARY;
rvtest_sig_end:
RVMODEL_DATA_END

841
vendor/riscv-arch-tests/riscv-test-suite/rv32i_m/D/src/fcvt.w.d_b24-01.S vendored
View file

@ -1,841 +0,0 @@
// -----------
// This file was generated by riscv_ctg (https://github.com/riscv-software-src/riscv-ctg)
// version : 0.7.1
// timestamp : Fri Jun 17 14:03:36 2022 GMT
// usage : riscv_ctg \
// -- cgf // --cgf /scratch/pawan/work/normalised/RV32D/fcvt.w.d.cgf \
\
// -- xlen 32 \
// --randomize \
// -----------
//
// -----------
// Copyright (c) 2020. RISC-V International. All rights reserved.
// SPDX-License-Identifier: BSD-3-Clause
// -----------
//
// This assembly file tests the fcvt.w.d instruction of the RISC-V RV32FD_Zicsr,RV64FD_Zicsr extension for the fcvt.w.d_b24 covergroup.
//
#include "model_test.h"
#include "arch_test.h"
RVTEST_ISA("RV32IFD_Zicsr,RV64IFD_Zicsr")
.section .text.init
.org 0x80
.globl rvtest_entry_point
rvtest_entry_point:
RVMODEL_BOOT
RVTEST_CODE_BEGIN
#ifdef TEST_CASE_1
RVTEST_CASE(0,"//check ISA:=regex(.*I.*D.*);def TEST_CASE_1=True;",fcvt.w.d_b24)
RVTEST_FP_ENABLE()
RVTEST_VALBASEUPD(x3,test_dataset_0)
RVTEST_SIGBASE(x9,signature_x9_1)
inst_0:// rs1==f21, rd==x19,fs1 == 0 and fe1 == 0x000 and fm1 == 0x0000000000000 and fcsr == 0x0 and rm_val == 7
/* opcode: fcvt.w.d ; op1:f21; dest:x19; op1val:0x0; valaddr_reg:x3;
val_offset:0*FLEN/8; rmval:dyn; correctval:??; testreg:x12;
fcsr_val:0*/
TEST_FPID_OP(fcvt.w.d, x19, f21, dyn, 0, 0, x3, 0*FLEN/8, x13, x9, x12,FLREG)
inst_1:// rs1==f5, rd==x7,fs1 == 0 and fe1 == 0x000 and fm1 == 0x0000000000000 and fcsr == 0x20 and rm_val == 7
/* opcode: fcvt.w.d ; op1:f5; dest:x7; op1val:0x0; valaddr_reg:x3;
val_offset:1*FLEN/8; rmval:dyn; correctval:??; testreg:x12;
fcsr_val:32*/
TEST_FPID_OP(fcvt.w.d, x7, f5, dyn, 32, 0, x3, 1*FLEN/8, x13, x9, x12,FLREG)
inst_2:// rs1==f7, rd==x6,fs1 == 0 and fe1 == 0x000 and fm1 == 0x0000000000000 and fcsr == 0x40 and rm_val == 7
/* opcode: fcvt.w.d ; op1:f7; dest:x6; op1val:0x0; valaddr_reg:x3;
val_offset:2*FLEN/8; rmval:dyn; correctval:??; testreg:x12;
fcsr_val:64*/
TEST_FPID_OP(fcvt.w.d, x6, f7, dyn, 64, 0, x3, 2*FLEN/8, x13, x9, x12,FLREG)
inst_3:// rs1==f3, rd==x24,fs1 == 0 and fe1 == 0x000 and fm1 == 0x0000000000000 and fcsr == 0x60 and rm_val == 7
/* opcode: fcvt.w.d ; op1:f3; dest:x24; op1val:0x0; valaddr_reg:x3;
val_offset:3*FLEN/8; rmval:dyn; correctval:??; testreg:x12;
fcsr_val:96*/
TEST_FPID_OP(fcvt.w.d, x24, f3, dyn, 96, 0, x3, 3*FLEN/8, x13, x9, x12,FLREG)
inst_4:// rs1==f13, rd==x22,fs1 == 0 and fe1 == 0x000 and fm1 == 0x0000000000000 and fcsr == 0x80 and rm_val == 7
/* opcode: fcvt.w.d ; op1:f13; dest:x22; op1val:0x0; valaddr_reg:x3;
val_offset:4*FLEN/8; rmval:dyn; correctval:??; testreg:x12;
fcsr_val:128*/
TEST_FPID_OP(fcvt.w.d, x22, f13, dyn, 128, 0, x3, 4*FLEN/8, x13, x9, x12,FLREG)
inst_5:// rs1==f6, rd==x31,fs1 == 0 and fe1 == 0x3f8 and fm1 == 0x47ae147ae147b and fcsr == 0x0 and rm_val == 7
/* opcode: fcvt.w.d ; op1:f6; dest:x31; op1val:0x3f847ae147ae147b; valaddr_reg:x3;
val_offset:5*FLEN/8; rmval:dyn; correctval:??; testreg:x12;
fcsr_val:0*/
TEST_FPID_OP(fcvt.w.d, x31, f6, dyn, 0, 0, x3, 5*FLEN/8, x13, x9, x12,FLREG)
inst_6:// rs1==f26, rd==x4,fs1 == 0 and fe1 == 0x3f8 and fm1 == 0x47ae147ae147b and fcsr == 0x20 and rm_val == 7
/* opcode: fcvt.w.d ; op1:f26; dest:x4; op1val:0x3f847ae147ae147b; valaddr_reg:x3;
val_offset:6*FLEN/8; rmval:dyn; correctval:??; testreg:x12;
fcsr_val:32*/
TEST_FPID_OP(fcvt.w.d, x4, f26, dyn, 32, 0, x3, 6*FLEN/8, x13, x9, x12,FLREG)
inst_7:// rs1==f9, rd==x10,fs1 == 0 and fe1 == 0x3f8 and fm1 == 0x47ae147ae147b and fcsr == 0x40 and rm_val == 7
/* opcode: fcvt.w.d ; op1:f9; dest:x10; op1val:0x3f847ae147ae147b; valaddr_reg:x3;
val_offset:7*FLEN/8; rmval:dyn; correctval:??; testreg:x12;
fcsr_val:64*/
TEST_FPID_OP(fcvt.w.d, x10, f9, dyn, 64, 0, x3, 7*FLEN/8, x13, x9, x12,FLREG)
inst_8:// rs1==f15, rd==x2,fs1 == 0 and fe1 == 0x3f8 and fm1 == 0x47ae147ae147b and fcsr == 0x60 and rm_val == 7
/* opcode: fcvt.w.d ; op1:f15; dest:x2; op1val:0x3f847ae147ae147b; valaddr_reg:x3;
val_offset:8*FLEN/8; rmval:dyn; correctval:??; testreg:x12;
fcsr_val:96*/
TEST_FPID_OP(fcvt.w.d, x2, f15, dyn, 96, 0, x3, 8*FLEN/8, x13, x9, x12,FLREG)
inst_9:// rs1==f11, rd==x18,fs1 == 0 and fe1 == 0x3f8 and fm1 == 0x47ae147ae147b and fcsr == 0x80 and rm_val == 7
/* opcode: fcvt.w.d ; op1:f11; dest:x18; op1val:0x3f847ae147ae147b; valaddr_reg:x3;
val_offset:9*FLEN/8; rmval:dyn; correctval:??; testreg:x12;
fcsr_val:128*/
TEST_FPID_OP(fcvt.w.d, x18, f11, dyn, 128, 0, x3, 9*FLEN/8, x13, x9, x12,FLREG)
inst_10:// rs1==f16, rd==x20,fs1 == 0 and fe1 == 0x3fb and fm1 == 0x999999999999a and fcsr == 0x0 and rm_val == 7
/* opcode: fcvt.w.d ; op1:f16; dest:x20; op1val:0x3fb999999999999a; valaddr_reg:x3;
val_offset:10*FLEN/8; rmval:dyn; correctval:??; testreg:x12;
fcsr_val:0*/
TEST_FPID_OP(fcvt.w.d, x20, f16, dyn, 0, 0, x3, 10*FLEN/8, x13, x9, x12,FLREG)
inst_11:// rs1==f1, rd==x28,fs1 == 0 and fe1 == 0x3fb and fm1 == 0x999999999999a and fcsr == 0x20 and rm_val == 7
/* opcode: fcvt.w.d ; op1:f1; dest:x28; op1val:0x3fb999999999999a; valaddr_reg:x3;
val_offset:11*FLEN/8; rmval:dyn; correctval:??; testreg:x12;
fcsr_val:32*/
TEST_FPID_OP(fcvt.w.d, x28, f1, dyn, 32, 0, x3, 11*FLEN/8, x13, x9, x12,FLREG)
inst_12:// rs1==f29, rd==x17,fs1 == 0 and fe1 == 0x3fb and fm1 == 0x999999999999a and fcsr == 0x40 and rm_val == 7
/* opcode: fcvt.w.d ; op1:f29; dest:x17; op1val:0x3fb999999999999a; valaddr_reg:x3;
val_offset:12*FLEN/8; rmval:dyn; correctval:??; testreg:x12;
fcsr_val:64*/
TEST_FPID_OP(fcvt.w.d, x17, f29, dyn, 64, 0, x3, 12*FLEN/8, x13, x9, x12,FLREG)
inst_13:// rs1==f8, rd==x14,fs1 == 0 and fe1 == 0x3fb and fm1 == 0x999999999999a and fcsr == 0x60 and rm_val == 7
/* opcode: fcvt.w.d ; op1:f8; dest:x14; op1val:0x3fb999999999999a; valaddr_reg:x3;
val_offset:13*FLEN/8; rmval:dyn; correctval:??; testreg:x12;
fcsr_val:96*/
TEST_FPID_OP(fcvt.w.d, x14, f8, dyn, 96, 0, x3, 13*FLEN/8, x13, x9, x12,FLREG)
inst_14:// rs1==f12, rd==x30,fs1 == 0 and fe1 == 0x3fb and fm1 == 0x999999999999a and fcsr == 0x80 and rm_val == 7
/* opcode: fcvt.w.d ; op1:f12; dest:x30; op1val:0x3fb999999999999a; valaddr_reg:x3;
val_offset:14*FLEN/8; rmval:dyn; correctval:??; testreg:x12;
fcsr_val:128*/
TEST_FPID_OP(fcvt.w.d, x30, f12, dyn, 128, 0, x3, 14*FLEN/8, x13, x9, x12,FLREG)
inst_15:// rs1==f10, rd==x1,fs1 == 0 and fe1 == 0x3fb and fm1 == 0xc28f5c28f5c29 and fcsr == 0x0 and rm_val == 7
/* opcode: fcvt.w.d ; op1:f10; dest:x1; op1val:0x3fbc28f5c28f5c29; valaddr_reg:x3;
val_offset:15*FLEN/8; rmval:dyn; correctval:??; testreg:x12;
fcsr_val:0*/
TEST_FPID_OP(fcvt.w.d, x1, f10, dyn, 0, 0, x3, 15*FLEN/8, x13, x9, x12,FLREG)
inst_16:// rs1==f14, rd==x8,fs1 == 0 and fe1 == 0x3fb and fm1 == 0xc28f5c28f5c29 and fcsr == 0x20 and rm_val == 7
/* opcode: fcvt.w.d ; op1:f14; dest:x8; op1val:0x3fbc28f5c28f5c29; valaddr_reg:x3;
val_offset:16*FLEN/8; rmval:dyn; correctval:??; testreg:x12;
fcsr_val:32*/
TEST_FPID_OP(fcvt.w.d, x8, f14, dyn, 32, 0, x3, 16*FLEN/8, x13, x9, x12,FLREG)
inst_17:// rs1==f4, rd==x11,fs1 == 0 and fe1 == 0x3fb and fm1 == 0xc28f5c28f5c29 and fcsr == 0x40 and rm_val == 7
/* opcode: fcvt.w.d ; op1:f4; dest:x11; op1val:0x3fbc28f5c28f5c29; valaddr_reg:x3;
val_offset:17*FLEN/8; rmval:dyn; correctval:??; testreg:x12;
fcsr_val:64*/
TEST_FPID_OP(fcvt.w.d, x11, f4, dyn, 64, 0, x3, 17*FLEN/8, x13, x9, x12,FLREG)
inst_18:// rs1==f31, rd==x21,fs1 == 0 and fe1 == 0x3fb and fm1 == 0xc28f5c28f5c29 and fcsr == 0x60 and rm_val == 7
/* opcode: fcvt.w.d ; op1:f31; dest:x21; op1val:0x3fbc28f5c28f5c29; valaddr_reg:x3;
val_offset:18*FLEN/8; rmval:dyn; correctval:??; testreg:x12;
fcsr_val:96*/
TEST_FPID_OP(fcvt.w.d, x21, f31, dyn, 96, 0, x3, 18*FLEN/8, x13, x9, x12,FLREG)
inst_19:// rs1==f27, rd==x5,fs1 == 0 and fe1 == 0x3fb and fm1 == 0xc28f5c28f5c29 and fcsr == 0x80 and rm_val == 7
/* opcode: fcvt.w.d ; op1:f27; dest:x5; op1val:0x3fbc28f5c28f5c29; valaddr_reg:x3;
val_offset:19*FLEN/8; rmval:dyn; correctval:??; testreg:x12;
fcsr_val:128*/
TEST_FPID_OP(fcvt.w.d, x5, f27, dyn, 128, 0, x3, 19*FLEN/8, x13, x9, x12,FLREG)
inst_20:// rs1==f17, rd==x27,fs1 == 0 and fe1 == 0x3fe and fm1 == 0xc7ae147ae147b and fcsr == 0x0 and rm_val == 7
/* opcode: fcvt.w.d ; op1:f17; dest:x27; op1val:0x3fec7ae147ae147b; valaddr_reg:x3;
val_offset:20*FLEN/8; rmval:dyn; correctval:??; testreg:x12;
fcsr_val:0*/
TEST_FPID_OP(fcvt.w.d, x27, f17, dyn, 0, 0, x3, 20*FLEN/8, x13, x9, x12,FLREG)
inst_21:// rs1==f18, rd==x23,fs1 == 0 and fe1 == 0x3fe and fm1 == 0xc7ae147ae147b and fcsr == 0x20 and rm_val == 7
/* opcode: fcvt.w.d ; op1:f18; dest:x23; op1val:0x3fec7ae147ae147b; valaddr_reg:x3;
val_offset:21*FLEN/8; rmval:dyn; correctval:??; testreg:x12;
fcsr_val:32*/
TEST_FPID_OP(fcvt.w.d, x23, f18, dyn, 32, 0, x3, 21*FLEN/8, x13, x9, x12,FLREG)
inst_22:// rs1==f2, rd==x16,fs1 == 0 and fe1 == 0x3fe and fm1 == 0xc7ae147ae147b and fcsr == 0x40 and rm_val == 7
/* opcode: fcvt.w.d ; op1:f2; dest:x16; op1val:0x3fec7ae147ae147b; valaddr_reg:x3;
val_offset:22*FLEN/8; rmval:dyn; correctval:??; testreg:x12;
fcsr_val:64*/
TEST_FPID_OP(fcvt.w.d, x16, f2, dyn, 64, 0, x3, 22*FLEN/8, x13, x9, x12,FLREG)
inst_23:// rs1==f0, rd==x29,fs1 == 0 and fe1 == 0x3fe and fm1 == 0xc7ae147ae147b and fcsr == 0x60 and rm_val == 7
/* opcode: fcvt.w.d ; op1:f0; dest:x29; op1val:0x3fec7ae147ae147b; valaddr_reg:x3;
val_offset:23*FLEN/8; rmval:dyn; correctval:??; testreg:x12;
fcsr_val:96*/
TEST_FPID_OP(fcvt.w.d, x29, f0, dyn, 96, 0, x3, 23*FLEN/8, x13, x9, x12,FLREG)
RVTEST_VALBASEUPD(x4,test_dataset_1)
inst_24:// rs1==f24, rd==x3,fs1 == 0 and fe1 == 0x3fe and fm1 == 0xc7ae147ae147b and fcsr == 0x80 and rm_val == 7
/* opcode: fcvt.w.d ; op1:f24; dest:x3; op1val:0x3fec7ae147ae147b; valaddr_reg:x4;
val_offset:0*FLEN/8; rmval:dyn; correctval:??; testreg:x12;
fcsr_val:128*/
TEST_FPID_OP(fcvt.w.d, x3, f24, dyn, 128, 0, x4, 0*FLEN/8, x5, x9, x12,FLREG)
inst_25:// rs1==f23, rd==x26,fs1 == 0 and fe1 == 0x3fe and fm1 == 0xccccccccccccd and fcsr == 0x0 and rm_val == 7
/* opcode: fcvt.w.d ; op1:f23; dest:x26; op1val:0x3feccccccccccccd; valaddr_reg:x4;
val_offset:1*FLEN/8; rmval:dyn; correctval:??; testreg:x12;
fcsr_val:0*/
TEST_FPID_OP(fcvt.w.d, x26, f23, dyn, 0, 0, x4, 1*FLEN/8, x5, x9, x12,FLREG)
inst_26:// rs1==f28, rd==x12,fs1 == 0 and fe1 == 0x3fe and fm1 == 0xccccccccccccd and fcsr == 0x20 and rm_val == 7
/* opcode: fcvt.w.d ; op1:f28; dest:x12; op1val:0x3feccccccccccccd; valaddr_reg:x4;
val_offset:2*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
fcsr_val:32*/
TEST_FPID_OP(fcvt.w.d, x12, f28, dyn, 32, 0, x4, 2*FLEN/8, x5, x9, x2,FLREG)
RVTEST_SIGBASE(x1,signature_x1_0)
inst_27:// rs1==f19, rd==x0,fs1 == 0 and fe1 == 0x3fe and fm1 == 0xccccccccccccd and fcsr == 0x40 and rm_val == 7
/* opcode: fcvt.w.d ; op1:f19; dest:x0; op1val:0x3feccccccccccccd; valaddr_reg:x4;
val_offset:3*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
fcsr_val:64*/
TEST_FPID_OP(fcvt.w.d, x0, f19, dyn, 64, 0, x4, 3*FLEN/8, x5, x1, x2,FLREG)
inst_28:// rs1==f25, rd==x13,fs1 == 0 and fe1 == 0x3fe and fm1 == 0xccccccccccccd and fcsr == 0x60 and rm_val == 7
/* opcode: fcvt.w.d ; op1:f25; dest:x13; op1val:0x3feccccccccccccd; valaddr_reg:x4;
val_offset:4*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
fcsr_val:96*/
TEST_FPID_OP(fcvt.w.d, x13, f25, dyn, 96, 0, x4, 4*FLEN/8, x5, x1, x2,FLREG)
inst_29:// rs1==f22, rd==x25,fs1 == 0 and fe1 == 0x3fe and fm1 == 0xccccccccccccd and fcsr == 0x80 and rm_val == 7
/* opcode: fcvt.w.d ; op1:f22; dest:x25; op1val:0x3feccccccccccccd; valaddr_reg:x4;
val_offset:5*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
fcsr_val:128*/
TEST_FPID_OP(fcvt.w.d, x25, f22, dyn, 128, 0, x4, 5*FLEN/8, x5, x1, x2,FLREG)
inst_30:// rs1==f20, rd==x9,fs1 == 0 and fe1 == 0x3fe and fm1 == 0xfae147ae147ae and fcsr == 0x0 and rm_val == 7
/* opcode: fcvt.w.d ; op1:f20; dest:x9; op1val:0x3fefae147ae147ae; valaddr_reg:x4;
val_offset:6*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
fcsr_val:0*/
TEST_FPID_OP(fcvt.w.d, x9, f20, dyn, 0, 0, x4, 6*FLEN/8, x5, x1, x2,FLREG)
inst_31:// rs1==f30, rd==x15,fs1 == 0 and fe1 == 0x3fe and fm1 == 0xfae147ae147ae and fcsr == 0x20 and rm_val == 7
/* opcode: fcvt.w.d ; op1:f30; dest:x15; op1val:0x3fefae147ae147ae; valaddr_reg:x4;
val_offset:7*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
fcsr_val:32*/
TEST_FPID_OP(fcvt.w.d, x15, f30, dyn, 32, 0, x4, 7*FLEN/8, x5, x1, x2,FLREG)
inst_32:// fs1 == 0 and fe1 == 0x3fe and fm1 == 0xfae147ae147ae and fcsr == 0x40 and rm_val == 7
/* opcode: fcvt.w.d ; op1:f31; dest:x31; op1val:0x3fefae147ae147ae; valaddr_reg:x4;
val_offset:8*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
fcsr_val:64*/
TEST_FPID_OP(fcvt.w.d, x31, f31, dyn, 64, 0, x4, 8*FLEN/8, x5, x1, x2,FLREG)
inst_33:// fs1 == 0 and fe1 == 0x3fe and fm1 == 0xfae147ae147ae and fcsr == 0x60 and rm_val == 7
/* opcode: fcvt.w.d ; op1:f31; dest:x31; op1val:0x3fefae147ae147ae; valaddr_reg:x4;
val_offset:9*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
fcsr_val:96*/
TEST_FPID_OP(fcvt.w.d, x31, f31, dyn, 96, 0, x4, 9*FLEN/8, x5, x1, x2,FLREG)
inst_34:// fs1 == 0 and fe1 == 0x3fe and fm1 == 0xfae147ae147ae and fcsr == 0x80 and rm_val == 7
/* opcode: fcvt.w.d ; op1:f31; dest:x31; op1val:0x3fefae147ae147ae; valaddr_reg:x4;
val_offset:10*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
fcsr_val:128*/
TEST_FPID_OP(fcvt.w.d, x31, f31, dyn, 128, 0, x4, 10*FLEN/8, x5, x1, x2,FLREG)
inst_35:// fs1 == 0 and fe1 == 0x3ff and fm1 == 0x0000000000000 and fcsr == 0x0 and rm_val == 7
/* opcode: fcvt.w.d ; op1:f31; dest:x31; op1val:0x3ff0000000000000; valaddr_reg:x4;
val_offset:11*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
fcsr_val:0*/
TEST_FPID_OP(fcvt.w.d, x31, f31, dyn, 0, 0, x4, 11*FLEN/8, x5, x1, x2,FLREG)
inst_36:// fs1 == 0 and fe1 == 0x3ff and fm1 == 0x0000000000000 and fcsr == 0x20 and rm_val == 7
/* opcode: fcvt.w.d ; op1:f31; dest:x31; op1val:0x3ff0000000000000; valaddr_reg:x4;
val_offset:12*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
fcsr_val:32*/
TEST_FPID_OP(fcvt.w.d, x31, f31, dyn, 32, 0, x4, 12*FLEN/8, x5, x1, x2,FLREG)
inst_37:// fs1 == 0 and fe1 == 0x3ff and fm1 == 0x0000000000000 and fcsr == 0x40 and rm_val == 7
/* opcode: fcvt.w.d ; op1:f31; dest:x31; op1val:0x3ff0000000000000; valaddr_reg:x4;
val_offset:13*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
fcsr_val:64*/
TEST_FPID_OP(fcvt.w.d, x31, f31, dyn, 64, 0, x4, 13*FLEN/8, x5, x1, x2,FLREG)
inst_38:// fs1 == 0 and fe1 == 0x3ff and fm1 == 0x0000000000000 and fcsr == 0x60 and rm_val == 7
/* opcode: fcvt.w.d ; op1:f31; dest:x31; op1val:0x3ff0000000000000; valaddr_reg:x4;
val_offset:14*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
fcsr_val:96*/
TEST_FPID_OP(fcvt.w.d, x31, f31, dyn, 96, 0, x4, 14*FLEN/8, x5, x1, x2,FLREG)
inst_39:// fs1 == 0 and fe1 == 0x3ff and fm1 == 0x0000000000000 and fcsr == 0x80 and rm_val == 7
/* opcode: fcvt.w.d ; op1:f31; dest:x31; op1val:0x3ff0000000000000; valaddr_reg:x4;
val_offset:15*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
fcsr_val:128*/
TEST_FPID_OP(fcvt.w.d, x31, f31, dyn, 128, 0, x4, 15*FLEN/8, x5, x1, x2,FLREG)
inst_40:// fs1 == 0 and fe1 == 0x3ff and fm1 == 0x028f5c28f5c29 and fcsr == 0x0 and rm_val == 7
/* opcode: fcvt.w.d ; op1:f31; dest:x31; op1val:0x3ff028f5c28f5c29; valaddr_reg:x4;
val_offset:16*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
fcsr_val:0*/
TEST_FPID_OP(fcvt.w.d, x31, f31, dyn, 0, 0, x4, 16*FLEN/8, x5, x1, x2,FLREG)
inst_41:// fs1 == 0 and fe1 == 0x3ff and fm1 == 0x028f5c28f5c29 and fcsr == 0x20 and rm_val == 7
/* opcode: fcvt.w.d ; op1:f31; dest:x31; op1val:0x3ff028f5c28f5c29; valaddr_reg:x4;
val_offset:17*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
fcsr_val:32*/
TEST_FPID_OP(fcvt.w.d, x31, f31, dyn, 32, 0, x4, 17*FLEN/8, x5, x1, x2,FLREG)
inst_42:// fs1 == 0 and fe1 == 0x3ff and fm1 == 0x028f5c28f5c29 and fcsr == 0x40 and rm_val == 7
/* opcode: fcvt.w.d ; op1:f31; dest:x31; op1val:0x3ff028f5c28f5c29; valaddr_reg:x4;
val_offset:18*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
fcsr_val:64*/
TEST_FPID_OP(fcvt.w.d, x31, f31, dyn, 64, 0, x4, 18*FLEN/8, x5, x1, x2,FLREG)
inst_43:// fs1 == 0 and fe1 == 0x3ff and fm1 == 0x028f5c28f5c29 and fcsr == 0x60 and rm_val == 7
/* opcode: fcvt.w.d ; op1:f31; dest:x31; op1val:0x3ff028f5c28f5c29; valaddr_reg:x4;
val_offset:19*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
fcsr_val:96*/
TEST_FPID_OP(fcvt.w.d, x31, f31, dyn, 96, 0, x4, 19*FLEN/8, x5, x1, x2,FLREG)
inst_44:// fs1 == 0 and fe1 == 0x3ff and fm1 == 0x028f5c28f5c29 and fcsr == 0x80 and rm_val == 7
/* opcode: fcvt.w.d ; op1:f31; dest:x31; op1val:0x3ff028f5c28f5c29; valaddr_reg:x4;
val_offset:20*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
fcsr_val:128*/
TEST_FPID_OP(fcvt.w.d, x31, f31, dyn, 128, 0, x4, 20*FLEN/8, x5, x1, x2,FLREG)
inst_45:// fs1 == 0 and fe1 == 0x3ff and fm1 == 0x199999999999a and fcsr == 0x0 and rm_val == 7
/* opcode: fcvt.w.d ; op1:f31; dest:x31; op1val:0x3ff199999999999a; valaddr_reg:x4;
val_offset:21*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
fcsr_val:0*/
TEST_FPID_OP(fcvt.w.d, x31, f31, dyn, 0, 0, x4, 21*FLEN/8, x5, x1, x2,FLREG)
inst_46:// fs1 == 0 and fe1 == 0x3ff and fm1 == 0x199999999999a and fcsr == 0x20 and rm_val == 7
/* opcode: fcvt.w.d ; op1:f31; dest:x31; op1val:0x3ff199999999999a; valaddr_reg:x4;
val_offset:22*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
fcsr_val:32*/
TEST_FPID_OP(fcvt.w.d, x31, f31, dyn, 32, 0, x4, 22*FLEN/8, x5, x1, x2,FLREG)
inst_47:// fs1 == 0 and fe1 == 0x3ff and fm1 == 0x199999999999a and fcsr == 0x40 and rm_val == 7
/* opcode: fcvt.w.d ; op1:f31; dest:x31; op1val:0x3ff199999999999a; valaddr_reg:x4;
val_offset:23*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
fcsr_val:64*/
TEST_FPID_OP(fcvt.w.d, x31, f31, dyn, 64, 0, x4, 23*FLEN/8, x5, x1, x2,FLREG)
inst_48:// fs1 == 0 and fe1 == 0x3ff and fm1 == 0x199999999999a and fcsr == 0x60 and rm_val == 7
/* opcode: fcvt.w.d ; op1:f31; dest:x31; op1val:0x3ff199999999999a; valaddr_reg:x4;
val_offset:24*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
fcsr_val:96*/
TEST_FPID_OP(fcvt.w.d, x31, f31, dyn, 96, 0, x4, 24*FLEN/8, x5, x1, x2,FLREG)
inst_49:// fs1 == 0 and fe1 == 0x3ff and fm1 == 0x199999999999a and fcsr == 0x80 and rm_val == 7
/* opcode: fcvt.w.d ; op1:f31; dest:x31; op1val:0x3ff199999999999a; valaddr_reg:x4;
val_offset:25*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
fcsr_val:128*/
TEST_FPID_OP(fcvt.w.d, x31, f31, dyn, 128, 0, x4, 25*FLEN/8, x5, x1, x2,FLREG)
inst_50:// fs1 == 0 and fe1 == 0x3ff and fm1 == 0x1c28f5c28f5c3 and fcsr == 0x0 and rm_val == 7
/* opcode: fcvt.w.d ; op1:f31; dest:x31; op1val:0x3ff1c28f5c28f5c3; valaddr_reg:x4;
val_offset:26*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
fcsr_val:0*/
TEST_FPID_OP(fcvt.w.d, x31, f31, dyn, 0, 0, x4, 26*FLEN/8, x5, x1, x2,FLREG)
inst_51:// fs1 == 0 and fe1 == 0x3ff and fm1 == 0x1c28f5c28f5c3 and fcsr == 0x20 and rm_val == 7
/* opcode: fcvt.w.d ; op1:f31; dest:x31; op1val:0x3ff1c28f5c28f5c3; valaddr_reg:x4;
val_offset:27*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
fcsr_val:32*/
TEST_FPID_OP(fcvt.w.d, x31, f31, dyn, 32, 0, x4, 27*FLEN/8, x5, x1, x2,FLREG)
inst_52:// fs1 == 0 and fe1 == 0x3ff and fm1 == 0x1c28f5c28f5c3 and fcsr == 0x40 and rm_val == 7
/* opcode: fcvt.w.d ; op1:f31; dest:x31; op1val:0x3ff1c28f5c28f5c3; valaddr_reg:x4;
val_offset:28*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
fcsr_val:64*/
TEST_FPID_OP(fcvt.w.d, x31, f31, dyn, 64, 0, x4, 28*FLEN/8, x5, x1, x2,FLREG)
inst_53:// fs1 == 0 and fe1 == 0x3ff and fm1 == 0x1c28f5c28f5c3 and fcsr == 0x60 and rm_val == 7
/* opcode: fcvt.w.d ; op1:f31; dest:x31; op1val:0x3ff1c28f5c28f5c3; valaddr_reg:x4;
val_offset:29*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
fcsr_val:96*/
TEST_FPID_OP(fcvt.w.d, x31, f31, dyn, 96, 0, x4, 29*FLEN/8, x5, x1, x2,FLREG)
inst_54:// fs1 == 0 and fe1 == 0x3ff and fm1 == 0x1c28f5c28f5c3 and fcsr == 0x80 and rm_val == 7
/* opcode: fcvt.w.d ; op1:f31; dest:x31; op1val:0x3ff1c28f5c28f5c3; valaddr_reg:x4;
val_offset:30*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
fcsr_val:128*/
TEST_FPID_OP(fcvt.w.d, x31, f31, dyn, 128, 0, x4, 30*FLEN/8, x5, x1, x2,FLREG)
inst_55:// fs1 == 1 and fe1 == 0x3f8 and fm1 == 0x47ae147ae147b and fcsr == 0x0 and rm_val == 7
/* opcode: fcvt.w.d ; op1:f31; dest:x31; op1val:0xbf847ae147ae147b; valaddr_reg:x4;
val_offset:31*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
fcsr_val:0*/
TEST_FPID_OP(fcvt.w.d, x31, f31, dyn, 0, 0, x4, 31*FLEN/8, x5, x1, x2,FLREG)
inst_56:// fs1 == 1 and fe1 == 0x3f8 and fm1 == 0x47ae147ae147b and fcsr == 0x20 and rm_val == 7
/* opcode: fcvt.w.d ; op1:f31; dest:x31; op1val:0xbf847ae147ae147b; valaddr_reg:x4;
val_offset:32*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
fcsr_val:32*/
TEST_FPID_OP(fcvt.w.d, x31, f31, dyn, 32, 0, x4, 32*FLEN/8, x5, x1, x2,FLREG)
inst_57:// fs1 == 1 and fe1 == 0x3f8 and fm1 == 0x47ae147ae147b and fcsr == 0x40 and rm_val == 7
/* opcode: fcvt.w.d ; op1:f31; dest:x31; op1val:0xbf847ae147ae147b; valaddr_reg:x4;
val_offset:33*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
fcsr_val:64*/
TEST_FPID_OP(fcvt.w.d, x31, f31, dyn, 64, 0, x4, 33*FLEN/8, x5, x1, x2,FLREG)
inst_58:// fs1 == 1 and fe1 == 0x3f8 and fm1 == 0x47ae147ae147b and fcsr == 0x60 and rm_val == 7
/* opcode: fcvt.w.d ; op1:f31; dest:x31; op1val:0xbf847ae147ae147b; valaddr_reg:x4;
val_offset:34*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
fcsr_val:96*/
TEST_FPID_OP(fcvt.w.d, x31, f31, dyn, 96, 0, x4, 34*FLEN/8, x5, x1, x2,FLREG)
inst_59:// fs1 == 1 and fe1 == 0x3f8 and fm1 == 0x47ae147ae147b and fcsr == 0x80 and rm_val == 7
/* opcode: fcvt.w.d ; op1:f31; dest:x31; op1val:0xbf847ae147ae147b; valaddr_reg:x4;
val_offset:35*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
fcsr_val:128*/
TEST_FPID_OP(fcvt.w.d, x31, f31, dyn, 128, 0, x4, 35*FLEN/8, x5, x1, x2,FLREG)
inst_60:// fs1 == 1 and fe1 == 0x3fb and fm1 == 0x999999999999a and fcsr == 0x0 and rm_val == 7
/* opcode: fcvt.w.d ; op1:f31; dest:x31; op1val:0xbfb999999999999a; valaddr_reg:x4;
val_offset:36*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
fcsr_val:0*/
TEST_FPID_OP(fcvt.w.d, x31, f31, dyn, 0, 0, x4, 36*FLEN/8, x5, x1, x2,FLREG)
inst_61:// fs1 == 1 and fe1 == 0x3fb and fm1 == 0x999999999999a and fcsr == 0x20 and rm_val == 7
/* opcode: fcvt.w.d ; op1:f31; dest:x31; op1val:0xbfb999999999999a; valaddr_reg:x4;
val_offset:37*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
fcsr_val:32*/
TEST_FPID_OP(fcvt.w.d, x31, f31, dyn, 32, 0, x4, 37*FLEN/8, x5, x1, x2,FLREG)
inst_62:// fs1 == 1 and fe1 == 0x3fb and fm1 == 0x999999999999a and fcsr == 0x40 and rm_val == 7
/* opcode: fcvt.w.d ; op1:f31; dest:x31; op1val:0xbfb999999999999a; valaddr_reg:x4;
val_offset:38*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
fcsr_val:64*/
TEST_FPID_OP(fcvt.w.d, x31, f31, dyn, 64, 0, x4, 38*FLEN/8, x5, x1, x2,FLREG)
inst_63:// fs1 == 1 and fe1 == 0x3fb and fm1 == 0x999999999999a and fcsr == 0x60 and rm_val == 7
/* opcode: fcvt.w.d ; op1:f31; dest:x31; op1val:0xbfb999999999999a; valaddr_reg:x4;
val_offset:39*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
fcsr_val:96*/
TEST_FPID_OP(fcvt.w.d, x31, f31, dyn, 96, 0, x4, 39*FLEN/8, x5, x1, x2,FLREG)
inst_64:// fs1 == 1 and fe1 == 0x3fb and fm1 == 0x999999999999a and fcsr == 0x80 and rm_val == 7
/* opcode: fcvt.w.d ; op1:f31; dest:x31; op1val:0xbfb999999999999a; valaddr_reg:x4;
val_offset:40*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
fcsr_val:128*/
TEST_FPID_OP(fcvt.w.d, x31, f31, dyn, 128, 0, x4, 40*FLEN/8, x5, x1, x2,FLREG)
inst_65:// fs1 == 1 and fe1 == 0x3fb and fm1 == 0xc28f5c28f5c29 and fcsr == 0x0 and rm_val == 7
/* opcode: fcvt.w.d ; op1:f31; dest:x31; op1val:0xbfbc28f5c28f5c29; valaddr_reg:x4;
val_offset:41*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
fcsr_val:0*/
TEST_FPID_OP(fcvt.w.d, x31, f31, dyn, 0, 0, x4, 41*FLEN/8, x5, x1, x2,FLREG)
inst_66:// fs1 == 1 and fe1 == 0x3fb and fm1 == 0xc28f5c28f5c29 and fcsr == 0x20 and rm_val == 7
/* opcode: fcvt.w.d ; op1:f31; dest:x31; op1val:0xbfbc28f5c28f5c29; valaddr_reg:x4;
val_offset:42*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
fcsr_val:32*/
TEST_FPID_OP(fcvt.w.d, x31, f31, dyn, 32, 0, x4, 42*FLEN/8, x5, x1, x2,FLREG)
inst_67:// fs1 == 1 and fe1 == 0x3fb and fm1 == 0xc28f5c28f5c29 and fcsr == 0x40 and rm_val == 7
/* opcode: fcvt.w.d ; op1:f31; dest:x31; op1val:0xbfbc28f5c28f5c29; valaddr_reg:x4;
val_offset:43*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
fcsr_val:64*/
TEST_FPID_OP(fcvt.w.d, x31, f31, dyn, 64, 0, x4, 43*FLEN/8, x5, x1, x2,FLREG)
inst_68:// fs1 == 1 and fe1 == 0x3fb and fm1 == 0xc28f5c28f5c29 and fcsr == 0x60 and rm_val == 7
/* opcode: fcvt.w.d ; op1:f31; dest:x31; op1val:0xbfbc28f5c28f5c29; valaddr_reg:x4;
val_offset:44*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
fcsr_val:96*/
TEST_FPID_OP(fcvt.w.d, x31, f31, dyn, 96, 0, x4, 44*FLEN/8, x5, x1, x2,FLREG)
inst_69:// fs1 == 1 and fe1 == 0x3fb and fm1 == 0xc28f5c28f5c29 and fcsr == 0x80 and rm_val == 7
/* opcode: fcvt.w.d ; op1:f31; dest:x31; op1val:0xbfbc28f5c28f5c29; valaddr_reg:x4;
val_offset:45*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
fcsr_val:128*/
TEST_FPID_OP(fcvt.w.d, x31, f31, dyn, 128, 0, x4, 45*FLEN/8, x5, x1, x2,FLREG)
inst_70:// fs1 == 1 and fe1 == 0x3fe and fm1 == 0xc7ae147ae147b and fcsr == 0x0 and rm_val == 7
/* opcode: fcvt.w.d ; op1:f31; dest:x31; op1val:0xbfec7ae147ae147b; valaddr_reg:x4;
val_offset:46*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
fcsr_val:0*/
TEST_FPID_OP(fcvt.w.d, x31, f31, dyn, 0, 0, x4, 46*FLEN/8, x5, x1, x2,FLREG)
inst_71:// fs1 == 1 and fe1 == 0x3fe and fm1 == 0xc7ae147ae147b and fcsr == 0x20 and rm_val == 7
/* opcode: fcvt.w.d ; op1:f31; dest:x31; op1val:0xbfec7ae147ae147b; valaddr_reg:x4;
val_offset:47*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
fcsr_val:32*/
TEST_FPID_OP(fcvt.w.d, x31, f31, dyn, 32, 0, x4, 47*FLEN/8, x5, x1, x2,FLREG)
inst_72:// fs1 == 1 and fe1 == 0x3fe and fm1 == 0xc7ae147ae147b and fcsr == 0x40 and rm_val == 7
/* opcode: fcvt.w.d ; op1:f31; dest:x31; op1val:0xbfec7ae147ae147b; valaddr_reg:x4;
val_offset:48*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
fcsr_val:64*/
TEST_FPID_OP(fcvt.w.d, x31, f31, dyn, 64, 0, x4, 48*FLEN/8, x5, x1, x2,FLREG)
inst_73:// fs1 == 1 and fe1 == 0x3fe and fm1 == 0xc7ae147ae147b and fcsr == 0x60 and rm_val == 7
/* opcode: fcvt.w.d ; op1:f31; dest:x31; op1val:0xbfec7ae147ae147b; valaddr_reg:x4;
val_offset:49*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
fcsr_val:96*/
TEST_FPID_OP(fcvt.w.d, x31, f31, dyn, 96, 0, x4, 49*FLEN/8, x5, x1, x2,FLREG)
inst_74:// fs1 == 1 and fe1 == 0x3fe and fm1 == 0xc7ae147ae147b and fcsr == 0x80 and rm_val == 7
/* opcode: fcvt.w.d ; op1:f31; dest:x31; op1val:0xbfec7ae147ae147b; valaddr_reg:x4;
val_offset:50*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
fcsr_val:128*/
TEST_FPID_OP(fcvt.w.d, x31, f31, dyn, 128, 0, x4, 50*FLEN/8, x5, x1, x2,FLREG)
inst_75:// fs1 == 1 and fe1 == 0x3fe and fm1 == 0xccccccccccccd and fcsr == 0x0 and rm_val == 7
/* opcode: fcvt.w.d ; op1:f31; dest:x31; op1val:0xbfeccccccccccccd; valaddr_reg:x4;
val_offset:51*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
fcsr_val:0*/
TEST_FPID_OP(fcvt.w.d, x31, f31, dyn, 0, 0, x4, 51*FLEN/8, x5, x1, x2,FLREG)
inst_76:// fs1 == 1 and fe1 == 0x3fe and fm1 == 0xccccccccccccd and fcsr == 0x20 and rm_val == 7
/* opcode: fcvt.w.d ; op1:f31; dest:x31; op1val:0xbfeccccccccccccd; valaddr_reg:x4;
val_offset:52*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
fcsr_val:32*/
TEST_FPID_OP(fcvt.w.d, x31, f31, dyn, 32, 0, x4, 52*FLEN/8, x5, x1, x2,FLREG)
inst_77:// fs1 == 1 and fe1 == 0x3fe and fm1 == 0xccccccccccccd and fcsr == 0x40 and rm_val == 7
/* opcode: fcvt.w.d ; op1:f31; dest:x31; op1val:0xbfeccccccccccccd; valaddr_reg:x4;
val_offset:53*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
fcsr_val:64*/
TEST_FPID_OP(fcvt.w.d, x31, f31, dyn, 64, 0, x4, 53*FLEN/8, x5, x1, x2,FLREG)
inst_78:// fs1 == 1 and fe1 == 0x3fe and fm1 == 0xccccccccccccd and fcsr == 0x60 and rm_val == 7
/* opcode: fcvt.w.d ; op1:f31; dest:x31; op1val:0xbfeccccccccccccd; valaddr_reg:x4;
val_offset:54*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
fcsr_val:96*/
TEST_FPID_OP(fcvt.w.d, x31, f31, dyn, 96, 0, x4, 54*FLEN/8, x5, x1, x2,FLREG)
inst_79:// fs1 == 1 and fe1 == 0x3fe and fm1 == 0xccccccccccccd and fcsr == 0x80 and rm_val == 7
/* opcode: fcvt.w.d ; op1:f31; dest:x31; op1val:0xbfeccccccccccccd; valaddr_reg:x4;
val_offset:55*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
fcsr_val:128*/
TEST_FPID_OP(fcvt.w.d, x31, f31, dyn, 128, 0, x4, 55*FLEN/8, x5, x1, x2,FLREG)
inst_80:// fs1 == 1 and fe1 == 0x3fe and fm1 == 0xfae147ae147ae and fcsr == 0x0 and rm_val == 7
/* opcode: fcvt.w.d ; op1:f31; dest:x31; op1val:0xbfefae147ae147ae; valaddr_reg:x4;
val_offset:56*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
fcsr_val:0*/
TEST_FPID_OP(fcvt.w.d, x31, f31, dyn, 0, 0, x4, 56*FLEN/8, x5, x1, x2,FLREG)
inst_81:// fs1 == 1 and fe1 == 0x3fe and fm1 == 0xfae147ae147ae and fcsr == 0x20 and rm_val == 7
/* opcode: fcvt.w.d ; op1:f31; dest:x31; op1val:0xbfefae147ae147ae; valaddr_reg:x4;
val_offset:57*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
fcsr_val:32*/
TEST_FPID_OP(fcvt.w.d, x31, f31, dyn, 32, 0, x4, 57*FLEN/8, x5, x1, x2,FLREG)
inst_82:// fs1 == 1 and fe1 == 0x3fe and fm1 == 0xfae147ae147ae and fcsr == 0x40 and rm_val == 7
/* opcode: fcvt.w.d ; op1:f31; dest:x31; op1val:0xbfefae147ae147ae; valaddr_reg:x4;
val_offset:58*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
fcsr_val:64*/
TEST_FPID_OP(fcvt.w.d, x31, f31, dyn, 64, 0, x4, 58*FLEN/8, x5, x1, x2,FLREG)
inst_83:// fs1 == 1 and fe1 == 0x3fe and fm1 == 0xfae147ae147ae and fcsr == 0x60 and rm_val == 7
/* opcode: fcvt.w.d ; op1:f31; dest:x31; op1val:0xbfefae147ae147ae; valaddr_reg:x4;
val_offset:59*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
fcsr_val:96*/
TEST_FPID_OP(fcvt.w.d, x31, f31, dyn, 96, 0, x4, 59*FLEN/8, x5, x1, x2,FLREG)
inst_84:// fs1 == 1 and fe1 == 0x3fe and fm1 == 0xfae147ae147ae and fcsr == 0x80 and rm_val == 7
/* opcode: fcvt.w.d ; op1:f31; dest:x31; op1val:0xbfefae147ae147ae; valaddr_reg:x4;
val_offset:60*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
fcsr_val:128*/
TEST_FPID_OP(fcvt.w.d, x31, f31, dyn, 128, 0, x4, 60*FLEN/8, x5, x1, x2,FLREG)
inst_85:// fs1 == 1 and fe1 == 0x3ff and fm1 == 0x0000000000000 and fcsr == 0x0 and rm_val == 7
/* opcode: fcvt.w.d ; op1:f31; dest:x31; op1val:0xbff0000000000000; valaddr_reg:x4;
val_offset:61*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
fcsr_val:0*/
TEST_FPID_OP(fcvt.w.d, x31, f31, dyn, 0, 0, x4, 61*FLEN/8, x5, x1, x2,FLREG)
inst_86:// fs1 == 1 and fe1 == 0x3ff and fm1 == 0x0000000000000 and fcsr == 0x20 and rm_val == 7
/* opcode: fcvt.w.d ; op1:f31; dest:x31; op1val:0xbff0000000000000; valaddr_reg:x4;
val_offset:62*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
fcsr_val:32*/
TEST_FPID_OP(fcvt.w.d, x31, f31, dyn, 32, 0, x4, 62*FLEN/8, x5, x1, x2,FLREG)
inst_87:// fs1 == 1 and fe1 == 0x3ff and fm1 == 0x0000000000000 and fcsr == 0x40 and rm_val == 7
/* opcode: fcvt.w.d ; op1:f31; dest:x31; op1val:0xbff0000000000000; valaddr_reg:x4;
val_offset:63*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
fcsr_val:64*/
TEST_FPID_OP(fcvt.w.d, x31, f31, dyn, 64, 0, x4, 63*FLEN/8, x5, x1, x2,FLREG)
inst_88:// fs1 == 1 and fe1 == 0x3ff and fm1 == 0x0000000000000 and fcsr == 0x60 and rm_val == 7
/* opcode: fcvt.w.d ; op1:f31; dest:x31; op1val:0xbff0000000000000; valaddr_reg:x4;
val_offset:64*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
fcsr_val:96*/
TEST_FPID_OP(fcvt.w.d, x31, f31, dyn, 96, 0, x4, 64*FLEN/8, x5, x1, x2,FLREG)
inst_89:// fs1 == 1 and fe1 == 0x3ff and fm1 == 0x0000000000000 and fcsr == 0x80 and rm_val == 7
/* opcode: fcvt.w.d ; op1:f31; dest:x31; op1val:0xbff0000000000000; valaddr_reg:x4;
val_offset:65*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
fcsr_val:128*/
TEST_FPID_OP(fcvt.w.d, x31, f31, dyn, 128, 0, x4, 65*FLEN/8, x5, x1, x2,FLREG)
inst_90:// fs1 == 1 and fe1 == 0x3ff and fm1 == 0x028f5c28f5c29 and fcsr == 0x0 and rm_val == 7
/* opcode: fcvt.w.d ; op1:f31; dest:x31; op1val:0xbff028f5c28f5c29; valaddr_reg:x4;
val_offset:66*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
fcsr_val:0*/
TEST_FPID_OP(fcvt.w.d, x31, f31, dyn, 0, 0, x4, 66*FLEN/8, x5, x1, x2,FLREG)
inst_91:// fs1 == 1 and fe1 == 0x3ff and fm1 == 0x028f5c28f5c29 and fcsr == 0x20 and rm_val == 7
/* opcode: fcvt.w.d ; op1:f31; dest:x31; op1val:0xbff028f5c28f5c29; valaddr_reg:x4;
val_offset:67*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
fcsr_val:32*/
TEST_FPID_OP(fcvt.w.d, x31, f31, dyn, 32, 0, x4, 67*FLEN/8, x5, x1, x2,FLREG)
inst_92:// fs1 == 1 and fe1 == 0x3ff and fm1 == 0x028f5c28f5c29 and fcsr == 0x40 and rm_val == 7
/* opcode: fcvt.w.d ; op1:f31; dest:x31; op1val:0xbff028f5c28f5c29; valaddr_reg:x4;
val_offset:68*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
fcsr_val:64*/
TEST_FPID_OP(fcvt.w.d, x31, f31, dyn, 64, 0, x4, 68*FLEN/8, x5, x1, x2,FLREG)
inst_93:// fs1 == 1 and fe1 == 0x3ff and fm1 == 0x028f5c28f5c29 and fcsr == 0x60 and rm_val == 7
/* opcode: fcvt.w.d ; op1:f31; dest:x31; op1val:0xbff028f5c28f5c29; valaddr_reg:x4;
val_offset:69*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
fcsr_val:96*/
TEST_FPID_OP(fcvt.w.d, x31, f31, dyn, 96, 0, x4, 69*FLEN/8, x5, x1, x2,FLREG)
inst_94:// fs1 == 1 and fe1 == 0x3ff and fm1 == 0x028f5c28f5c29 and fcsr == 0x80 and rm_val == 7
/* opcode: fcvt.w.d ; op1:f31; dest:x31; op1val:0xbff028f5c28f5c29; valaddr_reg:x4;
val_offset:70*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
fcsr_val:128*/
TEST_FPID_OP(fcvt.w.d, x31, f31, dyn, 128, 0, x4, 70*FLEN/8, x5, x1, x2,FLREG)
inst_95:// fs1 == 1 and fe1 == 0x3ff and fm1 == 0x199999999999a and fcsr == 0x0 and rm_val == 7
/* opcode: fcvt.w.d ; op1:f31; dest:x31; op1val:0xbff199999999999a; valaddr_reg:x4;
val_offset:71*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
fcsr_val:0*/
TEST_FPID_OP(fcvt.w.d, x31, f31, dyn, 0, 0, x4, 71*FLEN/8, x5, x1, x2,FLREG)
inst_96:// fs1 == 1 and fe1 == 0x3ff and fm1 == 0x199999999999a and fcsr == 0x20 and rm_val == 7
/* opcode: fcvt.w.d ; op1:f31; dest:x31; op1val:0xbff199999999999a; valaddr_reg:x4;
val_offset:72*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
fcsr_val:32*/
TEST_FPID_OP(fcvt.w.d, x31, f31, dyn, 32, 0, x4, 72*FLEN/8, x5, x1, x2,FLREG)
inst_97:// fs1 == 1 and fe1 == 0x3ff and fm1 == 0x199999999999a and fcsr == 0x40 and rm_val == 7
/* opcode: fcvt.w.d ; op1:f31; dest:x31; op1val:0xbff199999999999a; valaddr_reg:x4;
val_offset:73*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
fcsr_val:64*/
TEST_FPID_OP(fcvt.w.d, x31, f31, dyn, 64, 0, x4, 73*FLEN/8, x5, x1, x2,FLREG)
inst_98:// fs1 == 1 and fe1 == 0x3ff and fm1 == 0x199999999999a and fcsr == 0x60 and rm_val == 7
/* opcode: fcvt.w.d ; op1:f31; dest:x31; op1val:0xbff199999999999a; valaddr_reg:x4;
val_offset:74*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
fcsr_val:96*/
TEST_FPID_OP(fcvt.w.d, x31, f31, dyn, 96, 0, x4, 74*FLEN/8, x5, x1, x2,FLREG)
inst_99:// fs1 == 1 and fe1 == 0x3ff and fm1 == 0x199999999999a and fcsr == 0x80 and rm_val == 7
/* opcode: fcvt.w.d ; op1:f31; dest:x31; op1val:0xbff199999999999a; valaddr_reg:x4;
val_offset:75*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
fcsr_val:128*/
TEST_FPID_OP(fcvt.w.d, x31, f31, dyn, 128, 0, x4, 75*FLEN/8, x5, x1, x2,FLREG)
inst_100:// fs1 == 1 and fe1 == 0x3ff and fm1 == 0x1c28f5c28f5c3 and fcsr == 0x0 and rm_val == 7
/* opcode: fcvt.w.d ; op1:f31; dest:x31; op1val:0xbff1c28f5c28f5c3; valaddr_reg:x4;
val_offset:76*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
fcsr_val:0*/
TEST_FPID_OP(fcvt.w.d, x31, f31, dyn, 0, 0, x4, 76*FLEN/8, x5, x1, x2,FLREG)
inst_101:// fs1 == 1 and fe1 == 0x3ff and fm1 == 0x1c28f5c28f5c3 and fcsr == 0x20 and rm_val == 7
/* opcode: fcvt.w.d ; op1:f31; dest:x31; op1val:0xbff1c28f5c28f5c3; valaddr_reg:x4;
val_offset:77*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
fcsr_val:32*/
TEST_FPID_OP(fcvt.w.d, x31, f31, dyn, 32, 0, x4, 77*FLEN/8, x5, x1, x2,FLREG)
inst_102:// fs1 == 1 and fe1 == 0x3ff and fm1 == 0x1c28f5c28f5c3 and fcsr == 0x40 and rm_val == 7
/* opcode: fcvt.w.d ; op1:f31; dest:x31; op1val:0xbff1c28f5c28f5c3; valaddr_reg:x4;
val_offset:78*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
fcsr_val:64*/
TEST_FPID_OP(fcvt.w.d, x31, f31, dyn, 64, 0, x4, 78*FLEN/8, x5, x1, x2,FLREG)
inst_103:// fs1 == 1 and fe1 == 0x3ff and fm1 == 0x1c28f5c28f5c3 and fcsr == 0x60 and rm_val == 7
/* opcode: fcvt.w.d ; op1:f31; dest:x31; op1val:0xbff1c28f5c28f5c3; valaddr_reg:x4;
val_offset:79*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
fcsr_val:96*/
TEST_FPID_OP(fcvt.w.d, x31, f31, dyn, 96, 0, x4, 79*FLEN/8, x5, x1, x2,FLREG)
inst_104:// fs1 == 1 and fe1 == 0x3ff and fm1 == 0x1c28f5c28f5c3 and fcsr == 0x80 and rm_val == 7
/* opcode: fcvt.w.d ; op1:f31; dest:x31; op1val:0xbff1c28f5c28f5c3; valaddr_reg:x4;
val_offset:80*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
fcsr_val:128*/
TEST_FPID_OP(fcvt.w.d, x31, f31, dyn, 128, 0, x4, 80*FLEN/8, x5, x1, x2,FLREG)
inst_105:// fs1 == 0 and fe1 == 0x3fe and fm1 == 0xccccccccccccd and fcsr == 0x40 and rm_val == 7
/* opcode: fcvt.w.d ; op1:f31; dest:x31; op1val:0x3feccccccccccccd; valaddr_reg:x4;
val_offset:81*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
fcsr_val:64*/
TEST_FPID_OP(fcvt.w.d, x31, f31, dyn, 64, 0, x4, 81*FLEN/8, x5, x1, x2,FLREG)
#endif
RVTEST_CODE_END
RVMODEL_HALT
RVTEST_DATA_BEGIN
.align 4
rvtest_data:
.word 0xbabecafe
.word 0xabecafeb
.word 0xbecafeba
.word 0xecafebab
test_dataset_0:
NAN_BOXED(0,64,FLEN)
NAN_BOXED(0,64,FLEN)
NAN_BOXED(0,64,FLEN)
NAN_BOXED(0,64,FLEN)
NAN_BOXED(0,64,FLEN)
NAN_BOXED(4576918229304087675,64,FLEN)
NAN_BOXED(4576918229304087675,64,FLEN)
NAN_BOXED(4576918229304087675,64,FLEN)
NAN_BOXED(4576918229304087675,64,FLEN)
NAN_BOXED(4576918229304087675,64,FLEN)
NAN_BOXED(4591870180066957722,64,FLEN)
NAN_BOXED(4591870180066957722,64,FLEN)
NAN_BOXED(4591870180066957722,64,FLEN)
NAN_BOXED(4591870180066957722,64,FLEN)
NAN_BOXED(4591870180066957722,64,FLEN)
NAN_BOXED(4592590756007337001,64,FLEN)
NAN_BOXED(4592590756007337001,64,FLEN)
NAN_BOXED(4592590756007337001,64,FLEN)
NAN_BOXED(4592590756007337001,64,FLEN)
NAN_BOXED(4592590756007337001,64,FLEN)
NAN_BOXED(4606191626881995899,64,FLEN)
NAN_BOXED(4606191626881995899,64,FLEN)
NAN_BOXED(4606191626881995899,64,FLEN)
NAN_BOXED(4606191626881995899,64,FLEN)
test_dataset_1:
NAN_BOXED(4606191626881995899,64,FLEN)
NAN_BOXED(4606281698874543309,64,FLEN)
NAN_BOXED(4606281698874543309,64,FLEN)
NAN_BOXED(4606281698874543309,64,FLEN)
NAN_BOXED(4606281698874543309,64,FLEN)
NAN_BOXED(4606281698874543309,64,FLEN)
NAN_BOXED(4607092346807469998,64,FLEN)
NAN_BOXED(4607092346807469998,64,FLEN)
NAN_BOXED(4607092346807469998,64,FLEN)
NAN_BOXED(4607092346807469998,64,FLEN)
NAN_BOXED(4607092346807469998,64,FLEN)
NAN_BOXED(4607182418800017408,64,FLEN)
NAN_BOXED(4607182418800017408,64,FLEN)
NAN_BOXED(4607182418800017408,64,FLEN)
NAN_BOXED(4607182418800017408,64,FLEN)
NAN_BOXED(4607182418800017408,64,FLEN)
NAN_BOXED(4607227454796291113,64,FLEN)
NAN_BOXED(4607227454796291113,64,FLEN)
NAN_BOXED(4607227454796291113,64,FLEN)
NAN_BOXED(4607227454796291113,64,FLEN)
NAN_BOXED(4607227454796291113,64,FLEN)
NAN_BOXED(4607632778762754458,64,FLEN)
NAN_BOXED(4607632778762754458,64,FLEN)
NAN_BOXED(4607632778762754458,64,FLEN)
NAN_BOXED(4607632778762754458,64,FLEN)
NAN_BOXED(4607632778762754458,64,FLEN)
NAN_BOXED(4607677814759028163,64,FLEN)
NAN_BOXED(4607677814759028163,64,FLEN)
NAN_BOXED(4607677814759028163,64,FLEN)
NAN_BOXED(4607677814759028163,64,FLEN)
NAN_BOXED(4607677814759028163,64,FLEN)
NAN_BOXED(13800290266158863483,64,FLEN)
NAN_BOXED(13800290266158863483,64,FLEN)
NAN_BOXED(13800290266158863483,64,FLEN)
NAN_BOXED(13800290266158863483,64,FLEN)
NAN_BOXED(13800290266158863483,64,FLEN)
NAN_BOXED(13815242216921733530,64,FLEN)
NAN_BOXED(13815242216921733530,64,FLEN)
NAN_BOXED(13815242216921733530,64,FLEN)
NAN_BOXED(13815242216921733530,64,FLEN)
NAN_BOXED(13815242216921733530,64,FLEN)
NAN_BOXED(13815962792862112809,64,FLEN)
NAN_BOXED(13815962792862112809,64,FLEN)
NAN_BOXED(13815962792862112809,64,FLEN)
NAN_BOXED(13815962792862112809,64,FLEN)
NAN_BOXED(13815962792862112809,64,FLEN)
NAN_BOXED(13829563663736771707,64,FLEN)
NAN_BOXED(13829563663736771707,64,FLEN)
NAN_BOXED(13829563663736771707,64,FLEN)
NAN_BOXED(13829563663736771707,64,FLEN)
NAN_BOXED(13829563663736771707,64,FLEN)
NAN_BOXED(13829653735729319117,64,FLEN)
NAN_BOXED(13829653735729319117,64,FLEN)
NAN_BOXED(13829653735729319117,64,FLEN)
NAN_BOXED(13829653735729319117,64,FLEN)
NAN_BOXED(13829653735729319117,64,FLEN)
NAN_BOXED(13830464383662245806,64,FLEN)
NAN_BOXED(13830464383662245806,64,FLEN)
NAN_BOXED(13830464383662245806,64,FLEN)
NAN_BOXED(13830464383662245806,64,FLEN)
NAN_BOXED(13830464383662245806,64,FLEN)
NAN_BOXED(13830554455654793216,64,FLEN)
NAN_BOXED(13830554455654793216,64,FLEN)
NAN_BOXED(13830554455654793216,64,FLEN)
NAN_BOXED(13830554455654793216,64,FLEN)
NAN_BOXED(13830554455654793216,64,FLEN)
NAN_BOXED(13830599491651066921,64,FLEN)
NAN_BOXED(13830599491651066921,64,FLEN)
NAN_BOXED(13830599491651066921,64,FLEN)
NAN_BOXED(13830599491651066921,64,FLEN)
NAN_BOXED(13830599491651066921,64,FLEN)
NAN_BOXED(13831004815617530266,64,FLEN)
NAN_BOXED(13831004815617530266,64,FLEN)
NAN_BOXED(13831004815617530266,64,FLEN)
NAN_BOXED(13831004815617530266,64,FLEN)
NAN_BOXED(13831004815617530266,64,FLEN)
NAN_BOXED(13831049851613803971,64,FLEN)
NAN_BOXED(13831049851613803971,64,FLEN)
NAN_BOXED(13831049851613803971,64,FLEN)
NAN_BOXED(13831049851613803971,64,FLEN)
NAN_BOXED(13831049851613803971,64,FLEN)
NAN_BOXED(4606281698874543309,64,FLEN)
RVTEST_DATA_END
RVMODEL_DATA_BEGIN
rvtest_sig_begin:
sig_begin_canary:
CANARY;
signature_x9_0:
.fill 0*((SIGALIGN)/4),4,0xdeadbeef
signature_x9_1:
.fill 54*((SIGALIGN)/4),4,0xdeadbeef
signature_x1_0:
.fill 158*((SIGALIGN)/4),4,0xdeadbeef
#ifdef rvtest_mtrap_routine
tsig_begin_canary:
CANARY;
tsig_begin_canary:
CANARY;
mtrap_sigptr:
.fill 64*(XLEN/32),4,0xdeadbeef
tsig_end_canary:
CANARY;
tsig_end_canary:
CANARY;
#endif
#ifdef rvtest_gpr_save
gpr_save:
.fill 32*XLEN/32,4,0xdeadbeef
#endif
sig_end_canary:
CANARY;
rvtest_sig_end:
RVMODEL_DATA_END

330
vendor/riscv-arch-tests/riscv-test-suite/rv32i_m/D/src/fcvt.w.d_b27-01.S vendored
View file

@ -1,330 +0,0 @@
// -----------
// This file was generated by riscv_ctg (https://github.com/riscv-software-src/riscv-ctg)
// version : 0.7.1
// timestamp : Fri Jun 17 14:03:36 2022 GMT
// usage : riscv_ctg \
// -- cgf // --cgf /scratch/pawan/work/normalised/RV32D/fcvt.w.d.cgf \
\
// -- xlen 32 \
// --randomize \
// -----------
//
// -----------
// Copyright (c) 2020. RISC-V International. All rights reserved.
// SPDX-License-Identifier: BSD-3-Clause
// -----------
//
// This assembly file tests the fcvt.w.d instruction of the RISC-V RV32FD_Zicsr,RV64FD_Zicsr extension for the fcvt.w.d_b27 covergroup.
//
#include "model_test.h"
#include "arch_test.h"
RVTEST_ISA("RV32IFD_Zicsr,RV64IFD_Zicsr")
.section .text.init
.org 0x80
.globl rvtest_entry_point
rvtest_entry_point:
RVMODEL_BOOT
RVTEST_CODE_BEGIN
#ifdef TEST_CASE_1
RVTEST_CASE(0,"//check ISA:=regex(.*I.*D.*);def TEST_CASE_1=True;",fcvt.w.d_b27)
RVTEST_FP_ENABLE()
RVTEST_VALBASEUPD(x12,test_dataset_0)
RVTEST_SIGBASE(x16,signature_x16_1)
inst_0:// rs1==f18, rd==x11,fs1 == 0 and fe1 == 0x7ff and fm1 == 0x0000000000001 and fcsr == 0x0 and rm_val == 7
/* opcode: fcvt.w.d ; op1:f18; dest:x11; op1val:0x7ff0000000000001; valaddr_reg:x12;
val_offset:0*FLEN/8; rmval:dyn; correctval:??; testreg:x7;
fcsr_val:0*/
TEST_FPID_OP(fcvt.w.d, x11, f18, dyn, 0, 0, x12, 0*FLEN/8, x15, x16, x7,FLREG)
inst_1:// rs1==f21, rd==x6,fs1 == 0 and fe1 == 0x7ff and fm1 == 0x4aaaaaaaaaaaa and fcsr == 0x0 and rm_val == 7
/* opcode: fcvt.w.d ; op1:f21; dest:x6; op1val:0x7ff4aaaaaaaaaaaa; valaddr_reg:x12;
val_offset:1*FLEN/8; rmval:dyn; correctval:??; testreg:x7;
fcsr_val:0*/
TEST_FPID_OP(fcvt.w.d, x6, f21, dyn, 0, 0, x12, 1*FLEN/8, x15, x16, x7,FLREG)
inst_2:// rs1==f8, rd==x27,fs1 == 0 and fe1 == 0x7ff and fm1 == 0x8000000000001 and fcsr == 0x0 and rm_val == 7
/* opcode: fcvt.w.d ; op1:f8; dest:x27; op1val:0x7ff8000000000001; valaddr_reg:x12;
val_offset:2*FLEN/8; rmval:dyn; correctval:??; testreg:x7;
fcsr_val:0*/
TEST_FPID_OP(fcvt.w.d, x27, f8, dyn, 0, 0, x12, 2*FLEN/8, x15, x16, x7,FLREG)
inst_3:// rs1==f3, rd==x5,fs1 == 0 and fe1 == 0x7ff and fm1 == 0xc000000000001 and fcsr == 0x0 and rm_val == 7
/* opcode: fcvt.w.d ; op1:f3; dest:x5; op1val:0x7ffc000000000001; valaddr_reg:x12;
val_offset:3*FLEN/8; rmval:dyn; correctval:??; testreg:x7;
fcsr_val:0*/
TEST_FPID_OP(fcvt.w.d, x5, f3, dyn, 0, 0, x12, 3*FLEN/8, x15, x16, x7,FLREG)
inst_4:// rs1==f1, rd==x9,fs1 == 1 and fe1 == 0x7ff and fm1 == 0x0000000000001 and fcsr == 0x0 and rm_val == 7
/* opcode: fcvt.w.d ; op1:f1; dest:x9; op1val:0xfff0000000000001; valaddr_reg:x12;
val_offset:4*FLEN/8; rmval:dyn; correctval:??; testreg:x7;
fcsr_val:0*/
TEST_FPID_OP(fcvt.w.d, x9, f1, dyn, 0, 0, x12, 4*FLEN/8, x15, x16, x7,FLREG)
inst_5:// rs1==f14, rd==x19,fs1 == 1 and fe1 == 0x7ff and fm1 == 0x4aaaaaaaaaaaa and fcsr == 0x0 and rm_val == 7
/* opcode: fcvt.w.d ; op1:f14; dest:x19; op1val:0xfff4aaaaaaaaaaaa; valaddr_reg:x12;
val_offset:5*FLEN/8; rmval:dyn; correctval:??; testreg:x7;
fcsr_val:0*/
TEST_FPID_OP(fcvt.w.d, x19, f14, dyn, 0, 0, x12, 5*FLEN/8, x15, x16, x7,FLREG)
inst_6:// rs1==f17, rd==x28,fs1 == 1 and fe1 == 0x7ff and fm1 == 0x8000000000001 and fcsr == 0x0 and rm_val == 7
/* opcode: fcvt.w.d ; op1:f17; dest:x28; op1val:0xfff8000000000001; valaddr_reg:x12;
val_offset:6*FLEN/8; rmval:dyn; correctval:??; testreg:x7;
fcsr_val:0*/
TEST_FPID_OP(fcvt.w.d, x28, f17, dyn, 0, 0, x12, 6*FLEN/8, x15, x16, x7,FLREG)
inst_7:// rs1==f31, rd==x26,fs1 == 1 and fe1 == 0x7ff and fm1 == 0xc000000000001 and fcsr == 0x0 and rm_val == 7
/* opcode: fcvt.w.d ; op1:f31; dest:x26; op1val:0xfffc000000000001; valaddr_reg:x12;
val_offset:7*FLEN/8; rmval:dyn; correctval:??; testreg:x7;
fcsr_val:0*/
TEST_FPID_OP(fcvt.w.d, x26, f31, dyn, 0, 0, x12, 7*FLEN/8, x15, x16, x7,FLREG)
inst_8:// rs1==f2, rd==x30,
/* opcode: fcvt.w.d ; op1:f2; dest:x30; op1val:0x0; valaddr_reg:x12;
val_offset:8*FLEN/8; rmval:dyn; correctval:??; testreg:x7;
fcsr_val:0*/
TEST_FPID_OP(fcvt.w.d, x30, f2, dyn, 0, 0, x12, 8*FLEN/8, x15, x16, x7,FLREG)
inst_9:// rs1==f26, rd==x14,
/* opcode: fcvt.w.d ; op1:f26; dest:x14; op1val:0x0; valaddr_reg:x12;
val_offset:9*FLEN/8; rmval:dyn; correctval:??; testreg:x7;
fcsr_val:0*/
TEST_FPID_OP(fcvt.w.d, x14, f26, dyn, 0, 0, x12, 9*FLEN/8, x15, x16, x7,FLREG)
inst_10:// rs1==f9, rd==x13,
/* opcode: fcvt.w.d ; op1:f9; dest:x13; op1val:0x0; valaddr_reg:x12;
val_offset:10*FLEN/8; rmval:dyn; correctval:??; testreg:x7;
fcsr_val:0*/
TEST_FPID_OP(fcvt.w.d, x13, f9, dyn, 0, 0, x12, 10*FLEN/8, x15, x16, x7,FLREG)
inst_11:// rs1==f29, rd==x10,
/* opcode: fcvt.w.d ; op1:f29; dest:x10; op1val:0x0; valaddr_reg:x12;
val_offset:11*FLEN/8; rmval:dyn; correctval:??; testreg:x7;
fcsr_val:0*/
TEST_FPID_OP(fcvt.w.d, x10, f29, dyn, 0, 0, x12, 11*FLEN/8, x15, x16, x7,FLREG)
inst_12:// rs1==f22, rd==x24,
/* opcode: fcvt.w.d ; op1:f22; dest:x24; op1val:0x0; valaddr_reg:x12;
val_offset:12*FLEN/8; rmval:dyn; correctval:??; testreg:x7;
fcsr_val:0*/
TEST_FPID_OP(fcvt.w.d, x24, f22, dyn, 0, 0, x12, 12*FLEN/8, x15, x16, x7,FLREG)
inst_13:// rs1==f16, rd==x17,
/* opcode: fcvt.w.d ; op1:f16; dest:x17; op1val:0x0; valaddr_reg:x12;
val_offset:13*FLEN/8; rmval:dyn; correctval:??; testreg:x7;
fcsr_val:0*/
TEST_FPID_OP(fcvt.w.d, x17, f16, dyn, 0, 0, x12, 13*FLEN/8, x15, x16, x7,FLREG)
inst_14:// rs1==f23, rd==x25,
/* opcode: fcvt.w.d ; op1:f23; dest:x25; op1val:0x0; valaddr_reg:x12;
val_offset:14*FLEN/8; rmval:dyn; correctval:??; testreg:x7;
fcsr_val:0*/
TEST_FPID_OP(fcvt.w.d, x25, f23, dyn, 0, 0, x12, 14*FLEN/8, x15, x16, x7,FLREG)
inst_15:// rs1==f30, rd==x2,
/* opcode: fcvt.w.d ; op1:f30; dest:x2; op1val:0x0; valaddr_reg:x12;
val_offset:15*FLEN/8; rmval:dyn; correctval:??; testreg:x7;
fcsr_val:0*/
TEST_FPID_OP(fcvt.w.d, x2, f30, dyn, 0, 0, x12, 15*FLEN/8, x15, x16, x7,FLREG)
inst_16:// rs1==f20, rd==x31,
/* opcode: fcvt.w.d ; op1:f20; dest:x31; op1val:0x0; valaddr_reg:x12;
val_offset:16*FLEN/8; rmval:dyn; correctval:??; testreg:x7;
fcsr_val:0*/
TEST_FPID_OP(fcvt.w.d, x31, f20, dyn, 0, 0, x12, 16*FLEN/8, x15, x16, x7,FLREG)
inst_17:// rs1==f13, rd==x18,
/* opcode: fcvt.w.d ; op1:f13; dest:x18; op1val:0x0; valaddr_reg:x12;
val_offset:17*FLEN/8; rmval:dyn; correctval:??; testreg:x7;
fcsr_val:0*/
TEST_FPID_OP(fcvt.w.d, x18, f13, dyn, 0, 0, x12, 17*FLEN/8, x15, x16, x7,FLREG)
inst_18:// rs1==f19, rd==x29,
/* opcode: fcvt.w.d ; op1:f19; dest:x29; op1val:0x0; valaddr_reg:x12;
val_offset:18*FLEN/8; rmval:dyn; correctval:??; testreg:x7;
fcsr_val:0*/
TEST_FPID_OP(fcvt.w.d, x29, f19, dyn, 0, 0, x12, 18*FLEN/8, x15, x16, x7,FLREG)
inst_19:// rs1==f25, rd==x8,
/* opcode: fcvt.w.d ; op1:f25; dest:x8; op1val:0x0; valaddr_reg:x12;
val_offset:19*FLEN/8; rmval:dyn; correctval:??; testreg:x7;
fcsr_val:0*/
TEST_FPID_OP(fcvt.w.d, x8, f25, dyn, 0, 0, x12, 19*FLEN/8, x15, x16, x7,FLREG)
inst_20:// rs1==f24, rd==x1,
/* opcode: fcvt.w.d ; op1:f24; dest:x1; op1val:0x0; valaddr_reg:x12;
val_offset:20*FLEN/8; rmval:dyn; correctval:??; testreg:x7;
fcsr_val:0*/
TEST_FPID_OP(fcvt.w.d, x1, f24, dyn, 0, 0, x12, 20*FLEN/8, x15, x16, x7,FLREG)
inst_21:// rs1==f10, rd==x0,
/* opcode: fcvt.w.d ; op1:f10; dest:x0; op1val:0x0; valaddr_reg:x12;
val_offset:21*FLEN/8; rmval:dyn; correctval:??; testreg:x7;
fcsr_val:0*/
TEST_FPID_OP(fcvt.w.d, x0, f10, dyn, 0, 0, x12, 21*FLEN/8, x15, x16, x7,FLREG)
inst_22:// rs1==f12, rd==x4,
/* opcode: fcvt.w.d ; op1:f12; dest:x4; op1val:0x0; valaddr_reg:x12;
val_offset:22*FLEN/8; rmval:dyn; correctval:??; testreg:x7;
fcsr_val:0*/
TEST_FPID_OP(fcvt.w.d, x4, f12, dyn, 0, 0, x12, 22*FLEN/8, x15, x16, x7,FLREG)
inst_23:// rs1==f0, rd==x23,
/* opcode: fcvt.w.d ; op1:f0; dest:x23; op1val:0x0; valaddr_reg:x12;
val_offset:23*FLEN/8; rmval:dyn; correctval:??; testreg:x7;
fcsr_val:0*/
TEST_FPID_OP(fcvt.w.d, x23, f0, dyn, 0, 0, x12, 23*FLEN/8, x15, x16, x7,FLREG)
inst_24:// rs1==f6, rd==x3,
/* opcode: fcvt.w.d ; op1:f6; dest:x3; op1val:0x0; valaddr_reg:x12;
val_offset:24*FLEN/8; rmval:dyn; correctval:??; testreg:x7;
fcsr_val:0*/
TEST_FPID_OP(fcvt.w.d, x3, f6, dyn, 0, 0, x12, 24*FLEN/8, x15, x16, x7,FLREG)
RVTEST_VALBASEUPD(x3,test_dataset_1)
inst_25:// rs1==f27, rd==x15,
/* opcode: fcvt.w.d ; op1:f27; dest:x15; op1val:0x0; valaddr_reg:x3;
val_offset:0*FLEN/8; rmval:dyn; correctval:??; testreg:x7;
fcsr_val:0*/
TEST_FPID_OP(fcvt.w.d, x15, f27, dyn, 0, 0, x3, 0*FLEN/8, x4, x16, x7,FLREG)
inst_26:// rs1==f28, rd==x12,
/* opcode: fcvt.w.d ; op1:f28; dest:x12; op1val:0x0; valaddr_reg:x3;
val_offset:1*FLEN/8; rmval:dyn; correctval:??; testreg:x7;
fcsr_val:0*/
TEST_FPID_OP(fcvt.w.d, x12, f28, dyn, 0, 0, x3, 1*FLEN/8, x4, x16, x7,FLREG)
inst_27:// rs1==f11, rd==x7,
/* opcode: fcvt.w.d ; op1:f11; dest:x7; op1val:0x0; valaddr_reg:x3;
val_offset:2*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
fcsr_val:0*/
TEST_FPID_OP(fcvt.w.d, x7, f11, dyn, 0, 0, x3, 2*FLEN/8, x4, x16, x2,FLREG)
RVTEST_SIGBASE(x1,signature_x1_0)
inst_28:// rs1==f4, rd==x20,
/* opcode: fcvt.w.d ; op1:f4; dest:x20; op1val:0x0; valaddr_reg:x3;
val_offset:3*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
fcsr_val:0*/
TEST_FPID_OP(fcvt.w.d, x20, f4, dyn, 0, 0, x3, 3*FLEN/8, x4, x1, x2,FLREG)
inst_29:// rs1==f15, rd==x22,
/* opcode: fcvt.w.d ; op1:f15; dest:x22; op1val:0x0; valaddr_reg:x3;
val_offset:4*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
fcsr_val:0*/
TEST_FPID_OP(fcvt.w.d, x22, f15, dyn, 0, 0, x3, 4*FLEN/8, x4, x1, x2,FLREG)
inst_30:// rs1==f5, rd==x21,
/* opcode: fcvt.w.d ; op1:f5; dest:x21; op1val:0x0; valaddr_reg:x3;
val_offset:5*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
fcsr_val:0*/
TEST_FPID_OP(fcvt.w.d, x21, f5, dyn, 0, 0, x3, 5*FLEN/8, x4, x1, x2,FLREG)
inst_31:// rs1==f7, rd==x16,
/* opcode: fcvt.w.d ; op1:f7; dest:x16; op1val:0x0; valaddr_reg:x3;
val_offset:6*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
fcsr_val:0*/
TEST_FPID_OP(fcvt.w.d, x16, f7, dyn, 0, 0, x3, 6*FLEN/8, x4, x1, x2,FLREG)
inst_32://
/* opcode: fcvt.w.d ; op1:f31; dest:x31; op1val:0x0; valaddr_reg:x3;
val_offset:7*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
fcsr_val:0*/
TEST_FPID_OP(fcvt.w.d, x31, f31, dyn, 0, 0, x3, 7*FLEN/8, x4, x1, x2,FLREG)
#endif
RVTEST_CODE_END
RVMODEL_HALT
RVTEST_DATA_BEGIN
.align 4
rvtest_data:
.word 0xbabecafe
.word 0xabecafeb
.word 0xbecafeba
.word 0xecafebab
test_dataset_0:
NAN_BOXED(9218868437227405313,64,FLEN)
NAN_BOXED(9220181987118721706,64,FLEN)
NAN_BOXED(9221120237041090561,64,FLEN)
NAN_BOXED(9222246136947933185,64,FLEN)
NAN_BOXED(18442240474082181121,64,FLEN)
NAN_BOXED(18443554023973497514,64,FLEN)
NAN_BOXED(18444492273895866369,64,FLEN)
NAN_BOXED(18445618173802708993,64,FLEN)
NAN_BOXED(0,64,FLEN)
NAN_BOXED(0,64,FLEN)
NAN_BOXED(0,64,FLEN)
NAN_BOXED(0,64,FLEN)
NAN_BOXED(0,64,FLEN)
NAN_BOXED(0,64,FLEN)
NAN_BOXED(0,64,FLEN)
NAN_BOXED(0,64,FLEN)
NAN_BOXED(0,64,FLEN)
NAN_BOXED(0,64,FLEN)
NAN_BOXED(0,64,FLEN)
NAN_BOXED(0,64,FLEN)
NAN_BOXED(0,64,FLEN)
NAN_BOXED(0,64,FLEN)
NAN_BOXED(0,64,FLEN)
NAN_BOXED(0,64,FLEN)
NAN_BOXED(0,64,FLEN)
test_dataset_1:
NAN_BOXED(0,64,FLEN)
NAN_BOXED(0,64,FLEN)
NAN_BOXED(0,64,FLEN)
NAN_BOXED(0,64,FLEN)
NAN_BOXED(0,64,FLEN)
NAN_BOXED(0,64,FLEN)
NAN_BOXED(0,64,FLEN)
NAN_BOXED(0,64,FLEN)
RVTEST_DATA_END
RVMODEL_DATA_BEGIN
rvtest_sig_begin:
sig_begin_canary:
CANARY;
signature_x16_0:
.fill 0*((SIGALIGN)/4),4,0xdeadbeef
signature_x16_1:
.fill 56*((SIGALIGN)/4),4,0xdeadbeef
signature_x1_0:
.fill 10*((SIGALIGN)/4),4,0xdeadbeef
#ifdef rvtest_mtrap_routine
tsig_begin_canary:
CANARY;
tsig_begin_canary:
CANARY;
mtrap_sigptr:
.fill 64*(XLEN/32),4,0xdeadbeef
tsig_end_canary:
CANARY;
tsig_end_canary:
CANARY;
#endif
#ifdef rvtest_gpr_save
gpr_save:
.fill 32*XLEN/32,4,0xdeadbeef
#endif
sig_end_canary:
CANARY;
rvtest_sig_end:
RVMODEL_DATA_END

330
vendor/riscv-arch-tests/riscv-test-suite/rv32i_m/D/src/fcvt.w.d_b28-01.S vendored
View file

@ -1,330 +0,0 @@
// -----------
// This file was generated by riscv_ctg (https://github.com/riscv-software-src/riscv-ctg)
// version : 0.7.1
// timestamp : Fri Jun 17 14:03:36 2022 GMT
// usage : riscv_ctg \
// -- cgf // --cgf /scratch/pawan/work/normalised/RV32D/fcvt.w.d.cgf \
\
// -- xlen 32 \
// --randomize \
// -----------
//
// -----------
// Copyright (c) 2020. RISC-V International. All rights reserved.
// SPDX-License-Identifier: BSD-3-Clause
// -----------
//
// This assembly file tests the fcvt.w.d instruction of the RISC-V RV32FD_Zicsr,RV64FD_Zicsr extension for the fcvt.w.d_b28 covergroup.
//
#include "model_test.h"
#include "arch_test.h"
RVTEST_ISA("RV32IFD_Zicsr,RV64IFD_Zicsr")
.section .text.init
.org 0x80
.globl rvtest_entry_point
rvtest_entry_point:
RVMODEL_BOOT
RVTEST_CODE_BEGIN
#ifdef TEST_CASE_1
RVTEST_CASE(0,"//check ISA:=regex(.*I.*D.*);def TEST_CASE_1=True;",fcvt.w.d_b28)
RVTEST_FP_ENABLE()
RVTEST_VALBASEUPD(x10,test_dataset_0)
RVTEST_SIGBASE(x14,signature_x14_1)
inst_0:// rs1==f21, rd==x28,fs1 == 0 and fe1 == 0x000 and fm1 == 0x0000000000000 and fcsr == 0x0 and rm_val == 7
/* opcode: fcvt.w.d ; op1:f21; dest:x28; op1val:0x0; valaddr_reg:x10;
val_offset:0*FLEN/8; rmval:dyn; correctval:??; testreg:x5;
fcsr_val:0*/
TEST_FPID_OP(fcvt.w.d, x28, f21, dyn, 0, 0, x10, 0*FLEN/8, x15, x14, x5,FLREG)
inst_1:// rs1==f12, rd==x3,fs1 == 0 and fe1 == 0x3fe and fm1 == 0x248ee18215dfa and fcsr == 0x0 and rm_val == 7
/* opcode: fcvt.w.d ; op1:f12; dest:x3; op1val:0x3fe248ee18215dfa; valaddr_reg:x10;
val_offset:1*FLEN/8; rmval:dyn; correctval:??; testreg:x5;
fcsr_val:0*/
TEST_FPID_OP(fcvt.w.d, x3, f12, dyn, 0, 0, x10, 1*FLEN/8, x15, x14, x5,FLREG)
inst_2:// rs1==f5, rd==x7,fs1 == 0 and fe1 == 0x3ff and fm1 == 0x0000000000000 and fcsr == 0x0 and rm_val == 7
/* opcode: fcvt.w.d ; op1:f5; dest:x7; op1val:0x3ff0000000000000; valaddr_reg:x10;
val_offset:2*FLEN/8; rmval:dyn; correctval:??; testreg:x5;
fcsr_val:0*/
TEST_FPID_OP(fcvt.w.d, x7, f5, dyn, 0, 0, x10, 2*FLEN/8, x15, x14, x5,FLREG)
inst_3:// rs1==f4, rd==x1,fs1 == 0 and fe1 == 0x3ff and fm1 == 0x4000000000000 and fcsr == 0x0 and rm_val == 7
/* opcode: fcvt.w.d ; op1:f4; dest:x1; op1val:0x3ff4000000000000; valaddr_reg:x10;
val_offset:3*FLEN/8; rmval:dyn; correctval:??; testreg:x5;
fcsr_val:0*/
TEST_FPID_OP(fcvt.w.d, x1, f4, dyn, 0, 0, x10, 3*FLEN/8, x15, x14, x5,FLREG)
inst_4:// rs1==f10, rd==x9,fs1 == 0 and fe1 == 0x3ff and fm1 == 0x8000000000000 and fcsr == 0x0 and rm_val == 7
/* opcode: fcvt.w.d ; op1:f10; dest:x9; op1val:0x3ff8000000000000; valaddr_reg:x10;
val_offset:4*FLEN/8; rmval:dyn; correctval:??; testreg:x5;
fcsr_val:0*/
TEST_FPID_OP(fcvt.w.d, x9, f10, dyn, 0, 0, x10, 4*FLEN/8, x15, x14, x5,FLREG)
inst_5:// rs1==f9, rd==x16,fs1 == 0 and fe1 == 0x3ff and fm1 == 0xc000000000000 and fcsr == 0x0 and rm_val == 7
/* opcode: fcvt.w.d ; op1:f9; dest:x16; op1val:0x3ffc000000000000; valaddr_reg:x10;
val_offset:5*FLEN/8; rmval:dyn; correctval:??; testreg:x5;
fcsr_val:0*/
TEST_FPID_OP(fcvt.w.d, x16, f9, dyn, 0, 0, x10, 5*FLEN/8, x15, x14, x5,FLREG)
inst_6:// rs1==f2, rd==x22,fs1 == 0 and fe1 == 0x400 and fm1 == 0x0000000000000 and fcsr == 0x0 and rm_val == 7
/* opcode: fcvt.w.d ; op1:f2; dest:x22; op1val:0x4000000000000000; valaddr_reg:x10;
val_offset:6*FLEN/8; rmval:dyn; correctval:??; testreg:x5;
fcsr_val:0*/
TEST_FPID_OP(fcvt.w.d, x22, f2, dyn, 0, 0, x10, 6*FLEN/8, x15, x14, x5,FLREG)
inst_7:// rs1==f1, rd==x17,fs1 == 0 and fe1 == 0x400 and fm1 == 0x2000000000000 and fcsr == 0x0 and rm_val == 7
/* opcode: fcvt.w.d ; op1:f1; dest:x17; op1val:0x4002000000000000; valaddr_reg:x10;
val_offset:7*FLEN/8; rmval:dyn; correctval:??; testreg:x5;
fcsr_val:0*/
TEST_FPID_OP(fcvt.w.d, x17, f1, dyn, 0, 0, x10, 7*FLEN/8, x15, x14, x5,FLREG)
inst_8:// rs1==f17, rd==x11,fs1 == 0 and fe1 == 0x400 and fm1 == 0x4000000000000 and fcsr == 0x0 and rm_val == 7
/* opcode: fcvt.w.d ; op1:f17; dest:x11; op1val:0x4004000000000000; valaddr_reg:x10;
val_offset:8*FLEN/8; rmval:dyn; correctval:??; testreg:x5;
fcsr_val:0*/
TEST_FPID_OP(fcvt.w.d, x11, f17, dyn, 0, 0, x10, 8*FLEN/8, x15, x14, x5,FLREG)
inst_9:// rs1==f13, rd==x31,fs1 == 0 and fe1 == 0x400 and fm1 == 0x6000000000000 and fcsr == 0x0 and rm_val == 7
/* opcode: fcvt.w.d ; op1:f13; dest:x31; op1val:0x4006000000000000; valaddr_reg:x10;
val_offset:9*FLEN/8; rmval:dyn; correctval:??; testreg:x5;
fcsr_val:0*/
TEST_FPID_OP(fcvt.w.d, x31, f13, dyn, 0, 0, x10, 9*FLEN/8, x15, x14, x5,FLREG)
inst_10:// rs1==f14, rd==x18,fs1 == 0 and fe1 == 0x43c and fm1 == 0xb72eb13dc494a and fcsr == 0x0 and rm_val == 7
/* opcode: fcvt.w.d ; op1:f14; dest:x18; op1val:0x43cb72eb13dc494a; valaddr_reg:x10;
val_offset:10*FLEN/8; rmval:dyn; correctval:??; testreg:x5;
fcsr_val:0*/
TEST_FPID_OP(fcvt.w.d, x18, f14, dyn, 0, 0, x10, 10*FLEN/8, x15, x14, x5,FLREG)
inst_11:// rs1==f20, rd==x6,fs1 == 0 and fe1 == 0x43e and fm1 == 0x0000000000000 and fcsr == 0x0 and rm_val == 7
/* opcode: fcvt.w.d ; op1:f20; dest:x6; op1val:0x43e0000000000000; valaddr_reg:x10;
val_offset:11*FLEN/8; rmval:dyn; correctval:??; testreg:x5;
fcsr_val:0*/
TEST_FPID_OP(fcvt.w.d, x6, f20, dyn, 0, 0, x10, 11*FLEN/8, x15, x14, x5,FLREG)
inst_12:// rs1==f8, rd==x29,fs1 == 0 and fe1 == 0x7ff and fm1 == 0x0000000000000 and fcsr == 0x0 and rm_val == 7
/* opcode: fcvt.w.d ; op1:f8; dest:x29; op1val:0x7ff0000000000000; valaddr_reg:x10;
val_offset:12*FLEN/8; rmval:dyn; correctval:??; testreg:x5;
fcsr_val:0*/
TEST_FPID_OP(fcvt.w.d, x29, f8, dyn, 0, 0, x10, 12*FLEN/8, x15, x14, x5,FLREG)
inst_13:// rs1==f16, rd==x12,fs1 == 0 and fe1 == 0x7ff and fm1 == 0x0000000000001 and fcsr == 0x0 and rm_val == 7
/* opcode: fcvt.w.d ; op1:f16; dest:x12; op1val:0x7ff0000000000001; valaddr_reg:x10;
val_offset:13*FLEN/8; rmval:dyn; correctval:??; testreg:x5;
fcsr_val:0*/
TEST_FPID_OP(fcvt.w.d, x12, f16, dyn, 0, 0, x10, 13*FLEN/8, x15, x14, x5,FLREG)
inst_14:// rs1==f3, rd==x23,fs1 == 0 and fe1 == 0x7ff and fm1 == 0x8000000000001 and fcsr == 0x0 and rm_val == 7
/* opcode: fcvt.w.d ; op1:f3; dest:x23; op1val:0x7ff8000000000001; valaddr_reg:x10;
val_offset:14*FLEN/8; rmval:dyn; correctval:??; testreg:x5;
fcsr_val:0*/
TEST_FPID_OP(fcvt.w.d, x23, f3, dyn, 0, 0, x10, 14*FLEN/8, x15, x14, x5,FLREG)
inst_15:// rs1==f27, rd==x13,fs1 == 1 and fe1 == 0x000 and fm1 == 0x0000000000000 and fcsr == 0x0 and rm_val == 7
/* opcode: fcvt.w.d ; op1:f27; dest:x13; op1val:0x8000000000000000; valaddr_reg:x10;
val_offset:15*FLEN/8; rmval:dyn; correctval:??; testreg:x5;
fcsr_val:0*/
TEST_FPID_OP(fcvt.w.d, x13, f27, dyn, 0, 0, x10, 15*FLEN/8, x15, x14, x5,FLREG)
inst_16:// rs1==f26, rd==x8,fs1 == 1 and fe1 == 0x3f8 and fm1 == 0x0000000000000 and fcsr == 0x0 and rm_val == 7
/* opcode: fcvt.w.d ; op1:f26; dest:x8; op1val:0xbf80000000000000; valaddr_reg:x10;
val_offset:16*FLEN/8; rmval:dyn; correctval:??; testreg:x5;
fcsr_val:0*/
TEST_FPID_OP(fcvt.w.d, x8, f26, dyn, 0, 0, x10, 16*FLEN/8, x15, x14, x5,FLREG)
inst_17:// rs1==f22, rd==x2,fs1 == 1 and fe1 == 0x3fd and fm1 == 0xb008d57e19f88 and fcsr == 0x0 and rm_val == 7
/* opcode: fcvt.w.d ; op1:f22; dest:x2; op1val:0xbfdb008d57e19f88; valaddr_reg:x10;
val_offset:17*FLEN/8; rmval:dyn; correctval:??; testreg:x5;
fcsr_val:0*/
TEST_FPID_OP(fcvt.w.d, x2, f22, dyn, 0, 0, x10, 17*FLEN/8, x15, x14, x5,FLREG)
inst_18:// rs1==f25, rd==x20,fs1 == 1 and fe1 == 0x3ff and fm1 == 0x4000000000000 and fcsr == 0x0 and rm_val == 7
/* opcode: fcvt.w.d ; op1:f25; dest:x20; op1val:0xbff4000000000000; valaddr_reg:x10;
val_offset:18*FLEN/8; rmval:dyn; correctval:??; testreg:x5;
fcsr_val:0*/
TEST_FPID_OP(fcvt.w.d, x20, f25, dyn, 0, 0, x10, 18*FLEN/8, x15, x14, x5,FLREG)
inst_19:// rs1==f31, rd==x24,fs1 == 1 and fe1 == 0x3ff and fm1 == 0x8000000000000 and fcsr == 0x0 and rm_val == 7
/* opcode: fcvt.w.d ; op1:f31; dest:x24; op1val:0xbff8000000000000; valaddr_reg:x10;
val_offset:19*FLEN/8; rmval:dyn; correctval:??; testreg:x5;
fcsr_val:0*/
TEST_FPID_OP(fcvt.w.d, x24, f31, dyn, 0, 0, x10, 19*FLEN/8, x15, x14, x5,FLREG)
inst_20:// rs1==f19, rd==x30,fs1 == 1 and fe1 == 0x3ff and fm1 == 0xc000000000000 and fcsr == 0x0 and rm_val == 7
/* opcode: fcvt.w.d ; op1:f19; dest:x30; op1val:0xbffc000000000000; valaddr_reg:x10;
val_offset:20*FLEN/8; rmval:dyn; correctval:??; testreg:x5;
fcsr_val:0*/
TEST_FPID_OP(fcvt.w.d, x30, f19, dyn, 0, 0, x10, 20*FLEN/8, x15, x14, x5,FLREG)
inst_21:// rs1==f6, rd==x25,fs1 == 1 and fe1 == 0x400 and fm1 == 0x0000000000000 and fcsr == 0x0 and rm_val == 7
/* opcode: fcvt.w.d ; op1:f6; dest:x25; op1val:0xc000000000000000; valaddr_reg:x10;
val_offset:21*FLEN/8; rmval:dyn; correctval:??; testreg:x5;
fcsr_val:0*/
TEST_FPID_OP(fcvt.w.d, x25, f6, dyn, 0, 0, x10, 21*FLEN/8, x15, x14, x5,FLREG)
inst_22:// rs1==f18, rd==x4,fs1 == 1 and fe1 == 0x400 and fm1 == 0x2000000000000 and fcsr == 0x0 and rm_val == 7
/* opcode: fcvt.w.d ; op1:f18; dest:x4; op1val:0xc002000000000000; valaddr_reg:x10;
val_offset:22*FLEN/8; rmval:dyn; correctval:??; testreg:x5;
fcsr_val:0*/
TEST_FPID_OP(fcvt.w.d, x4, f18, dyn, 0, 0, x10, 22*FLEN/8, x15, x14, x5,FLREG)
inst_23:// rs1==f23, rd==x26,fs1 == 1 and fe1 == 0x400 and fm1 == 0x4000000000000 and fcsr == 0x0 and rm_val == 7
/* opcode: fcvt.w.d ; op1:f23; dest:x26; op1val:0xc004000000000000; valaddr_reg:x10;
val_offset:23*FLEN/8; rmval:dyn; correctval:??; testreg:x5;
fcsr_val:0*/
TEST_FPID_OP(fcvt.w.d, x26, f23, dyn, 0, 0, x10, 23*FLEN/8, x15, x14, x5,FLREG)
RVTEST_VALBASEUPD(x3,test_dataset_1)
inst_24:// rs1==f29, rd==x10,fs1 == 1 and fe1 == 0x400 and fm1 == 0x6000000000000 and fcsr == 0x0 and rm_val == 7
/* opcode: fcvt.w.d ; op1:f29; dest:x10; op1val:0xc006000000000000; valaddr_reg:x3;
val_offset:0*FLEN/8; rmval:dyn; correctval:??; testreg:x5;
fcsr_val:0*/
TEST_FPID_OP(fcvt.w.d, x10, f29, dyn, 0, 0, x3, 0*FLEN/8, x4, x14, x5,FLREG)
inst_25:// rs1==f24, rd==x15,fs1 == 1 and fe1 == 0x43d and fm1 == 0x967a4ae26514c and fcsr == 0x0 and rm_val == 7
/* opcode: fcvt.w.d ; op1:f24; dest:x15; op1val:0xc3d967a4ae26514c; valaddr_reg:x3;
val_offset:1*FLEN/8; rmval:dyn; correctval:??; testreg:x5;
fcsr_val:0*/
TEST_FPID_OP(fcvt.w.d, x15, f24, dyn, 0, 0, x3, 1*FLEN/8, x4, x14, x5,FLREG)
inst_26:// rs1==f0, rd==x5,fs1 == 1 and fe1 == 0x43e and fm1 == 0x0000000000000 and fcsr == 0x0 and rm_val == 7
/* opcode: fcvt.w.d ; op1:f0; dest:x5; op1val:0xc3e0000000000000; valaddr_reg:x3;
val_offset:2*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
fcsr_val:0*/
TEST_FPID_OP(fcvt.w.d, x5, f0, dyn, 0, 0, x3, 2*FLEN/8, x4, x14, x2,FLREG)
RVTEST_SIGBASE(x1,signature_x1_0)
inst_27:// rs1==f30, rd==x27,fs1 == 1 and fe1 == 0x7ff and fm1 == 0x0000000000000 and fcsr == 0x0 and rm_val == 7
/* opcode: fcvt.w.d ; op1:f30; dest:x27; op1val:0xfff0000000000000; valaddr_reg:x3;
val_offset:3*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
fcsr_val:0*/
TEST_FPID_OP(fcvt.w.d, x27, f30, dyn, 0, 0, x3, 3*FLEN/8, x4, x1, x2,FLREG)
inst_28:// rs1==f15, rd==x14,
/* opcode: fcvt.w.d ; op1:f15; dest:x14; op1val:0x0; valaddr_reg:x3;
val_offset:4*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
fcsr_val:0*/
TEST_FPID_OP(fcvt.w.d, x14, f15, dyn, 0, 0, x3, 4*FLEN/8, x4, x1, x2,FLREG)
inst_29:// rs1==f28, rd==x21,
/* opcode: fcvt.w.d ; op1:f28; dest:x21; op1val:0x0; valaddr_reg:x3;
val_offset:5*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
fcsr_val:0*/
TEST_FPID_OP(fcvt.w.d, x21, f28, dyn, 0, 0, x3, 5*FLEN/8, x4, x1, x2,FLREG)
inst_30:// rs1==f11, rd==x19,
/* opcode: fcvt.w.d ; op1:f11; dest:x19; op1val:0x0; valaddr_reg:x3;
val_offset:6*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
fcsr_val:0*/
TEST_FPID_OP(fcvt.w.d, x19, f11, dyn, 0, 0, x3, 6*FLEN/8, x4, x1, x2,FLREG)
inst_31:// rs1==f7, rd==x0,
/* opcode: fcvt.w.d ; op1:f7; dest:x0; op1val:0x0; valaddr_reg:x3;
val_offset:7*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
fcsr_val:0*/
TEST_FPID_OP(fcvt.w.d, x0, f7, dyn, 0, 0, x3, 7*FLEN/8, x4, x1, x2,FLREG)
inst_32://
/* opcode: fcvt.w.d ; op1:f31; dest:x31; op1val:0x0; valaddr_reg:x3;
val_offset:8*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
fcsr_val:0*/
TEST_FPID_OP(fcvt.w.d, x31, f31, dyn, 0, 0, x3, 8*FLEN/8, x4, x1, x2,FLREG)
#endif
RVTEST_CODE_END
RVMODEL_HALT
RVTEST_DATA_BEGIN
.align 4
rvtest_data:
.word 0xbabecafe
.word 0xabecafeb
.word 0xbecafeba
.word 0xecafebab
test_dataset_0:
NAN_BOXED(0,64,FLEN)
NAN_BOXED(4603321956570324474,64,FLEN)
NAN_BOXED(4607182418800017408,64,FLEN)
NAN_BOXED(4608308318706860032,64,FLEN)
NAN_BOXED(4609434218613702656,64,FLEN)
NAN_BOXED(4610560118520545280,64,FLEN)
NAN_BOXED(4611686018427387904,64,FLEN)
NAN_BOXED(4612248968380809216,64,FLEN)
NAN_BOXED(4612811918334230528,64,FLEN)
NAN_BOXED(4613374868287651840,64,FLEN)
NAN_BOXED(4885124574789519690,64,FLEN)
NAN_BOXED(4890909195324358656,64,FLEN)
NAN_BOXED(9218868437227405312,64,FLEN)
NAN_BOXED(9218868437227405313,64,FLEN)
NAN_BOXED(9221120237041090561,64,FLEN)
NAN_BOXED(9223372036854775808,64,FLEN)
NAN_BOXED(13799029258263199744,64,FLEN)
NAN_BOXED(13824644088208662408,64,FLEN)
NAN_BOXED(13831680355561635840,64,FLEN)
NAN_BOXED(13832806255468478464,64,FLEN)
NAN_BOXED(13833932155375321088,64,FLEN)
NAN_BOXED(13835058055282163712,64,FLEN)
NAN_BOXED(13835621005235585024,64,FLEN)
NAN_BOXED(13836183955189006336,64,FLEN)
test_dataset_1:
NAN_BOXED(13836746905142427648,64,FLEN)
NAN_BOXED(14112424864336204108,64,FLEN)
NAN_BOXED(14114281232179134464,64,FLEN)
NAN_BOXED(18442240474082181120,64,FLEN)
NAN_BOXED(0,64,FLEN)
NAN_BOXED(0,64,FLEN)
NAN_BOXED(0,64,FLEN)
NAN_BOXED(0,64,FLEN)
NAN_BOXED(0,64,FLEN)
RVTEST_DATA_END
RVMODEL_DATA_BEGIN
rvtest_sig_begin:
sig_begin_canary:
CANARY;
signature_x14_0:
.fill 0*((SIGALIGN)/4),4,0xdeadbeef
signature_x14_1:
.fill 54*((SIGALIGN)/4),4,0xdeadbeef
signature_x1_0:
.fill 12*((SIGALIGN)/4),4,0xdeadbeef
#ifdef rvtest_mtrap_routine
tsig_begin_canary:
CANARY;
tsig_begin_canary:
CANARY;
mtrap_sigptr:
.fill 64*(XLEN/32),4,0xdeadbeef
tsig_end_canary:
CANARY;
tsig_end_canary:
CANARY;
#endif
#ifdef rvtest_gpr_save
gpr_save:
.fill 32*XLEN/32,4,0xdeadbeef
#endif
sig_end_canary:
CANARY;
rvtest_sig_end:
RVMODEL_DATA_END

666
vendor/riscv-arch-tests/riscv-test-suite/rv32i_m/D/src/fcvt.w.d_b29-01.S vendored
View file

@ -1,666 +0,0 @@
// -----------
// This file was generated by riscv_ctg (https://github.com/riscv-software-src/riscv-ctg)
// version : 0.7.1
// timestamp : Fri Jun 17 14:03:36 2022 GMT
// usage : riscv_ctg \
// -- cgf // --cgf /scratch/pawan/work/normalised/RV32D/fcvt.w.d.cgf \
\
// -- xlen 32 \
// --randomize \
// -----------
//
// -----------
// Copyright (c) 2020. RISC-V International. All rights reserved.
// SPDX-License-Identifier: BSD-3-Clause
// -----------
//
// This assembly file tests the fcvt.w.d instruction of the RISC-V RV32FD_Zicsr,RV64FD_Zicsr extension for the fcvt.w.d_b29 covergroup.
//
#include "model_test.h"
#include "arch_test.h"
RVTEST_ISA("RV32IFD_Zicsr,RV64IFD_Zicsr")
.section .text.init
.org 0x80
.globl rvtest_entry_point
rvtest_entry_point:
RVMODEL_BOOT
RVTEST_CODE_BEGIN
#ifdef TEST_CASE_1
RVTEST_CASE(0,"//check ISA:=regex(.*I.*D.*);def TEST_CASE_1=True;",fcvt.w.d_b29)
RVTEST_FP_ENABLE()
RVTEST_VALBASEUPD(x16,test_dataset_0)
RVTEST_SIGBASE(x1,signature_x1_1)
inst_0:// rs1==f15, rd==x31,fs1 == 0 and fe1 == 0x3fc and fm1 == 0x08574923b8698 and fcsr == 0x0 and rm_val == 7
/* opcode: fcvt.w.d ; op1:f15; dest:x31; op1val:0x3fc08574923b8698; valaddr_reg:x16;
val_offset:0*FLEN/8; rmval:dyn; correctval:??; testreg:x11;
fcsr_val:0*/
TEST_FPID_OP(fcvt.w.d, x31, f15, dyn, 0, 0, x16, 0*FLEN/8, x20, x1, x11,FLREG)
inst_1:// rs1==f18, rd==x29,fs1 == 0 and fe1 == 0x3fc and fm1 == 0x08574923b8698 and fcsr == 0x20 and rm_val == 7
/* opcode: fcvt.w.d ; op1:f18; dest:x29; op1val:0x3fc08574923b8698; valaddr_reg:x16;
val_offset:1*FLEN/8; rmval:dyn; correctval:??; testreg:x11;
fcsr_val:32*/
TEST_FPID_OP(fcvt.w.d, x29, f18, dyn, 32, 0, x16, 1*FLEN/8, x20, x1, x11,FLREG)
inst_2:// rs1==f6, rd==x14,fs1 == 0 and fe1 == 0x3fc and fm1 == 0x08574923b8698 and fcsr == 0x40 and rm_val == 7
/* opcode: fcvt.w.d ; op1:f6; dest:x14; op1val:0x3fc08574923b8698; valaddr_reg:x16;
val_offset:2*FLEN/8; rmval:dyn; correctval:??; testreg:x11;
fcsr_val:64*/
TEST_FPID_OP(fcvt.w.d, x14, f6, dyn, 64, 0, x16, 2*FLEN/8, x20, x1, x11,FLREG)
inst_3:// rs1==f8, rd==x23,fs1 == 0 and fe1 == 0x3fc and fm1 == 0x08574923b8698 and fcsr == 0x60 and rm_val == 7
/* opcode: fcvt.w.d ; op1:f8; dest:x23; op1val:0x3fc08574923b8698; valaddr_reg:x16;
val_offset:3*FLEN/8; rmval:dyn; correctval:??; testreg:x11;
fcsr_val:96*/
TEST_FPID_OP(fcvt.w.d, x23, f8, dyn, 96, 0, x16, 3*FLEN/8, x20, x1, x11,FLREG)
inst_4:// rs1==f14, rd==x10,fs1 == 0 and fe1 == 0x3fc and fm1 == 0x08574923b8698 and fcsr == 0x80 and rm_val == 7
/* opcode: fcvt.w.d ; op1:f14; dest:x10; op1val:0x3fc08574923b8698; valaddr_reg:x16;
val_offset:4*FLEN/8; rmval:dyn; correctval:??; testreg:x11;
fcsr_val:128*/
TEST_FPID_OP(fcvt.w.d, x10, f14, dyn, 128, 0, x16, 4*FLEN/8, x20, x1, x11,FLREG)
inst_5:// rs1==f26, rd==x18,fs1 == 0 and fe1 == 0x3fc and fm1 == 0x08574923b8699 and fcsr == 0x0 and rm_val == 7
/* opcode: fcvt.w.d ; op1:f26; dest:x18; op1val:0x3fc08574923b8699; valaddr_reg:x16;
val_offset:5*FLEN/8; rmval:dyn; correctval:??; testreg:x11;
fcsr_val:0*/
TEST_FPID_OP(fcvt.w.d, x18, f26, dyn, 0, 0, x16, 5*FLEN/8, x20, x1, x11,FLREG)
inst_6:// rs1==f24, rd==x8,fs1 == 0 and fe1 == 0x3fc and fm1 == 0x08574923b8699 and fcsr == 0x20 and rm_val == 7
/* opcode: fcvt.w.d ; op1:f24; dest:x8; op1val:0x3fc08574923b8699; valaddr_reg:x16;
val_offset:6*FLEN/8; rmval:dyn; correctval:??; testreg:x11;
fcsr_val:32*/
TEST_FPID_OP(fcvt.w.d, x8, f24, dyn, 32, 0, x16, 6*FLEN/8, x20, x1, x11,FLREG)
inst_7:// rs1==f4, rd==x22,fs1 == 0 and fe1 == 0x3fc and fm1 == 0x08574923b8699 and fcsr == 0x40 and rm_val == 7
/* opcode: fcvt.w.d ; op1:f4; dest:x22; op1val:0x3fc08574923b8699; valaddr_reg:x16;
val_offset:7*FLEN/8; rmval:dyn; correctval:??; testreg:x11;
fcsr_val:64*/
TEST_FPID_OP(fcvt.w.d, x22, f4, dyn, 64, 0, x16, 7*FLEN/8, x20, x1, x11,FLREG)
inst_8:// rs1==f19, rd==x6,fs1 == 0 and fe1 == 0x3fc and fm1 == 0x08574923b8699 and fcsr == 0x60 and rm_val == 7
/* opcode: fcvt.w.d ; op1:f19; dest:x6; op1val:0x3fc08574923b8699; valaddr_reg:x16;
val_offset:8*FLEN/8; rmval:dyn; correctval:??; testreg:x11;
fcsr_val:96*/
TEST_FPID_OP(fcvt.w.d, x6, f19, dyn, 96, 0, x16, 8*FLEN/8, x20, x1, x11,FLREG)
inst_9:// rs1==f0, rd==x26,fs1 == 0 and fe1 == 0x3fc and fm1 == 0x08574923b8699 and fcsr == 0x80 and rm_val == 7
/* opcode: fcvt.w.d ; op1:f0; dest:x26; op1val:0x3fc08574923b8699; valaddr_reg:x16;
val_offset:9*FLEN/8; rmval:dyn; correctval:??; testreg:x11;
fcsr_val:128*/
TEST_FPID_OP(fcvt.w.d, x26, f0, dyn, 128, 0, x16, 9*FLEN/8, x20, x1, x11,FLREG)
inst_10:// rs1==f9, rd==x9,fs1 == 0 and fe1 == 0x3fc and fm1 == 0x08574923b869a and fcsr == 0x0 and rm_val == 7
/* opcode: fcvt.w.d ; op1:f9; dest:x9; op1val:0x3fc08574923b869a; valaddr_reg:x16;
val_offset:10*FLEN/8; rmval:dyn; correctval:??; testreg:x11;
fcsr_val:0*/
TEST_FPID_OP(fcvt.w.d, x9, f9, dyn, 0, 0, x16, 10*FLEN/8, x20, x1, x11,FLREG)
inst_11:// rs1==f22, rd==x27,fs1 == 0 and fe1 == 0x3fc and fm1 == 0x08574923b869a and fcsr == 0x20 and rm_val == 7
/* opcode: fcvt.w.d ; op1:f22; dest:x27; op1val:0x3fc08574923b869a; valaddr_reg:x16;
val_offset:11*FLEN/8; rmval:dyn; correctval:??; testreg:x11;
fcsr_val:32*/
TEST_FPID_OP(fcvt.w.d, x27, f22, dyn, 32, 0, x16, 11*FLEN/8, x20, x1, x11,FLREG)
inst_12:// rs1==f2, rd==x17,fs1 == 0 and fe1 == 0x3fc and fm1 == 0x08574923b869a and fcsr == 0x40 and rm_val == 7
/* opcode: fcvt.w.d ; op1:f2; dest:x17; op1val:0x3fc08574923b869a; valaddr_reg:x16;
val_offset:12*FLEN/8; rmval:dyn; correctval:??; testreg:x11;
fcsr_val:64*/
TEST_FPID_OP(fcvt.w.d, x17, f2, dyn, 64, 0, x16, 12*FLEN/8, x20, x1, x11,FLREG)
inst_13:// rs1==f1, rd==x21,fs1 == 0 and fe1 == 0x3fc and fm1 == 0x08574923b869a and fcsr == 0x60 and rm_val == 7
/* opcode: fcvt.w.d ; op1:f1; dest:x21; op1val:0x3fc08574923b869a; valaddr_reg:x16;
val_offset:13*FLEN/8; rmval:dyn; correctval:??; testreg:x11;
fcsr_val:96*/
TEST_FPID_OP(fcvt.w.d, x21, f1, dyn, 96, 0, x16, 13*FLEN/8, x20, x1, x11,FLREG)
inst_14:// rs1==f3, rd==x5,fs1 == 0 and fe1 == 0x3fc and fm1 == 0x08574923b869a and fcsr == 0x80 and rm_val == 7
/* opcode: fcvt.w.d ; op1:f3; dest:x5; op1val:0x3fc08574923b869a; valaddr_reg:x16;
val_offset:14*FLEN/8; rmval:dyn; correctval:??; testreg:x11;
fcsr_val:128*/
TEST_FPID_OP(fcvt.w.d, x5, f3, dyn, 128, 0, x16, 14*FLEN/8, x20, x1, x11,FLREG)
inst_15:// rs1==f31, rd==x12,fs1 == 0 and fe1 == 0x3fc and fm1 == 0x08574923b869b and fcsr == 0x0 and rm_val == 7
/* opcode: fcvt.w.d ; op1:f31; dest:x12; op1val:0x3fc08574923b869b; valaddr_reg:x16;
val_offset:15*FLEN/8; rmval:dyn; correctval:??; testreg:x11;
fcsr_val:0*/
TEST_FPID_OP(fcvt.w.d, x12, f31, dyn, 0, 0, x16, 15*FLEN/8, x20, x1, x11,FLREG)
inst_16:// rs1==f17, rd==x7,fs1 == 0 and fe1 == 0x3fc and fm1 == 0x08574923b869b and fcsr == 0x20 and rm_val == 7
/* opcode: fcvt.w.d ; op1:f17; dest:x7; op1val:0x3fc08574923b869b; valaddr_reg:x16;
val_offset:16*FLEN/8; rmval:dyn; correctval:??; testreg:x11;
fcsr_val:32*/
TEST_FPID_OP(fcvt.w.d, x7, f17, dyn, 32, 0, x16, 16*FLEN/8, x20, x1, x11,FLREG)
inst_17:// rs1==f25, rd==x2,fs1 == 0 and fe1 == 0x3fc and fm1 == 0x08574923b869b and fcsr == 0x40 and rm_val == 7
/* opcode: fcvt.w.d ; op1:f25; dest:x2; op1val:0x3fc08574923b869b; valaddr_reg:x16;
val_offset:17*FLEN/8; rmval:dyn; correctval:??; testreg:x11;
fcsr_val:64*/
TEST_FPID_OP(fcvt.w.d, x2, f25, dyn, 64, 0, x16, 17*FLEN/8, x20, x1, x11,FLREG)
inst_18:// rs1==f27, rd==x3,fs1 == 0 and fe1 == 0x3fc and fm1 == 0x08574923b869b and fcsr == 0x60 and rm_val == 7
/* opcode: fcvt.w.d ; op1:f27; dest:x3; op1val:0x3fc08574923b869b; valaddr_reg:x16;
val_offset:18*FLEN/8; rmval:dyn; correctval:??; testreg:x11;
fcsr_val:96*/
TEST_FPID_OP(fcvt.w.d, x3, f27, dyn, 96, 0, x16, 18*FLEN/8, x20, x1, x11,FLREG)
inst_19:// rs1==f16, rd==x19,fs1 == 0 and fe1 == 0x3fc and fm1 == 0x08574923b869b and fcsr == 0x80 and rm_val == 7
/* opcode: fcvt.w.d ; op1:f16; dest:x19; op1val:0x3fc08574923b869b; valaddr_reg:x16;
val_offset:19*FLEN/8; rmval:dyn; correctval:??; testreg:x11;
fcsr_val:128*/
TEST_FPID_OP(fcvt.w.d, x19, f16, dyn, 128, 0, x16, 19*FLEN/8, x20, x1, x11,FLREG)
inst_20:// rs1==f20, rd==x15,fs1 == 0 and fe1 == 0x3fc and fm1 == 0x08574923b869c and fcsr == 0x0 and rm_val == 7
/* opcode: fcvt.w.d ; op1:f20; dest:x15; op1val:0x3fc08574923b869c; valaddr_reg:x16;
val_offset:20*FLEN/8; rmval:dyn; correctval:??; testreg:x11;
fcsr_val:0*/
TEST_FPID_OP(fcvt.w.d, x15, f20, dyn, 0, 0, x16, 20*FLEN/8, x20, x1, x11,FLREG)
inst_21:// rs1==f28, rd==x4,fs1 == 0 and fe1 == 0x3fc and fm1 == 0x08574923b869c and fcsr == 0x20 and rm_val == 7
/* opcode: fcvt.w.d ; op1:f28; dest:x4; op1val:0x3fc08574923b869c; valaddr_reg:x16;
val_offset:21*FLEN/8; rmval:dyn; correctval:??; testreg:x11;
fcsr_val:32*/
TEST_FPID_OP(fcvt.w.d, x4, f28, dyn, 32, 0, x16, 21*FLEN/8, x20, x1, x11,FLREG)
inst_22:// rs1==f11, rd==x13,fs1 == 0 and fe1 == 0x3fc and fm1 == 0x08574923b869c and fcsr == 0x40 and rm_val == 7
/* opcode: fcvt.w.d ; op1:f11; dest:x13; op1val:0x3fc08574923b869c; valaddr_reg:x16;
val_offset:22*FLEN/8; rmval:dyn; correctval:??; testreg:x11;
fcsr_val:64*/
TEST_FPID_OP(fcvt.w.d, x13, f11, dyn, 64, 0, x16, 22*FLEN/8, x20, x1, x11,FLREG)
inst_23:// rs1==f10, rd==x30,fs1 == 0 and fe1 == 0x3fc and fm1 == 0x08574923b869c and fcsr == 0x60 and rm_val == 7
/* opcode: fcvt.w.d ; op1:f10; dest:x30; op1val:0x3fc08574923b869c; valaddr_reg:x16;
val_offset:23*FLEN/8; rmval:dyn; correctval:??; testreg:x11;
fcsr_val:96*/
TEST_FPID_OP(fcvt.w.d, x30, f10, dyn, 96, 0, x16, 23*FLEN/8, x20, x1, x11,FLREG)
RVTEST_VALBASEUPD(x4,test_dataset_1)
inst_24:// rs1==f13, rd==x24,fs1 == 0 and fe1 == 0x3fc and fm1 == 0x08574923b869c and fcsr == 0x80 and rm_val == 7
/* opcode: fcvt.w.d ; op1:f13; dest:x24; op1val:0x3fc08574923b869c; valaddr_reg:x4;
val_offset:0*FLEN/8; rmval:dyn; correctval:??; testreg:x11;
fcsr_val:128*/
TEST_FPID_OP(fcvt.w.d, x24, f13, dyn, 128, 0, x4, 0*FLEN/8, x5, x1, x11,FLREG)
inst_25:// rs1==f5, rd==x0,fs1 == 0 and fe1 == 0x3fc and fm1 == 0x08574923b869d and fcsr == 0x0 and rm_val == 7
/* opcode: fcvt.w.d ; op1:f5; dest:x0; op1val:0x3fc08574923b869d; valaddr_reg:x4;
val_offset:1*FLEN/8; rmval:dyn; correctval:??; testreg:x11;
fcsr_val:0*/
TEST_FPID_OP(fcvt.w.d, x0, f5, dyn, 0, 0, x4, 1*FLEN/8, x5, x1, x11,FLREG)
inst_26:// rs1==f7, rd==x25,fs1 == 0 and fe1 == 0x3fc and fm1 == 0x08574923b869d and fcsr == 0x20 and rm_val == 7
/* opcode: fcvt.w.d ; op1:f7; dest:x25; op1val:0x3fc08574923b869d; valaddr_reg:x4;
val_offset:2*FLEN/8; rmval:dyn; correctval:??; testreg:x11;
fcsr_val:32*/
TEST_FPID_OP(fcvt.w.d, x25, f7, dyn, 32, 0, x4, 2*FLEN/8, x5, x1, x11,FLREG)
inst_27:// rs1==f23, rd==x11,fs1 == 0 and fe1 == 0x3fc and fm1 == 0x08574923b869d and fcsr == 0x40 and rm_val == 7
/* opcode: fcvt.w.d ; op1:f23; dest:x11; op1val:0x3fc08574923b869d; valaddr_reg:x4;
val_offset:3*FLEN/8; rmval:dyn; correctval:??; testreg:x3;
fcsr_val:64*/
TEST_FPID_OP(fcvt.w.d, x11, f23, dyn, 64, 0, x4, 3*FLEN/8, x5, x1, x3,FLREG)
RVTEST_SIGBASE(x2,signature_x2_0)
inst_28:// rs1==f29, rd==x16,fs1 == 0 and fe1 == 0x3fc and fm1 == 0x08574923b869d and fcsr == 0x60 and rm_val == 7
/* opcode: fcvt.w.d ; op1:f29; dest:x16; op1val:0x3fc08574923b869d; valaddr_reg:x4;
val_offset:4*FLEN/8; rmval:dyn; correctval:??; testreg:x3;
fcsr_val:96*/
TEST_FPID_OP(fcvt.w.d, x16, f29, dyn, 96, 0, x4, 4*FLEN/8, x5, x2, x3,FLREG)
inst_29:// rs1==f30, rd==x28,fs1 == 0 and fe1 == 0x3fc and fm1 == 0x08574923b869d and fcsr == 0x80 and rm_val == 7
/* opcode: fcvt.w.d ; op1:f30; dest:x28; op1val:0x3fc08574923b869d; valaddr_reg:x4;
val_offset:5*FLEN/8; rmval:dyn; correctval:??; testreg:x3;
fcsr_val:128*/
TEST_FPID_OP(fcvt.w.d, x28, f30, dyn, 128, 0, x4, 5*FLEN/8, x5, x2, x3,FLREG)
inst_30:// rs1==f12, rd==x20,fs1 == 0 and fe1 == 0x3fc and fm1 == 0x08574923b869e and fcsr == 0x0 and rm_val == 7
/* opcode: fcvt.w.d ; op1:f12; dest:x20; op1val:0x3fc08574923b869e; valaddr_reg:x4;
val_offset:6*FLEN/8; rmval:dyn; correctval:??; testreg:x3;
fcsr_val:0*/
TEST_FPID_OP(fcvt.w.d, x20, f12, dyn, 0, 0, x4, 6*FLEN/8, x5, x2, x3,FLREG)
inst_31:// rs1==f21, rd==x1,fs1 == 0 and fe1 == 0x3fc and fm1 == 0x08574923b869e and fcsr == 0x20 and rm_val == 7
/* opcode: fcvt.w.d ; op1:f21; dest:x1; op1val:0x3fc08574923b869e; valaddr_reg:x4;
val_offset:7*FLEN/8; rmval:dyn; correctval:??; testreg:x3;
fcsr_val:32*/
TEST_FPID_OP(fcvt.w.d, x1, f21, dyn, 32, 0, x4, 7*FLEN/8, x5, x2, x3,FLREG)
inst_32:// fs1 == 0 and fe1 == 0x3fc and fm1 == 0x08574923b869e and fcsr == 0x40 and rm_val == 7
/* opcode: fcvt.w.d ; op1:f31; dest:x31; op1val:0x3fc08574923b869e; valaddr_reg:x4;
val_offset:8*FLEN/8; rmval:dyn; correctval:??; testreg:x3;
fcsr_val:64*/
TEST_FPID_OP(fcvt.w.d, x31, f31, dyn, 64, 0, x4, 8*FLEN/8, x5, x2, x3,FLREG)
inst_33:// fs1 == 0 and fe1 == 0x3fc and fm1 == 0x08574923b869e and fcsr == 0x60 and rm_val == 7
/* opcode: fcvt.w.d ; op1:f31; dest:x31; op1val:0x3fc08574923b869e; valaddr_reg:x4;
val_offset:9*FLEN/8; rmval:dyn; correctval:??; testreg:x3;
fcsr_val:96*/
TEST_FPID_OP(fcvt.w.d, x31, f31, dyn, 96, 0, x4, 9*FLEN/8, x5, x2, x3,FLREG)
inst_34:// fs1 == 0 and fe1 == 0x3fc and fm1 == 0x08574923b869e and fcsr == 0x80 and rm_val == 7
/* opcode: fcvt.w.d ; op1:f31; dest:x31; op1val:0x3fc08574923b869e; valaddr_reg:x4;
val_offset:10*FLEN/8; rmval:dyn; correctval:??; testreg:x3;
fcsr_val:128*/
TEST_FPID_OP(fcvt.w.d, x31, f31, dyn, 128, 0, x4, 10*FLEN/8, x5, x2, x3,FLREG)
inst_35:// fs1 == 0 and fe1 == 0x3fc and fm1 == 0x08574923b869f and fcsr == 0x0 and rm_val == 7
/* opcode: fcvt.w.d ; op1:f31; dest:x31; op1val:0x3fc08574923b869f; valaddr_reg:x4;
val_offset:11*FLEN/8; rmval:dyn; correctval:??; testreg:x3;
fcsr_val:0*/
TEST_FPID_OP(fcvt.w.d, x31, f31, dyn, 0, 0, x4, 11*FLEN/8, x5, x2, x3,FLREG)
inst_36:// fs1 == 0 and fe1 == 0x3fc and fm1 == 0x08574923b869f and fcsr == 0x20 and rm_val == 7
/* opcode: fcvt.w.d ; op1:f31; dest:x31; op1val:0x3fc08574923b869f; valaddr_reg:x4;
val_offset:12*FLEN/8; rmval:dyn; correctval:??; testreg:x3;
fcsr_val:32*/
TEST_FPID_OP(fcvt.w.d, x31, f31, dyn, 32, 0, x4, 12*FLEN/8, x5, x2, x3,FLREG)
inst_37:// fs1 == 0 and fe1 == 0x3fc and fm1 == 0x08574923b869f and fcsr == 0x40 and rm_val == 7
/* opcode: fcvt.w.d ; op1:f31; dest:x31; op1val:0x3fc08574923b869f; valaddr_reg:x4;
val_offset:13*FLEN/8; rmval:dyn; correctval:??; testreg:x3;
fcsr_val:64*/
TEST_FPID_OP(fcvt.w.d, x31, f31, dyn, 64, 0, x4, 13*FLEN/8, x5, x2, x3,FLREG)
inst_38:// fs1 == 0 and fe1 == 0x3fc and fm1 == 0x08574923b869f and fcsr == 0x60 and rm_val == 7
/* opcode: fcvt.w.d ; op1:f31; dest:x31; op1val:0x3fc08574923b869f; valaddr_reg:x4;
val_offset:14*FLEN/8; rmval:dyn; correctval:??; testreg:x3;
fcsr_val:96*/
TEST_FPID_OP(fcvt.w.d, x31, f31, dyn, 96, 0, x4, 14*FLEN/8, x5, x2, x3,FLREG)
inst_39:// fs1 == 0 and fe1 == 0x3fc and fm1 == 0x08574923b869f and fcsr == 0x80 and rm_val == 7
/* opcode: fcvt.w.d ; op1:f31; dest:x31; op1val:0x3fc08574923b869f; valaddr_reg:x4;
val_offset:15*FLEN/8; rmval:dyn; correctval:??; testreg:x3;
fcsr_val:128*/
TEST_FPID_OP(fcvt.w.d, x31, f31, dyn, 128, 0, x4, 15*FLEN/8, x5, x2, x3,FLREG)
inst_40:// fs1 == 1 and fe1 == 0x3fc and fm1 == 0x08574923b8698 and fcsr == 0x0 and rm_val == 7
/* opcode: fcvt.w.d ; op1:f31; dest:x31; op1val:0xbfc08574923b8698; valaddr_reg:x4;
val_offset:16*FLEN/8; rmval:dyn; correctval:??; testreg:x3;
fcsr_val:0*/
TEST_FPID_OP(fcvt.w.d, x31, f31, dyn, 0, 0, x4, 16*FLEN/8, x5, x2, x3,FLREG)
inst_41:// fs1 == 1 and fe1 == 0x3fc and fm1 == 0x08574923b8698 and fcsr == 0x20 and rm_val == 7
/* opcode: fcvt.w.d ; op1:f31; dest:x31; op1val:0xbfc08574923b8698; valaddr_reg:x4;
val_offset:17*FLEN/8; rmval:dyn; correctval:??; testreg:x3;
fcsr_val:32*/
TEST_FPID_OP(fcvt.w.d, x31, f31, dyn, 32, 0, x4, 17*FLEN/8, x5, x2, x3,FLREG)
inst_42:// fs1 == 1 and fe1 == 0x3fc and fm1 == 0x08574923b8698 and fcsr == 0x40 and rm_val == 7
/* opcode: fcvt.w.d ; op1:f31; dest:x31; op1val:0xbfc08574923b8698; valaddr_reg:x4;
val_offset:18*FLEN/8; rmval:dyn; correctval:??; testreg:x3;
fcsr_val:64*/
TEST_FPID_OP(fcvt.w.d, x31, f31, dyn, 64, 0, x4, 18*FLEN/8, x5, x2, x3,FLREG)
inst_43:// fs1 == 1 and fe1 == 0x3fc and fm1 == 0x08574923b8698 and fcsr == 0x60 and rm_val == 7
/* opcode: fcvt.w.d ; op1:f31; dest:x31; op1val:0xbfc08574923b8698; valaddr_reg:x4;
val_offset:19*FLEN/8; rmval:dyn; correctval:??; testreg:x3;
fcsr_val:96*/
TEST_FPID_OP(fcvt.w.d, x31, f31, dyn, 96, 0, x4, 19*FLEN/8, x5, x2, x3,FLREG)
inst_44:// fs1 == 1 and fe1 == 0x3fc and fm1 == 0x08574923b8698 and fcsr == 0x80 and rm_val == 7
/* opcode: fcvt.w.d ; op1:f31; dest:x31; op1val:0xbfc08574923b8698; valaddr_reg:x4;
val_offset:20*FLEN/8; rmval:dyn; correctval:??; testreg:x3;
fcsr_val:128*/
TEST_FPID_OP(fcvt.w.d, x31, f31, dyn, 128, 0, x4, 20*FLEN/8, x5, x2, x3,FLREG)
inst_45:// fs1 == 1 and fe1 == 0x3fc and fm1 == 0x08574923b8699 and fcsr == 0x0 and rm_val == 7
/* opcode: fcvt.w.d ; op1:f31; dest:x31; op1val:0xbfc08574923b8699; valaddr_reg:x4;
val_offset:21*FLEN/8; rmval:dyn; correctval:??; testreg:x3;
fcsr_val:0*/
TEST_FPID_OP(fcvt.w.d, x31, f31, dyn, 0, 0, x4, 21*FLEN/8, x5, x2, x3,FLREG)
inst_46:// fs1 == 1 and fe1 == 0x3fc and fm1 == 0x08574923b8699 and fcsr == 0x20 and rm_val == 7
/* opcode: fcvt.w.d ; op1:f31; dest:x31; op1val:0xbfc08574923b8699; valaddr_reg:x4;
val_offset:22*FLEN/8; rmval:dyn; correctval:??; testreg:x3;
fcsr_val:32*/
TEST_FPID_OP(fcvt.w.d, x31, f31, dyn, 32, 0, x4, 22*FLEN/8, x5, x2, x3,FLREG)
inst_47:// fs1 == 1 and fe1 == 0x3fc and fm1 == 0x08574923b8699 and fcsr == 0x40 and rm_val == 7
/* opcode: fcvt.w.d ; op1:f31; dest:x31; op1val:0xbfc08574923b8699; valaddr_reg:x4;
val_offset:23*FLEN/8; rmval:dyn; correctval:??; testreg:x3;
fcsr_val:64*/
TEST_FPID_OP(fcvt.w.d, x31, f31, dyn, 64, 0, x4, 23*FLEN/8, x5, x2, x3,FLREG)
inst_48:// fs1 == 1 and fe1 == 0x3fc and fm1 == 0x08574923b8699 and fcsr == 0x60 and rm_val == 7
/* opcode: fcvt.w.d ; op1:f31; dest:x31; op1val:0xbfc08574923b8699; valaddr_reg:x4;
val_offset:24*FLEN/8; rmval:dyn; correctval:??; testreg:x3;
fcsr_val:96*/
TEST_FPID_OP(fcvt.w.d, x31, f31, dyn, 96, 0, x4, 24*FLEN/8, x5, x2, x3,FLREG)
inst_49:// fs1 == 1 and fe1 == 0x3fc and fm1 == 0x08574923b8699 and fcsr == 0x80 and rm_val == 7
/* opcode: fcvt.w.d ; op1:f31; dest:x31; op1val:0xbfc08574923b8699; valaddr_reg:x4;
val_offset:25*FLEN/8; rmval:dyn; correctval:??; testreg:x3;
fcsr_val:128*/
TEST_FPID_OP(fcvt.w.d, x31, f31, dyn, 128, 0, x4, 25*FLEN/8, x5, x2, x3,FLREG)
inst_50:// fs1 == 1 and fe1 == 0x3fc and fm1 == 0x08574923b869a and fcsr == 0x0 and rm_val == 7
/* opcode: fcvt.w.d ; op1:f31; dest:x31; op1val:0xbfc08574923b869a; valaddr_reg:x4;
val_offset:26*FLEN/8; rmval:dyn; correctval:??; testreg:x3;
fcsr_val:0*/
TEST_FPID_OP(fcvt.w.d, x31, f31, dyn, 0, 0, x4, 26*FLEN/8, x5, x2, x3,FLREG)
inst_51:// fs1 == 1 and fe1 == 0x3fc and fm1 == 0x08574923b869a and fcsr == 0x20 and rm_val == 7
/* opcode: fcvt.w.d ; op1:f31; dest:x31; op1val:0xbfc08574923b869a; valaddr_reg:x4;
val_offset:27*FLEN/8; rmval:dyn; correctval:??; testreg:x3;
fcsr_val:32*/
TEST_FPID_OP(fcvt.w.d, x31, f31, dyn, 32, 0, x4, 27*FLEN/8, x5, x2, x3,FLREG)
inst_52:// fs1 == 1 and fe1 == 0x3fc and fm1 == 0x08574923b869a and fcsr == 0x40 and rm_val == 7
/* opcode: fcvt.w.d ; op1:f31; dest:x31; op1val:0xbfc08574923b869a; valaddr_reg:x4;
val_offset:28*FLEN/8; rmval:dyn; correctval:??; testreg:x3;
fcsr_val:64*/
TEST_FPID_OP(fcvt.w.d, x31, f31, dyn, 64, 0, x4, 28*FLEN/8, x5, x2, x3,FLREG)
inst_53:// fs1 == 1 and fe1 == 0x3fc and fm1 == 0x08574923b869a and fcsr == 0x60 and rm_val == 7
/* opcode: fcvt.w.d ; op1:f31; dest:x31; op1val:0xbfc08574923b869a; valaddr_reg:x4;
val_offset:29*FLEN/8; rmval:dyn; correctval:??; testreg:x3;
fcsr_val:96*/
TEST_FPID_OP(fcvt.w.d, x31, f31, dyn, 96, 0, x4, 29*FLEN/8, x5, x2, x3,FLREG)
inst_54:// fs1 == 1 and fe1 == 0x3fc and fm1 == 0x08574923b869a and fcsr == 0x80 and rm_val == 7
/* opcode: fcvt.w.d ; op1:f31; dest:x31; op1val:0xbfc08574923b869a; valaddr_reg:x4;
val_offset:30*FLEN/8; rmval:dyn; correctval:??; testreg:x3;
fcsr_val:128*/
TEST_FPID_OP(fcvt.w.d, x31, f31, dyn, 128, 0, x4, 30*FLEN/8, x5, x2, x3,FLREG)
inst_55:// fs1 == 1 and fe1 == 0x3fc and fm1 == 0x08574923b869b and fcsr == 0x0 and rm_val == 7
/* opcode: fcvt.w.d ; op1:f31; dest:x31; op1val:0xbfc08574923b869b; valaddr_reg:x4;
val_offset:31*FLEN/8; rmval:dyn; correctval:??; testreg:x3;
fcsr_val:0*/
TEST_FPID_OP(fcvt.w.d, x31, f31, dyn, 0, 0, x4, 31*FLEN/8, x5, x2, x3,FLREG)
inst_56:// fs1 == 1 and fe1 == 0x3fc and fm1 == 0x08574923b869b and fcsr == 0x20 and rm_val == 7
/* opcode: fcvt.w.d ; op1:f31; dest:x31; op1val:0xbfc08574923b869b; valaddr_reg:x4;
val_offset:32*FLEN/8; rmval:dyn; correctval:??; testreg:x3;
fcsr_val:32*/
TEST_FPID_OP(fcvt.w.d, x31, f31, dyn, 32, 0, x4, 32*FLEN/8, x5, x2, x3,FLREG)
inst_57:// fs1 == 1 and fe1 == 0x3fc and fm1 == 0x08574923b869b and fcsr == 0x40 and rm_val == 7
/* opcode: fcvt.w.d ; op1:f31; dest:x31; op1val:0xbfc08574923b869b; valaddr_reg:x4;
val_offset:33*FLEN/8; rmval:dyn; correctval:??; testreg:x3;
fcsr_val:64*/
TEST_FPID_OP(fcvt.w.d, x31, f31, dyn, 64, 0, x4, 33*FLEN/8, x5, x2, x3,FLREG)
inst_58:// fs1 == 1 and fe1 == 0x3fc and fm1 == 0x08574923b869b and fcsr == 0x60 and rm_val == 7
/* opcode: fcvt.w.d ; op1:f31; dest:x31; op1val:0xbfc08574923b869b; valaddr_reg:x4;
val_offset:34*FLEN/8; rmval:dyn; correctval:??; testreg:x3;
fcsr_val:96*/
TEST_FPID_OP(fcvt.w.d, x31, f31, dyn, 96, 0, x4, 34*FLEN/8, x5, x2, x3,FLREG)
inst_59:// fs1 == 1 and fe1 == 0x3fc and fm1 == 0x08574923b869b and fcsr == 0x80 and rm_val == 7
/* opcode: fcvt.w.d ; op1:f31; dest:x31; op1val:0xbfc08574923b869b; valaddr_reg:x4;
val_offset:35*FLEN/8; rmval:dyn; correctval:??; testreg:x3;
fcsr_val:128*/
TEST_FPID_OP(fcvt.w.d, x31, f31, dyn, 128, 0, x4, 35*FLEN/8, x5, x2, x3,FLREG)
inst_60:// fs1 == 1 and fe1 == 0x3fc and fm1 == 0x08574923b869c and fcsr == 0x0 and rm_val == 7
/* opcode: fcvt.w.d ; op1:f31; dest:x31; op1val:0xbfc08574923b869c; valaddr_reg:x4;
val_offset:36*FLEN/8; rmval:dyn; correctval:??; testreg:x3;
fcsr_val:0*/
TEST_FPID_OP(fcvt.w.d, x31, f31, dyn, 0, 0, x4, 36*FLEN/8, x5, x2, x3,FLREG)
inst_61:// fs1 == 1 and fe1 == 0x3fc and fm1 == 0x08574923b869c and fcsr == 0x20 and rm_val == 7
/* opcode: fcvt.w.d ; op1:f31; dest:x31; op1val:0xbfc08574923b869c; valaddr_reg:x4;
val_offset:37*FLEN/8; rmval:dyn; correctval:??; testreg:x3;
fcsr_val:32*/
TEST_FPID_OP(fcvt.w.d, x31, f31, dyn, 32, 0, x4, 37*FLEN/8, x5, x2, x3,FLREG)
inst_62:// fs1 == 1 and fe1 == 0x3fc and fm1 == 0x08574923b869c and fcsr == 0x40 and rm_val == 7
/* opcode: fcvt.w.d ; op1:f31; dest:x31; op1val:0xbfc08574923b869c; valaddr_reg:x4;
val_offset:38*FLEN/8; rmval:dyn; correctval:??; testreg:x3;
fcsr_val:64*/
TEST_FPID_OP(fcvt.w.d, x31, f31, dyn, 64, 0, x4, 38*FLEN/8, x5, x2, x3,FLREG)
inst_63:// fs1 == 1 and fe1 == 0x3fc and fm1 == 0x08574923b869c and fcsr == 0x60 and rm_val == 7
/* opcode: fcvt.w.d ; op1:f31; dest:x31; op1val:0xbfc08574923b869c; valaddr_reg:x4;
val_offset:39*FLEN/8; rmval:dyn; correctval:??; testreg:x3;
fcsr_val:96*/
TEST_FPID_OP(fcvt.w.d, x31, f31, dyn, 96, 0, x4, 39*FLEN/8, x5, x2, x3,FLREG)
inst_64:// fs1 == 1 and fe1 == 0x3fc and fm1 == 0x08574923b869c and fcsr == 0x80 and rm_val == 7
/* opcode: fcvt.w.d ; op1:f31; dest:x31; op1val:0xbfc08574923b869c; valaddr_reg:x4;
val_offset:40*FLEN/8; rmval:dyn; correctval:??; testreg:x3;
fcsr_val:128*/
TEST_FPID_OP(fcvt.w.d, x31, f31, dyn, 128, 0, x4, 40*FLEN/8, x5, x2, x3,FLREG)
inst_65:// fs1 == 1 and fe1 == 0x3fc and fm1 == 0x08574923b869d and fcsr == 0x0 and rm_val == 7
/* opcode: fcvt.w.d ; op1:f31; dest:x31; op1val:0xbfc08574923b869d; valaddr_reg:x4;
val_offset:41*FLEN/8; rmval:dyn; correctval:??; testreg:x3;
fcsr_val:0*/
TEST_FPID_OP(fcvt.w.d, x31, f31, dyn, 0, 0, x4, 41*FLEN/8, x5, x2, x3,FLREG)
inst_66:// fs1 == 1 and fe1 == 0x3fc and fm1 == 0x08574923b869d and fcsr == 0x20 and rm_val == 7
/* opcode: fcvt.w.d ; op1:f31; dest:x31; op1val:0xbfc08574923b869d; valaddr_reg:x4;
val_offset:42*FLEN/8; rmval:dyn; correctval:??; testreg:x3;
fcsr_val:32*/
TEST_FPID_OP(fcvt.w.d, x31, f31, dyn, 32, 0, x4, 42*FLEN/8, x5, x2, x3,FLREG)
inst_67:// fs1 == 1 and fe1 == 0x3fc and fm1 == 0x08574923b869d and fcsr == 0x40 and rm_val == 7
/* opcode: fcvt.w.d ; op1:f31; dest:x31; op1val:0xbfc08574923b869d; valaddr_reg:x4;
val_offset:43*FLEN/8; rmval:dyn; correctval:??; testreg:x3;
fcsr_val:64*/
TEST_FPID_OP(fcvt.w.d, x31, f31, dyn, 64, 0, x4, 43*FLEN/8, x5, x2, x3,FLREG)
inst_68:// fs1 == 1 and fe1 == 0x3fc and fm1 == 0x08574923b869d and fcsr == 0x60 and rm_val == 7
/* opcode: fcvt.w.d ; op1:f31; dest:x31; op1val:0xbfc08574923b869d; valaddr_reg:x4;
val_offset:44*FLEN/8; rmval:dyn; correctval:??; testreg:x3;
fcsr_val:96*/
TEST_FPID_OP(fcvt.w.d, x31, f31, dyn, 96, 0, x4, 44*FLEN/8, x5, x2, x3,FLREG)
inst_69:// fs1 == 1 and fe1 == 0x3fc and fm1 == 0x08574923b869d and fcsr == 0x80 and rm_val == 7
/* opcode: fcvt.w.d ; op1:f31; dest:x31; op1val:0xbfc08574923b869d; valaddr_reg:x4;
val_offset:45*FLEN/8; rmval:dyn; correctval:??; testreg:x3;
fcsr_val:128*/
TEST_FPID_OP(fcvt.w.d, x31, f31, dyn, 128, 0, x4, 45*FLEN/8, x5, x2, x3,FLREG)
inst_70:// fs1 == 1 and fe1 == 0x3fc and fm1 == 0x08574923b869e and fcsr == 0x0 and rm_val == 7
/* opcode: fcvt.w.d ; op1:f31; dest:x31; op1val:0xbfc08574923b869e; valaddr_reg:x4;
val_offset:46*FLEN/8; rmval:dyn; correctval:??; testreg:x3;
fcsr_val:0*/
TEST_FPID_OP(fcvt.w.d, x31, f31, dyn, 0, 0, x4, 46*FLEN/8, x5, x2, x3,FLREG)
inst_71:// fs1 == 1 and fe1 == 0x3fc and fm1 == 0x08574923b869e and fcsr == 0x20 and rm_val == 7
/* opcode: fcvt.w.d ; op1:f31; dest:x31; op1val:0xbfc08574923b869e; valaddr_reg:x4;
val_offset:47*FLEN/8; rmval:dyn; correctval:??; testreg:x3;
fcsr_val:32*/
TEST_FPID_OP(fcvt.w.d, x31, f31, dyn, 32, 0, x4, 47*FLEN/8, x5, x2, x3,FLREG)
inst_72:// fs1 == 1 and fe1 == 0x3fc and fm1 == 0x08574923b869e and fcsr == 0x40 and rm_val == 7
/* opcode: fcvt.w.d ; op1:f31; dest:x31; op1val:0xbfc08574923b869e; valaddr_reg:x4;
val_offset:48*FLEN/8; rmval:dyn; correctval:??; testreg:x3;
fcsr_val:64*/
TEST_FPID_OP(fcvt.w.d, x31, f31, dyn, 64, 0, x4, 48*FLEN/8, x5, x2, x3,FLREG)
inst_73:// fs1 == 1 and fe1 == 0x3fc and fm1 == 0x08574923b869e and fcsr == 0x60 and rm_val == 7
/* opcode: fcvt.w.d ; op1:f31; dest:x31; op1val:0xbfc08574923b869e; valaddr_reg:x4;
val_offset:49*FLEN/8; rmval:dyn; correctval:??; testreg:x3;
fcsr_val:96*/
TEST_FPID_OP(fcvt.w.d, x31, f31, dyn, 96, 0, x4, 49*FLEN/8, x5, x2, x3,FLREG)
inst_74:// fs1 == 1 and fe1 == 0x3fc and fm1 == 0x08574923b869e and fcsr == 0x80 and rm_val == 7
/* opcode: fcvt.w.d ; op1:f31; dest:x31; op1val:0xbfc08574923b869e; valaddr_reg:x4;
val_offset:50*FLEN/8; rmval:dyn; correctval:??; testreg:x3;
fcsr_val:128*/
TEST_FPID_OP(fcvt.w.d, x31, f31, dyn, 128, 0, x4, 50*FLEN/8, x5, x2, x3,FLREG)
inst_75:// fs1 == 1 and fe1 == 0x3fc and fm1 == 0x08574923b869f and fcsr == 0x0 and rm_val == 7
/* opcode: fcvt.w.d ; op1:f31; dest:x31; op1val:0xbfc08574923b869f; valaddr_reg:x4;
val_offset:51*FLEN/8; rmval:dyn; correctval:??; testreg:x3;
fcsr_val:0*/
TEST_FPID_OP(fcvt.w.d, x31, f31, dyn, 0, 0, x4, 51*FLEN/8, x5, x2, x3,FLREG)
inst_76:// fs1 == 1 and fe1 == 0x3fc and fm1 == 0x08574923b869f and fcsr == 0x20 and rm_val == 7
/* opcode: fcvt.w.d ; op1:f31; dest:x31; op1val:0xbfc08574923b869f; valaddr_reg:x4;
val_offset:52*FLEN/8; rmval:dyn; correctval:??; testreg:x3;
fcsr_val:32*/
TEST_FPID_OP(fcvt.w.d, x31, f31, dyn, 32, 0, x4, 52*FLEN/8, x5, x2, x3,FLREG)
inst_77:// fs1 == 1 and fe1 == 0x3fc and fm1 == 0x08574923b869f and fcsr == 0x40 and rm_val == 7
/* opcode: fcvt.w.d ; op1:f31; dest:x31; op1val:0xbfc08574923b869f; valaddr_reg:x4;
val_offset:53*FLEN/8; rmval:dyn; correctval:??; testreg:x3;
fcsr_val:64*/
TEST_FPID_OP(fcvt.w.d, x31, f31, dyn, 64, 0, x4, 53*FLEN/8, x5, x2, x3,FLREG)
inst_78:// fs1 == 1 and fe1 == 0x3fc and fm1 == 0x08574923b869f and fcsr == 0x60 and rm_val == 7
/* opcode: fcvt.w.d ; op1:f31; dest:x31; op1val:0xbfc08574923b869f; valaddr_reg:x4;
val_offset:54*FLEN/8; rmval:dyn; correctval:??; testreg:x3;
fcsr_val:96*/
TEST_FPID_OP(fcvt.w.d, x31, f31, dyn, 96, 0, x4, 54*FLEN/8, x5, x2, x3,FLREG)
inst_79:// fs1 == 1 and fe1 == 0x3fc and fm1 == 0x08574923b869f and fcsr == 0x80 and rm_val == 7
/* opcode: fcvt.w.d ; op1:f31; dest:x31; op1val:0xbfc08574923b869f; valaddr_reg:x4;
val_offset:55*FLEN/8; rmval:dyn; correctval:??; testreg:x3;
fcsr_val:128*/
TEST_FPID_OP(fcvt.w.d, x31, f31, dyn, 128, 0, x4, 55*FLEN/8, x5, x2, x3,FLREG)
inst_80:// fs1 == 0 and fe1 == 0x3fc and fm1 == 0x08574923b869d and fcsr == 0x0 and rm_val == 7
/* opcode: fcvt.w.d ; op1:f31; dest:x31; op1val:0x3fc08574923b869d; valaddr_reg:x4;
val_offset:56*FLEN/8; rmval:dyn; correctval:??; testreg:x3;
fcsr_val:0*/
TEST_FPID_OP(fcvt.w.d, x31, f31, dyn, 0, 0, x4, 56*FLEN/8, x5, x2, x3,FLREG)
#endif
RVTEST_CODE_END
RVMODEL_HALT
RVTEST_DATA_BEGIN
.align 4
rvtest_data:
.word 0xbabecafe
.word 0xabecafeb
.word 0xbecafeba
.word 0xecafebab
test_dataset_0:
NAN_BOXED(4593818355633981080,64,FLEN)
NAN_BOXED(4593818355633981080,64,FLEN)
NAN_BOXED(4593818355633981080,64,FLEN)
NAN_BOXED(4593818355633981080,64,FLEN)
NAN_BOXED(4593818355633981080,64,FLEN)
NAN_BOXED(4593818355633981081,64,FLEN)
NAN_BOXED(4593818355633981081,64,FLEN)
NAN_BOXED(4593818355633981081,64,FLEN)
NAN_BOXED(4593818355633981081,64,FLEN)
NAN_BOXED(4593818355633981081,64,FLEN)
NAN_BOXED(4593818355633981082,64,FLEN)
NAN_BOXED(4593818355633981082,64,FLEN)
NAN_BOXED(4593818355633981082,64,FLEN)
NAN_BOXED(4593818355633981082,64,FLEN)
NAN_BOXED(4593818355633981082,64,FLEN)
NAN_BOXED(4593818355633981083,64,FLEN)
NAN_BOXED(4593818355633981083,64,FLEN)
NAN_BOXED(4593818355633981083,64,FLEN)
NAN_BOXED(4593818355633981083,64,FLEN)
NAN_BOXED(4593818355633981083,64,FLEN)
NAN_BOXED(4593818355633981084,64,FLEN)
NAN_BOXED(4593818355633981084,64,FLEN)
NAN_BOXED(4593818355633981084,64,FLEN)
NAN_BOXED(4593818355633981084,64,FLEN)
test_dataset_1:
NAN_BOXED(4593818355633981084,64,FLEN)
NAN_BOXED(4593818355633981085,64,FLEN)
NAN_BOXED(4593818355633981085,64,FLEN)
NAN_BOXED(4593818355633981085,64,FLEN)
NAN_BOXED(4593818355633981085,64,FLEN)
NAN_BOXED(4593818355633981085,64,FLEN)
NAN_BOXED(4593818355633981086,64,FLEN)
NAN_BOXED(4593818355633981086,64,FLEN)
NAN_BOXED(4593818355633981086,64,FLEN)
NAN_BOXED(4593818355633981086,64,FLEN)
NAN_BOXED(4593818355633981086,64,FLEN)
NAN_BOXED(4593818355633981087,64,FLEN)
NAN_BOXED(4593818355633981087,64,FLEN)
NAN_BOXED(4593818355633981087,64,FLEN)
NAN_BOXED(4593818355633981087,64,FLEN)
NAN_BOXED(4593818355633981087,64,FLEN)
NAN_BOXED(13817190392488756888,64,FLEN)
NAN_BOXED(13817190392488756888,64,FLEN)
NAN_BOXED(13817190392488756888,64,FLEN)
NAN_BOXED(13817190392488756888,64,FLEN)
NAN_BOXED(13817190392488756888,64,FLEN)
NAN_BOXED(13817190392488756889,64,FLEN)
NAN_BOXED(13817190392488756889,64,FLEN)
NAN_BOXED(13817190392488756889,64,FLEN)
NAN_BOXED(13817190392488756889,64,FLEN)
NAN_BOXED(13817190392488756889,64,FLEN)
NAN_BOXED(13817190392488756890,64,FLEN)
NAN_BOXED(13817190392488756890,64,FLEN)
NAN_BOXED(13817190392488756890,64,FLEN)
NAN_BOXED(13817190392488756890,64,FLEN)
NAN_BOXED(13817190392488756890,64,FLEN)
NAN_BOXED(13817190392488756891,64,FLEN)
NAN_BOXED(13817190392488756891,64,FLEN)
NAN_BOXED(13817190392488756891,64,FLEN)
NAN_BOXED(13817190392488756891,64,FLEN)
NAN_BOXED(13817190392488756891,64,FLEN)
NAN_BOXED(13817190392488756892,64,FLEN)
NAN_BOXED(13817190392488756892,64,FLEN)
NAN_BOXED(13817190392488756892,64,FLEN)
NAN_BOXED(13817190392488756892,64,FLEN)
NAN_BOXED(13817190392488756892,64,FLEN)
NAN_BOXED(13817190392488756893,64,FLEN)
NAN_BOXED(13817190392488756893,64,FLEN)
NAN_BOXED(13817190392488756893,64,FLEN)
NAN_BOXED(13817190392488756893,64,FLEN)
NAN_BOXED(13817190392488756893,64,FLEN)
NAN_BOXED(13817190392488756894,64,FLEN)
NAN_BOXED(13817190392488756894,64,FLEN)
NAN_BOXED(13817190392488756894,64,FLEN)
NAN_BOXED(13817190392488756894,64,FLEN)
NAN_BOXED(13817190392488756894,64,FLEN)
NAN_BOXED(13817190392488756895,64,FLEN)
NAN_BOXED(13817190392488756895,64,FLEN)
NAN_BOXED(13817190392488756895,64,FLEN)
NAN_BOXED(13817190392488756895,64,FLEN)
NAN_BOXED(13817190392488756895,64,FLEN)
NAN_BOXED(4593818355633981085,64,FLEN)
RVTEST_DATA_END
RVMODEL_DATA_BEGIN
rvtest_sig_begin:
sig_begin_canary:
CANARY;
signature_x1_0:
.fill 0*((SIGALIGN)/4),4,0xdeadbeef
signature_x1_1:
.fill 56*((SIGALIGN)/4),4,0xdeadbeef
signature_x2_0:
.fill 106*((SIGALIGN)/4),4,0xdeadbeef
#ifdef rvtest_mtrap_routine
tsig_begin_canary:
CANARY;
tsig_begin_canary:
CANARY;
mtrap_sigptr:
.fill 64*(XLEN/32),4,0xdeadbeef
tsig_end_canary:
CANARY;
tsig_end_canary:
CANARY;
#endif
#ifdef rvtest_gpr_save
gpr_save:
.fill 32*XLEN/32,4,0xdeadbeef
#endif
sig_end_canary:
CANARY;
rvtest_sig_end:
RVMODEL_DATA_END

330
vendor/riscv-arch-tests/riscv-test-suite/rv32i_m/D/src/fcvt.wu.d_b1-01.S vendored
View file

@ -1,330 +0,0 @@
// -----------
// This file was generated by riscv_ctg (https://github.com/riscv-software-src/riscv-ctg)
// version : 0.7.1
// timestamp : Fri Jun 17 14:03:51 2022 GMT
// usage : riscv_ctg \
// -- cgf // --cgf /scratch/pawan/work/normalised/RV32D/fcvt.wu.d.cgf \
\
// -- xlen 32 \
// --randomize \
// -----------
//
// -----------
// Copyright (c) 2020. RISC-V International. All rights reserved.
// SPDX-License-Identifier: BSD-3-Clause
// -----------
//
// This assembly file tests the fcvt.wu.d instruction of the RISC-V RV32FD_Zicsr,RV64FD_Zicsr extension for the fcvt.wu.d_b1 covergroup.
//
#include "model_test.h"
#include "arch_test.h"
RVTEST_ISA("RV32IFD_Zicsr,RV64IFD_Zicsr")
.section .text.init
.org 0x80
.globl rvtest_entry_point
rvtest_entry_point:
RVMODEL_BOOT
RVTEST_CODE_BEGIN
#ifdef TEST_CASE_1
RVTEST_CASE(0,"//check ISA:=regex(.*I.*D.*);def TEST_CASE_1=True;",fcvt.wu.d_b1)
RVTEST_FP_ENABLE()
RVTEST_VALBASEUPD(x9,test_dataset_0)
RVTEST_SIGBASE(x5,signature_x5_1)
inst_0:// rs1==f19, rd==x15,fs1 == 0 and fe1 == 0x000 and fm1 == 0x0000000000000 and fcsr == 0x0 and rm_val == 7
/* opcode: fcvt.wu.d ; op1:f19; dest:x15; op1val:0x0; valaddr_reg:x9;
val_offset:0*FLEN/8; rmval:dyn; correctval:??; testreg:x6;
fcsr_val:0*/
TEST_FPID_OP(fcvt.wu.d, x15, f19, dyn, 0, 0, x9, 0*FLEN/8, x16, x5, x6,FLREG)
inst_1:// rs1==f14, rd==x22,fs1 == 0 and fe1 == 0x000 and fm1 == 0x0000000000001 and fcsr == 0x0 and rm_val == 7
/* opcode: fcvt.wu.d ; op1:f14; dest:x22; op1val:0x1; valaddr_reg:x9;
val_offset:1*FLEN/8; rmval:dyn; correctval:??; testreg:x6;
fcsr_val:0*/
TEST_FPID_OP(fcvt.wu.d, x22, f14, dyn, 0, 0, x9, 1*FLEN/8, x16, x5, x6,FLREG)
inst_2:// rs1==f22, rd==x0,fs1 == 0 and fe1 == 0x000 and fm1 == 0x0000000000002 and fcsr == 0x0 and rm_val == 7
/* opcode: fcvt.wu.d ; op1:f22; dest:x0; op1val:0x2; valaddr_reg:x9;
val_offset:2*FLEN/8; rmval:dyn; correctval:??; testreg:x6;
fcsr_val:0*/
TEST_FPID_OP(fcvt.wu.d, x0, f22, dyn, 0, 0, x9, 2*FLEN/8, x16, x5, x6,FLREG)
inst_3:// rs1==f30, rd==x12,fs1 == 0 and fe1 == 0x000 and fm1 == 0xfffffffffffff and fcsr == 0x0 and rm_val == 7
/* opcode: fcvt.wu.d ; op1:f30; dest:x12; op1val:0xfffffffffffff; valaddr_reg:x9;
val_offset:3*FLEN/8; rmval:dyn; correctval:??; testreg:x6;
fcsr_val:0*/
TEST_FPID_OP(fcvt.wu.d, x12, f30, dyn, 0, 0, x9, 3*FLEN/8, x16, x5, x6,FLREG)
inst_4:// rs1==f27, rd==x18,fs1 == 0 and fe1 == 0x001 and fm1 == 0x0000000000000 and fcsr == 0x0 and rm_val == 7
/* opcode: fcvt.wu.d ; op1:f27; dest:x18; op1val:0x10000000000000; valaddr_reg:x9;
val_offset:4*FLEN/8; rmval:dyn; correctval:??; testreg:x6;
fcsr_val:0*/
TEST_FPID_OP(fcvt.wu.d, x18, f27, dyn, 0, 0, x9, 4*FLEN/8, x16, x5, x6,FLREG)
inst_5:// rs1==f8, rd==x21,fs1 == 0 and fe1 == 0x001 and fm1 == 0x0000000000002 and fcsr == 0x0 and rm_val == 7
/* opcode: fcvt.wu.d ; op1:f8; dest:x21; op1val:0x10000000000002; valaddr_reg:x9;
val_offset:5*FLEN/8; rmval:dyn; correctval:??; testreg:x6;
fcsr_val:0*/
TEST_FPID_OP(fcvt.wu.d, x21, f8, dyn, 0, 0, x9, 5*FLEN/8, x16, x5, x6,FLREG)
inst_6:// rs1==f13, rd==x14,fs1 == 0 and fe1 == 0x3ff and fm1 == 0x0000000000000 and fcsr == 0x0 and rm_val == 7
/* opcode: fcvt.wu.d ; op1:f13; dest:x14; op1val:0x3ff0000000000000; valaddr_reg:x9;
val_offset:6*FLEN/8; rmval:dyn; correctval:??; testreg:x6;
fcsr_val:0*/
TEST_FPID_OP(fcvt.wu.d, x14, f13, dyn, 0, 0, x9, 6*FLEN/8, x16, x5, x6,FLREG)
inst_7:// rs1==f29, rd==x26,fs1 == 0 and fe1 == 0x7fe and fm1 == 0xfffffffffffff and fcsr == 0x0 and rm_val == 7
/* opcode: fcvt.wu.d ; op1:f29; dest:x26; op1val:0x7fefffffffffffff; valaddr_reg:x9;
val_offset:7*FLEN/8; rmval:dyn; correctval:??; testreg:x6;
fcsr_val:0*/
TEST_FPID_OP(fcvt.wu.d, x26, f29, dyn, 0, 0, x9, 7*FLEN/8, x16, x5, x6,FLREG)
inst_8:// rs1==f20, rd==x10,fs1 == 0 and fe1 == 0x7ff and fm1 == 0x0000000000000 and fcsr == 0x0 and rm_val == 7
/* opcode: fcvt.wu.d ; op1:f20; dest:x10; op1val:0x7ff0000000000000; valaddr_reg:x9;
val_offset:8*FLEN/8; rmval:dyn; correctval:??; testreg:x6;
fcsr_val:0*/
TEST_FPID_OP(fcvt.wu.d, x10, f20, dyn, 0, 0, x9, 8*FLEN/8, x16, x5, x6,FLREG)
inst_9:// rs1==f10, rd==x25,fs1 == 0 and fe1 == 0x7ff and fm1 == 0x0000000000001 and fcsr == 0x0 and rm_val == 7
/* opcode: fcvt.wu.d ; op1:f10; dest:x25; op1val:0x7ff0000000000001; valaddr_reg:x9;
val_offset:9*FLEN/8; rmval:dyn; correctval:??; testreg:x6;
fcsr_val:0*/
TEST_FPID_OP(fcvt.wu.d, x25, f10, dyn, 0, 0, x9, 9*FLEN/8, x16, x5, x6,FLREG)
inst_10:// rs1==f5, rd==x8,fs1 == 0 and fe1 == 0x7ff and fm1 == 0x8000000000000 and fcsr == 0x0 and rm_val == 7
/* opcode: fcvt.wu.d ; op1:f5; dest:x8; op1val:0x7ff8000000000000; valaddr_reg:x9;
val_offset:10*FLEN/8; rmval:dyn; correctval:??; testreg:x6;
fcsr_val:0*/
TEST_FPID_OP(fcvt.wu.d, x8, f5, dyn, 0, 0, x9, 10*FLEN/8, x16, x5, x6,FLREG)
inst_11:// rs1==f11, rd==x1,fs1 == 0 and fe1 == 0x7ff and fm1 == 0x8000000000001 and fcsr == 0x0 and rm_val == 7
/* opcode: fcvt.wu.d ; op1:f11; dest:x1; op1val:0x7ff8000000000001; valaddr_reg:x9;
val_offset:11*FLEN/8; rmval:dyn; correctval:??; testreg:x6;
fcsr_val:0*/
TEST_FPID_OP(fcvt.wu.d, x1, f11, dyn, 0, 0, x9, 11*FLEN/8, x16, x5, x6,FLREG)
inst_12:// rs1==f28, rd==x3,fs1 == 1 and fe1 == 0x000 and fm1 == 0x0000000000000 and fcsr == 0x0 and rm_val == 7
/* opcode: fcvt.wu.d ; op1:f28; dest:x3; op1val:0x8000000000000000; valaddr_reg:x9;
val_offset:12*FLEN/8; rmval:dyn; correctval:??; testreg:x6;
fcsr_val:0*/
TEST_FPID_OP(fcvt.wu.d, x3, f28, dyn, 0, 0, x9, 12*FLEN/8, x16, x5, x6,FLREG)
inst_13:// rs1==f18, rd==x24,fs1 == 1 and fe1 == 0x000 and fm1 == 0x0000000000001 and fcsr == 0x0 and rm_val == 7
/* opcode: fcvt.wu.d ; op1:f18; dest:x24; op1val:0x8000000000000001; valaddr_reg:x9;
val_offset:13*FLEN/8; rmval:dyn; correctval:??; testreg:x6;
fcsr_val:0*/
TEST_FPID_OP(fcvt.wu.d, x24, f18, dyn, 0, 0, x9, 13*FLEN/8, x16, x5, x6,FLREG)
inst_14:// rs1==f7, rd==x31,fs1 == 1 and fe1 == 0x000 and fm1 == 0x0000000000002 and fcsr == 0x0 and rm_val == 7
/* opcode: fcvt.wu.d ; op1:f7; dest:x31; op1val:0x8000000000000002; valaddr_reg:x9;
val_offset:14*FLEN/8; rmval:dyn; correctval:??; testreg:x6;
fcsr_val:0*/
TEST_FPID_OP(fcvt.wu.d, x31, f7, dyn, 0, 0, x9, 14*FLEN/8, x16, x5, x6,FLREG)
inst_15:// rs1==f21, rd==x17,fs1 == 1 and fe1 == 0x000 and fm1 == 0xfffffffffffff and fcsr == 0x0 and rm_val == 7
/* opcode: fcvt.wu.d ; op1:f21; dest:x17; op1val:0x800fffffffffffff; valaddr_reg:x9;
val_offset:15*FLEN/8; rmval:dyn; correctval:??; testreg:x6;
fcsr_val:0*/
TEST_FPID_OP(fcvt.wu.d, x17, f21, dyn, 0, 0, x9, 15*FLEN/8, x16, x5, x6,FLREG)
inst_16:// rs1==f26, rd==x30,fs1 == 1 and fe1 == 0x001 and fm1 == 0x0000000000000 and fcsr == 0x0 and rm_val == 7
/* opcode: fcvt.wu.d ; op1:f26; dest:x30; op1val:0x8010000000000000; valaddr_reg:x9;
val_offset:16*FLEN/8; rmval:dyn; correctval:??; testreg:x6;
fcsr_val:0*/
TEST_FPID_OP(fcvt.wu.d, x30, f26, dyn, 0, 0, x9, 16*FLEN/8, x16, x5, x6,FLREG)
inst_17:// rs1==f25, rd==x20,fs1 == 1 and fe1 == 0x001 and fm1 == 0x0000000000002 and fcsr == 0x0 and rm_val == 7
/* opcode: fcvt.wu.d ; op1:f25; dest:x20; op1val:0x8010000000000002; valaddr_reg:x9;
val_offset:17*FLEN/8; rmval:dyn; correctval:??; testreg:x6;
fcsr_val:0*/
TEST_FPID_OP(fcvt.wu.d, x20, f25, dyn, 0, 0, x9, 17*FLEN/8, x16, x5, x6,FLREG)
inst_18:// rs1==f6, rd==x28,fs1 == 1 and fe1 == 0x3f8 and fm1 == 0x0000000000000 and fcsr == 0x0 and rm_val == 7
/* opcode: fcvt.wu.d ; op1:f6; dest:x28; op1val:0xbf80000000000000; valaddr_reg:x9;
val_offset:18*FLEN/8; rmval:dyn; correctval:??; testreg:x6;
fcsr_val:0*/
TEST_FPID_OP(fcvt.wu.d, x28, f6, dyn, 0, 0, x9, 18*FLEN/8, x16, x5, x6,FLREG)
inst_19:// rs1==f4, rd==x7,fs1 == 1 and fe1 == 0x7fe and fm1 == 0xfffffffffffff and fcsr == 0x0 and rm_val == 7
/* opcode: fcvt.wu.d ; op1:f4; dest:x7; op1val:0xffefffffffffffff; valaddr_reg:x9;
val_offset:19*FLEN/8; rmval:dyn; correctval:??; testreg:x6;
fcsr_val:0*/
TEST_FPID_OP(fcvt.wu.d, x7, f4, dyn, 0, 0, x9, 19*FLEN/8, x16, x5, x6,FLREG)
inst_20:// rs1==f23, rd==x2,fs1 == 1 and fe1 == 0x7ff and fm1 == 0x0000000000000 and fcsr == 0x0 and rm_val == 7
/* opcode: fcvt.wu.d ; op1:f23; dest:x2; op1val:0xfff0000000000000; valaddr_reg:x9;
val_offset:20*FLEN/8; rmval:dyn; correctval:??; testreg:x6;
fcsr_val:0*/
TEST_FPID_OP(fcvt.wu.d, x2, f23, dyn, 0, 0, x9, 20*FLEN/8, x16, x5, x6,FLREG)
inst_21:// rs1==f3, rd==x19,fs1 == 1 and fe1 == 0x7ff and fm1 == 0x0000000000001 and fcsr == 0x0 and rm_val == 7
/* opcode: fcvt.wu.d ; op1:f3; dest:x19; op1val:0xfff0000000000001; valaddr_reg:x9;
val_offset:21*FLEN/8; rmval:dyn; correctval:??; testreg:x6;
fcsr_val:0*/
TEST_FPID_OP(fcvt.wu.d, x19, f3, dyn, 0, 0, x9, 21*FLEN/8, x16, x5, x6,FLREG)
inst_22:// rs1==f15, rd==x13,fs1 == 1 and fe1 == 0x7ff and fm1 == 0x8000000000000 and fcsr == 0x0 and rm_val == 7
/* opcode: fcvt.wu.d ; op1:f15; dest:x13; op1val:0xfff8000000000000; valaddr_reg:x9;
val_offset:22*FLEN/8; rmval:dyn; correctval:??; testreg:x6;
fcsr_val:0*/
TEST_FPID_OP(fcvt.wu.d, x13, f15, dyn, 0, 0, x9, 22*FLEN/8, x16, x5, x6,FLREG)
inst_23:// rs1==f12, rd==x4,fs1 == 1 and fe1 == 0x7ff and fm1 == 0x8000000000001 and fcsr == 0x0 and rm_val == 7
/* opcode: fcvt.wu.d ; op1:f12; dest:x4; op1val:0xfff8000000000001; valaddr_reg:x9;
val_offset:23*FLEN/8; rmval:dyn; correctval:??; testreg:x6;
fcsr_val:0*/
TEST_FPID_OP(fcvt.wu.d, x4, f12, dyn, 0, 0, x9, 23*FLEN/8, x16, x5, x6,FLREG)
inst_24:// rs1==f2, rd==x11,
/* opcode: fcvt.wu.d ; op1:f2; dest:x11; op1val:0x0; valaddr_reg:x9;
val_offset:24*FLEN/8; rmval:dyn; correctval:??; testreg:x6;
fcsr_val:0*/
TEST_FPID_OP(fcvt.wu.d, x11, f2, dyn, 0, 0, x9, 24*FLEN/8, x16, x5, x6,FLREG)
RVTEST_VALBASEUPD(x3,test_dataset_1)
inst_25:// rs1==f24, rd==x27,
/* opcode: fcvt.wu.d ; op1:f24; dest:x27; op1val:0x0; valaddr_reg:x3;
val_offset:0*FLEN/8; rmval:dyn; correctval:??; testreg:x6;
fcsr_val:0*/
TEST_FPID_OP(fcvt.wu.d, x27, f24, dyn, 0, 0, x3, 0*FLEN/8, x4, x5, x6,FLREG)
inst_26:// rs1==f17, rd==x16,
/* opcode: fcvt.wu.d ; op1:f17; dest:x16; op1val:0x0; valaddr_reg:x3;
val_offset:1*FLEN/8; rmval:dyn; correctval:??; testreg:x6;
fcsr_val:0*/
TEST_FPID_OP(fcvt.wu.d, x16, f17, dyn, 0, 0, x3, 1*FLEN/8, x4, x5, x6,FLREG)
inst_27:// rs1==f9, rd==x6,
/* opcode: fcvt.wu.d ; op1:f9; dest:x6; op1val:0x0; valaddr_reg:x3;
val_offset:2*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
fcsr_val:0*/
TEST_FPID_OP(fcvt.wu.d, x6, f9, dyn, 0, 0, x3, 2*FLEN/8, x4, x5, x2,FLREG)
RVTEST_SIGBASE(x1,signature_x1_0)
inst_28:// rs1==f31, rd==x23,
/* opcode: fcvt.wu.d ; op1:f31; dest:x23; op1val:0x0; valaddr_reg:x3;
val_offset:3*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
fcsr_val:0*/
TEST_FPID_OP(fcvt.wu.d, x23, f31, dyn, 0, 0, x3, 3*FLEN/8, x4, x1, x2,FLREG)
inst_29:// rs1==f16, rd==x9,
/* opcode: fcvt.wu.d ; op1:f16; dest:x9; op1val:0x0; valaddr_reg:x3;
val_offset:4*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
fcsr_val:0*/
TEST_FPID_OP(fcvt.wu.d, x9, f16, dyn, 0, 0, x3, 4*FLEN/8, x4, x1, x2,FLREG)
inst_30:// rs1==f0, rd==x5,
/* opcode: fcvt.wu.d ; op1:f0; dest:x5; op1val:0x0; valaddr_reg:x3;
val_offset:5*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
fcsr_val:0*/
TEST_FPID_OP(fcvt.wu.d, x5, f0, dyn, 0, 0, x3, 5*FLEN/8, x4, x1, x2,FLREG)
inst_31:// rs1==f1, rd==x29,
/* opcode: fcvt.wu.d ; op1:f1; dest:x29; op1val:0x0; valaddr_reg:x3;
val_offset:6*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
fcsr_val:0*/
TEST_FPID_OP(fcvt.wu.d, x29, f1, dyn, 0, 0, x3, 6*FLEN/8, x4, x1, x2,FLREG)
inst_32:// fs1 == 0 and fe1 == 0x000 and fm1 == 0x0000000000002 and fcsr == 0x0 and rm_val == 7
/* opcode: fcvt.wu.d ; op1:f31; dest:x31; op1val:0x2; valaddr_reg:x3;
val_offset:7*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
fcsr_val:0*/
TEST_FPID_OP(fcvt.wu.d, x31, f31, dyn, 0, 0, x3, 7*FLEN/8, x4, x1, x2,FLREG)
#endif
RVTEST_CODE_END
RVMODEL_HALT
RVTEST_DATA_BEGIN
.align 4
rvtest_data:
.word 0xbabecafe
.word 0xabecafeb
.word 0xbecafeba
.word 0xecafebab
test_dataset_0:
NAN_BOXED(0,64,FLEN)
NAN_BOXED(1,64,FLEN)
NAN_BOXED(2,64,FLEN)
NAN_BOXED(4503599627370495,64,FLEN)
NAN_BOXED(4503599627370496,64,FLEN)
NAN_BOXED(4503599627370498,64,FLEN)
NAN_BOXED(4607182418800017408,64,FLEN)
NAN_BOXED(9218868437227405311,64,FLEN)
NAN_BOXED(9218868437227405312,64,FLEN)
NAN_BOXED(9218868437227405313,64,FLEN)
NAN_BOXED(9221120237041090560,64,FLEN)
NAN_BOXED(9221120237041090561,64,FLEN)
NAN_BOXED(9223372036854775808,64,FLEN)
NAN_BOXED(9223372036854775809,64,FLEN)
NAN_BOXED(9223372036854775810,64,FLEN)
NAN_BOXED(9227875636482146303,64,FLEN)
NAN_BOXED(9227875636482146304,64,FLEN)
NAN_BOXED(9227875636482146306,64,FLEN)
NAN_BOXED(13799029258263199744,64,FLEN)
NAN_BOXED(18442240474082181119,64,FLEN)
NAN_BOXED(18442240474082181120,64,FLEN)
NAN_BOXED(18442240474082181121,64,FLEN)
NAN_BOXED(18444492273895866368,64,FLEN)
NAN_BOXED(18444492273895866369,64,FLEN)
NAN_BOXED(0,64,FLEN)
test_dataset_1:
NAN_BOXED(0,64,FLEN)
NAN_BOXED(0,64,FLEN)
NAN_BOXED(0,64,FLEN)
NAN_BOXED(0,64,FLEN)
NAN_BOXED(0,64,FLEN)
NAN_BOXED(0,64,FLEN)
NAN_BOXED(0,64,FLEN)
NAN_BOXED(2,64,FLEN)
RVTEST_DATA_END
RVMODEL_DATA_BEGIN
rvtest_sig_begin:
sig_begin_canary:
CANARY;
signature_x5_0:
.fill 0*((SIGALIGN)/4),4,0xdeadbeef
signature_x5_1:
.fill 56*((SIGALIGN)/4),4,0xdeadbeef
signature_x1_0:
.fill 10*((SIGALIGN)/4),4,0xdeadbeef
#ifdef rvtest_mtrap_routine
tsig_begin_canary:
CANARY;
tsig_begin_canary:
CANARY;
mtrap_sigptr:
.fill 64*(XLEN/32),4,0xdeadbeef
tsig_end_canary:
CANARY;
tsig_end_canary:
CANARY;
#endif
#ifdef rvtest_gpr_save
gpr_save:
.fill 32*XLEN/32,4,0xdeadbeef
#endif
sig_end_canary:
CANARY;
rvtest_sig_end:
RVMODEL_DATA_END

386
vendor/riscv-arch-tests/riscv-test-suite/rv32i_m/D/src/fcvt.wu.d_b22-01.S vendored
View file

@ -1,386 +0,0 @@
// -----------
// This file was generated by riscv_ctg (https://github.com/riscv-software-src/riscv-ctg)
// version : 0.7.1
// timestamp : Fri Jun 17 14:03:51 2022 GMT
// usage : riscv_ctg \
// -- cgf // --cgf /scratch/pawan/work/normalised/RV32D/fcvt.wu.d.cgf \
\
// -- xlen 32 \
// --randomize \
// -----------
//
// -----------
// Copyright (c) 2020. RISC-V International. All rights reserved.
// SPDX-License-Identifier: BSD-3-Clause
// -----------
//
// This assembly file tests the fcvt.wu.d instruction of the RISC-V RV32FD_Zicsr,RV64FD_Zicsr extension for the fcvt.wu.d_b22 covergroup.
//
#include "model_test.h"
#include "arch_test.h"
RVTEST_ISA("RV32IFD_Zicsr,RV64IFD_Zicsr")
.section .text.init
.org 0x80
.globl rvtest_entry_point
rvtest_entry_point:
RVMODEL_BOOT
RVTEST_CODE_BEGIN
#ifdef TEST_CASE_1
RVTEST_CASE(0,"//check ISA:=regex(.*I.*D.*);def TEST_CASE_1=True;",fcvt.wu.d_b22)
RVTEST_FP_ENABLE()
RVTEST_VALBASEUPD(x19,test_dataset_0)
RVTEST_SIGBASE(x3,signature_x3_1)
inst_0:// rs1==f18, rd==x8,fs1 == 0 and fe1 == 0x3ca and fm1 == 0x30e08ceb506f6 and fcsr == 0x0 and rm_val == 7
/* opcode: fcvt.wu.d ; op1:f18; dest:x8; op1val:0x3ca30e08ceb506f6; valaddr_reg:x19;
val_offset:0*FLEN/8; rmval:dyn; correctval:??; testreg:x6;
fcsr_val:0*/
TEST_FPID_OP(fcvt.wu.d, x8, f18, dyn, 0, 0, x19, 0*FLEN/8, x23, x3, x6,FLREG)
inst_1:// rs1==f3, rd==x30,fs1 == 0 and fe1 == 0x3fc and fm1 == 0x08577924770d3 and fcsr == 0x0 and rm_val == 7
/* opcode: fcvt.wu.d ; op1:f3; dest:x30; op1val:0x3fc08577924770d3; valaddr_reg:x19;
val_offset:1*FLEN/8; rmval:dyn; correctval:??; testreg:x6;
fcsr_val:0*/
TEST_FPID_OP(fcvt.wu.d, x30, f3, dyn, 0, 0, x19, 1*FLEN/8, x23, x3, x6,FLREG)
inst_2:// rs1==f16, rd==x1,fs1 == 0 and fe1 == 0x3fd and fm1 == 0x93fdc7b89296c and fcsr == 0x0 and rm_val == 7
/* opcode: fcvt.wu.d ; op1:f16; dest:x1; op1val:0x3fd93fdc7b89296c; valaddr_reg:x19;
val_offset:2*FLEN/8; rmval:dyn; correctval:??; testreg:x6;
fcsr_val:0*/
TEST_FPID_OP(fcvt.wu.d, x1, f16, dyn, 0, 0, x19, 2*FLEN/8, x23, x3, x6,FLREG)
inst_3:// rs1==f28, rd==x9,fs1 == 0 and fe1 == 0x3ff and fm1 == 0xd2d6b7dc59a3a and fcsr == 0x0 and rm_val == 7
/* opcode: fcvt.wu.d ; op1:f28; dest:x9; op1val:0x3ffd2d6b7dc59a3a; valaddr_reg:x19;
val_offset:3*FLEN/8; rmval:dyn; correctval:??; testreg:x6;
fcsr_val:0*/
TEST_FPID_OP(fcvt.wu.d, x9, f28, dyn, 0, 0, x19, 3*FLEN/8, x23, x3, x6,FLREG)
inst_4:// rs1==f26, rd==x10,fs1 == 0 and fe1 == 0x400 and fm1 == 0xcf84ba749f9c5 and fcsr == 0x0 and rm_val == 7
/* opcode: fcvt.wu.d ; op1:f26; dest:x10; op1val:0x400cf84ba749f9c5; valaddr_reg:x19;
val_offset:4*FLEN/8; rmval:dyn; correctval:??; testreg:x6;
fcsr_val:0*/
TEST_FPID_OP(fcvt.wu.d, x10, f26, dyn, 0, 0, x19, 4*FLEN/8, x23, x3, x6,FLREG)
inst_5:// rs1==f1, rd==x12,fs1 == 0 and fe1 == 0x401 and fm1 == 0x854a908ceac39 and fcsr == 0x0 and rm_val == 7
/* opcode: fcvt.wu.d ; op1:f1; dest:x12; op1val:0x401854a908ceac39; valaddr_reg:x19;
val_offset:5*FLEN/8; rmval:dyn; correctval:??; testreg:x6;
fcsr_val:0*/
TEST_FPID_OP(fcvt.wu.d, x12, f1, dyn, 0, 0, x19, 5*FLEN/8, x23, x3, x6,FLREG)
inst_6:// rs1==f30, rd==x25,fs1 == 0 and fe1 == 0x402 and fm1 == 0x137a953e8eb43 and fcsr == 0x0 and rm_val == 7
/* opcode: fcvt.wu.d ; op1:f30; dest:x25; op1val:0x402137a953e8eb43; valaddr_reg:x19;
val_offset:6*FLEN/8; rmval:dyn; correctval:??; testreg:x6;
fcsr_val:0*/
TEST_FPID_OP(fcvt.wu.d, x25, f30, dyn, 0, 0, x19, 6*FLEN/8, x23, x3, x6,FLREG)
inst_7:// rs1==f22, rd==x5,fs1 == 0 and fe1 == 0x404 and fm1 == 0x5c74eff1e5bef and fcsr == 0x0 and rm_val == 7
/* opcode: fcvt.wu.d ; op1:f22; dest:x5; op1val:0x4045c74eff1e5bef; valaddr_reg:x19;
val_offset:7*FLEN/8; rmval:dyn; correctval:??; testreg:x6;
fcsr_val:0*/
TEST_FPID_OP(fcvt.wu.d, x5, f22, dyn, 0, 0, x19, 7*FLEN/8, x23, x3, x6,FLREG)
inst_8:// rs1==f11, rd==x26,fs1 == 0 and fe1 == 0x405 and fm1 == 0xdc3386b9f15c4 and fcsr == 0x0 and rm_val == 7
/* opcode: fcvt.wu.d ; op1:f11; dest:x26; op1val:0x405dc3386b9f15c4; valaddr_reg:x19;
val_offset:8*FLEN/8; rmval:dyn; correctval:??; testreg:x6;
fcsr_val:0*/
TEST_FPID_OP(fcvt.wu.d, x26, f11, dyn, 0, 0, x19, 8*FLEN/8, x23, x3, x6,FLREG)
inst_9:// rs1==f13, rd==x11,fs1 == 0 and fe1 == 0x406 and fm1 == 0x5ae6a9a6ab329 and fcsr == 0x0 and rm_val == 7
/* opcode: fcvt.wu.d ; op1:f13; dest:x11; op1val:0x4065ae6a9a6ab329; valaddr_reg:x19;
val_offset:9*FLEN/8; rmval:dyn; correctval:??; testreg:x6;
fcsr_val:0*/
TEST_FPID_OP(fcvt.wu.d, x11, f13, dyn, 0, 0, x19, 9*FLEN/8, x23, x3, x6,FLREG)
inst_10:// rs1==f24, rd==x29,fs1 == 0 and fe1 == 0x408 and fm1 == 0x43277acca7f0d and fcsr == 0x0 and rm_val == 7
/* opcode: fcvt.wu.d ; op1:f24; dest:x29; op1val:0x40843277acca7f0d; valaddr_reg:x19;
val_offset:10*FLEN/8; rmval:dyn; correctval:??; testreg:x6;
fcsr_val:0*/
TEST_FPID_OP(fcvt.wu.d, x29, f24, dyn, 0, 0, x19, 10*FLEN/8, x23, x3, x6,FLREG)
inst_11:// rs1==f9, rd==x16,fs1 == 0 and fe1 == 0x409 and fm1 == 0xaf9492cb7362c and fcsr == 0x0 and rm_val == 7
/* opcode: fcvt.wu.d ; op1:f9; dest:x16; op1val:0x409af9492cb7362c; valaddr_reg:x19;
val_offset:11*FLEN/8; rmval:dyn; correctval:??; testreg:x6;
fcsr_val:0*/
TEST_FPID_OP(fcvt.wu.d, x16, f9, dyn, 0, 0, x19, 11*FLEN/8, x23, x3, x6,FLREG)
inst_12:// rs1==f5, rd==x20,fs1 == 0 and fe1 == 0x40a and fm1 == 0x5cd28a96ec2b3 and fcsr == 0x0 and rm_val == 7
/* opcode: fcvt.wu.d ; op1:f5; dest:x20; op1val:0x40a5cd28a96ec2b3; valaddr_reg:x19;
val_offset:12*FLEN/8; rmval:dyn; correctval:??; testreg:x6;
fcsr_val:0*/
TEST_FPID_OP(fcvt.wu.d, x20, f5, dyn, 0, 0, x19, 12*FLEN/8, x23, x3, x6,FLREG)
inst_13:// rs1==f27, rd==x2,fs1 == 0 and fe1 == 0x40d and fm1 == 0x9d02f708cc1b6 and fcsr == 0x0 and rm_val == 7
/* opcode: fcvt.wu.d ; op1:f27; dest:x2; op1val:0x40d9d02f708cc1b6; valaddr_reg:x19;
val_offset:13*FLEN/8; rmval:dyn; correctval:??; testreg:x6;
fcsr_val:0*/
TEST_FPID_OP(fcvt.wu.d, x2, f27, dyn, 0, 0, x19, 13*FLEN/8, x23, x3, x6,FLREG)
inst_14:// rs1==f15, rd==x31,fs1 == 0 and fe1 == 0x40e and fm1 == 0x953b00b54aa22 and fcsr == 0x0 and rm_val == 7
/* opcode: fcvt.wu.d ; op1:f15; dest:x31; op1val:0x40e953b00b54aa22; valaddr_reg:x19;
val_offset:14*FLEN/8; rmval:dyn; correctval:??; testreg:x6;
fcsr_val:0*/
TEST_FPID_OP(fcvt.wu.d, x31, f15, dyn, 0, 0, x19, 14*FLEN/8, x23, x3, x6,FLREG)
inst_15:// rs1==f31, rd==x7,fs1 == 0 and fe1 == 0x40f and fm1 == 0x224c03c53d0e3 and fcsr == 0x0 and rm_val == 7
/* opcode: fcvt.wu.d ; op1:f31; dest:x7; op1val:0x40f224c03c53d0e3; valaddr_reg:x19;
val_offset:15*FLEN/8; rmval:dyn; correctval:??; testreg:x6;
fcsr_val:0*/
TEST_FPID_OP(fcvt.wu.d, x7, f31, dyn, 0, 0, x19, 15*FLEN/8, x23, x3, x6,FLREG)
inst_16:// rs1==f21, rd==x18,fs1 == 0 and fe1 == 0x410 and fm1 == 0xe8dacf0e58650 and fcsr == 0x0 and rm_val == 7
/* opcode: fcvt.wu.d ; op1:f21; dest:x18; op1val:0x410e8dacf0e58650; valaddr_reg:x19;
val_offset:16*FLEN/8; rmval:dyn; correctval:??; testreg:x6;
fcsr_val:0*/
TEST_FPID_OP(fcvt.wu.d, x18, f21, dyn, 0, 0, x19, 16*FLEN/8, x23, x3, x6,FLREG)
inst_17:// rs1==f12, rd==x21,fs1 == 0 and fe1 == 0x412 and fm1 == 0x3d7c9e5f0307e and fcsr == 0x0 and rm_val == 7
/* opcode: fcvt.wu.d ; op1:f12; dest:x21; op1val:0x4123d7c9e5f0307e; valaddr_reg:x19;
val_offset:17*FLEN/8; rmval:dyn; correctval:??; testreg:x6;
fcsr_val:0*/
TEST_FPID_OP(fcvt.wu.d, x21, f12, dyn, 0, 0, x19, 17*FLEN/8, x23, x3, x6,FLREG)
inst_18:// rs1==f23, rd==x13,fs1 == 0 and fe1 == 0x413 and fm1 == 0x8c8a1aaac3142 and fcsr == 0x0 and rm_val == 7
/* opcode: fcvt.wu.d ; op1:f23; dest:x13; op1val:0x4138c8a1aaac3142; valaddr_reg:x19;
val_offset:18*FLEN/8; rmval:dyn; correctval:??; testreg:x6;
fcsr_val:0*/
TEST_FPID_OP(fcvt.wu.d, x13, f23, dyn, 0, 0, x19, 18*FLEN/8, x23, x3, x6,FLREG)
inst_19:// rs1==f0, rd==x17,fs1 == 0 and fe1 == 0x414 and fm1 == 0x785036f9fb997 and fcsr == 0x0 and rm_val == 7
/* opcode: fcvt.wu.d ; op1:f0; dest:x17; op1val:0x414785036f9fb997; valaddr_reg:x19;
val_offset:19*FLEN/8; rmval:dyn; correctval:??; testreg:x6;
fcsr_val:0*/
TEST_FPID_OP(fcvt.wu.d, x17, f0, dyn, 0, 0, x19, 19*FLEN/8, x23, x3, x6,FLREG)
inst_20:// rs1==f2, rd==x22,fs1 == 0 and fe1 == 0x415 and fm1 == 0x95a4da7298c66 and fcsr == 0x0 and rm_val == 7
/* opcode: fcvt.wu.d ; op1:f2; dest:x22; op1val:0x41595a4da7298c66; valaddr_reg:x19;
val_offset:20*FLEN/8; rmval:dyn; correctval:??; testreg:x6;
fcsr_val:0*/
TEST_FPID_OP(fcvt.wu.d, x22, f2, dyn, 0, 0, x19, 20*FLEN/8, x23, x3, x6,FLREG)
inst_21:// rs1==f7, rd==x15,fs1 == 0 and fe1 == 0x416 and fm1 == 0x807dad814d575 and fcsr == 0x0 and rm_val == 7
/* opcode: fcvt.wu.d ; op1:f7; dest:x15; op1val:0x416807dad814d575; valaddr_reg:x19;
val_offset:21*FLEN/8; rmval:dyn; correctval:??; testreg:x6;
fcsr_val:0*/
TEST_FPID_OP(fcvt.wu.d, x15, f7, dyn, 0, 0, x19, 21*FLEN/8, x23, x3, x6,FLREG)
inst_22:// rs1==f20, rd==x14,fs1 == 0 and fe1 == 0x418 and fm1 == 0x3d06169b1dcbf and fcsr == 0x0 and rm_val == 7
/* opcode: fcvt.wu.d ; op1:f20; dest:x14; op1val:0x4183d06169b1dcbf; valaddr_reg:x19;
val_offset:22*FLEN/8; rmval:dyn; correctval:??; testreg:x6;
fcsr_val:0*/
TEST_FPID_OP(fcvt.wu.d, x14, f20, dyn, 0, 0, x19, 22*FLEN/8, x23, x3, x6,FLREG)
inst_23:// rs1==f19, rd==x4,fs1 == 0 and fe1 == 0x419 and fm1 == 0x7f21608208d09 and fcsr == 0x0 and rm_val == 7
/* opcode: fcvt.wu.d ; op1:f19; dest:x4; op1val:0x4197f21608208d09; valaddr_reg:x19;
val_offset:23*FLEN/8; rmval:dyn; correctval:??; testreg:x6;
fcsr_val:0*/
TEST_FPID_OP(fcvt.wu.d, x4, f19, dyn, 0, 0, x19, 23*FLEN/8, x23, x3, x6,FLREG)
RVTEST_VALBASEUPD(x4,test_dataset_1)
inst_24:// rs1==f25, rd==x24,fs1 == 0 and fe1 == 0x41c and fm1 == 0x14b91dae98554 and fcsr == 0x0 and rm_val == 7
/* opcode: fcvt.wu.d ; op1:f25; dest:x24; op1val:0x41c14b91dae98554; valaddr_reg:x4;
val_offset:0*FLEN/8; rmval:dyn; correctval:??; testreg:x6;
fcsr_val:0*/
TEST_FPID_OP(fcvt.wu.d, x24, f25, dyn, 0, 0, x4, 0*FLEN/8, x5, x3, x6,FLREG)
inst_25:// rs1==f10, rd==x19,fs1 == 0 and fe1 == 0x420 and fm1 == 0xc5ec6c6880007 and fcsr == 0x0 and rm_val == 7
/* opcode: fcvt.wu.d ; op1:f10; dest:x19; op1val:0x420c5ec6c6880007; valaddr_reg:x4;
val_offset:1*FLEN/8; rmval:dyn; correctval:??; testreg:x6;
fcsr_val:0*/
TEST_FPID_OP(fcvt.wu.d, x19, f10, dyn, 0, 0, x4, 1*FLEN/8, x5, x3, x6,FLREG)
inst_26:// rs1==f4, rd==x23,fs1 == 0 and fe1 == 0x5ca and fm1 == 0xf871c6ee84270 and fcsr == 0x0 and rm_val == 7
/* opcode: fcvt.wu.d ; op1:f4; dest:x23; op1val:0x5caf871c6ee84270; valaddr_reg:x4;
val_offset:2*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
fcsr_val:0*/
TEST_FPID_OP(fcvt.wu.d, x23, f4, dyn, 0, 0, x4, 2*FLEN/8, x5, x3, x2,FLREG)
RVTEST_SIGBASE(x1,signature_x1_0)
inst_27:// rs1==f17, rd==x6,fs1 == 1 and fe1 == 0x3fe and fm1 == 0x766ba34c2da80 and fcsr == 0x0 and rm_val == 7
/* opcode: fcvt.wu.d ; op1:f17; dest:x6; op1val:0xbfe766ba34c2da80; valaddr_reg:x4;
val_offset:3*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
fcsr_val:0*/
TEST_FPID_OP(fcvt.wu.d, x6, f17, dyn, 0, 0, x4, 3*FLEN/8, x5, x1, x2,FLREG)
inst_28:// rs1==f8, rd==x3,fs1 == 1 and fe1 == 0x403 and fm1 == 0xf3ebcf3d06f86 and fcsr == 0x0 and rm_val == 7
/* opcode: fcvt.wu.d ; op1:f8; dest:x3; op1val:0xc03f3ebcf3d06f86; valaddr_reg:x4;
val_offset:4*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
fcsr_val:0*/
TEST_FPID_OP(fcvt.wu.d, x3, f8, dyn, 0, 0, x4, 4*FLEN/8, x5, x1, x2,FLREG)
inst_29:// rs1==f29, rd==x28,fs1 == 1 and fe1 == 0x407 and fm1 == 0x489b36bd7f503 and fcsr == 0x0 and rm_val == 7
/* opcode: fcvt.wu.d ; op1:f29; dest:x28; op1val:0xc07489b36bd7f503; valaddr_reg:x4;
val_offset:5*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
fcsr_val:0*/
TEST_FPID_OP(fcvt.wu.d, x28, f29, dyn, 0, 0, x4, 5*FLEN/8, x5, x1, x2,FLREG)
inst_30:// rs1==f6, rd==x0,fs1 == 1 and fe1 == 0x40b and fm1 == 0xc491074f942cb and fcsr == 0x0 and rm_val == 7
/* opcode: fcvt.wu.d ; op1:f6; dest:x0; op1val:0xc0bc491074f942cb; valaddr_reg:x4;
val_offset:6*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
fcsr_val:0*/
TEST_FPID_OP(fcvt.wu.d, x0, f6, dyn, 0, 0, x4, 6*FLEN/8, x5, x1, x2,FLREG)
inst_31:// rs1==f14, rd==x27,fs1 == 1 and fe1 == 0x40c and fm1 == 0x3d480fb7f6f5d and fcsr == 0x0 and rm_val == 7
/* opcode: fcvt.wu.d ; op1:f14; dest:x27; op1val:0xc0c3d480fb7f6f5d; valaddr_reg:x4;
val_offset:7*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
fcsr_val:0*/
TEST_FPID_OP(fcvt.wu.d, x27, f14, dyn, 0, 0, x4, 7*FLEN/8, x5, x1, x2,FLREG)
inst_32:// fs1 == 1 and fe1 == 0x411 and fm1 == 0x5dbbb894deab4 and fcsr == 0x0 and rm_val == 7
/* opcode: fcvt.wu.d ; op1:f31; dest:x31; op1val:0xc115dbbb894deab4; valaddr_reg:x4;
val_offset:8*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
fcsr_val:0*/
TEST_FPID_OP(fcvt.wu.d, x31, f31, dyn, 0, 0, x4, 8*FLEN/8, x5, x1, x2,FLREG)
inst_33:// fs1 == 1 and fe1 == 0x417 and fm1 == 0x396bad798c9cf and fcsr == 0x0 and rm_val == 7
/* opcode: fcvt.wu.d ; op1:f31; dest:x31; op1val:0xc17396bad798c9cf; valaddr_reg:x4;
val_offset:9*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
fcsr_val:0*/
TEST_FPID_OP(fcvt.wu.d, x31, f31, dyn, 0, 0, x4, 9*FLEN/8, x5, x1, x2,FLREG)
inst_34:// fs1 == 1 and fe1 == 0x41a and fm1 == 0x9b4f3d167533a and fcsr == 0x0 and rm_val == 7
/* opcode: fcvt.wu.d ; op1:f31; dest:x31; op1val:0xc1a9b4f3d167533a; valaddr_reg:x4;
val_offset:10*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
fcsr_val:0*/
TEST_FPID_OP(fcvt.wu.d, x31, f31, dyn, 0, 0, x4, 10*FLEN/8, x5, x1, x2,FLREG)
inst_35:// fs1 == 1 and fe1 == 0x41b and fm1 == 0x889261270dee2 and fcsr == 0x0 and rm_val == 7
/* opcode: fcvt.wu.d ; op1:f31; dest:x31; op1val:0xc1b889261270dee2; valaddr_reg:x4;
val_offset:11*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
fcsr_val:0*/
TEST_FPID_OP(fcvt.wu.d, x31, f31, dyn, 0, 0, x4, 11*FLEN/8, x5, x1, x2,FLREG)
inst_36:// fs1 == 1 and fe1 == 0x41d and fm1 == 0x9136562694646 and fcsr == 0x0 and rm_val == 7
/* opcode: fcvt.wu.d ; op1:f31; dest:x31; op1val:0xc1d9136562694646; valaddr_reg:x4;
val_offset:12*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
fcsr_val:0*/
TEST_FPID_OP(fcvt.wu.d, x31, f31, dyn, 0, 0, x4, 12*FLEN/8, x5, x1, x2,FLREG)
inst_37:// fs1 == 1 and fe1 == 0x41e and fm1 == 0xe9b7e5fc9eba4 and fcsr == 0x0 and rm_val == 7
/* opcode: fcvt.wu.d ; op1:f31; dest:x31; op1val:0xc1ee9b7e5fc9eba4; valaddr_reg:x4;
val_offset:13*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
fcsr_val:0*/
TEST_FPID_OP(fcvt.wu.d, x31, f31, dyn, 0, 0, x4, 13*FLEN/8, x5, x1, x2,FLREG)
inst_38:// fs1 == 1 and fe1 == 0x41f and fm1 == 0x1ce80265039f6 and fcsr == 0x0 and rm_val == 7
/* opcode: fcvt.wu.d ; op1:f31; dest:x31; op1val:0xc1f1ce80265039f6; valaddr_reg:x4;
val_offset:14*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
fcsr_val:0*/
TEST_FPID_OP(fcvt.wu.d, x31, f31, dyn, 0, 0, x4, 14*FLEN/8, x5, x1, x2,FLREG)
inst_39:// fs1 == 1 and fe1 == 0x421 and fm1 == 0x2a96d71097999 and fcsr == 0x0 and rm_val == 7
/* opcode: fcvt.wu.d ; op1:f31; dest:x31; op1val:0xc212a96d71097999; valaddr_reg:x4;
val_offset:15*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
fcsr_val:0*/
TEST_FPID_OP(fcvt.wu.d, x31, f31, dyn, 0, 0, x4, 15*FLEN/8, x5, x1, x2,FLREG)
inst_40:// fs1 == 1 and fe1 == 0x40b and fm1 == 0xc491074f942cb and fcsr == 0x0 and rm_val == 7
/* opcode: fcvt.wu.d ; op1:f31; dest:x31; op1val:0xc0bc491074f942cb; valaddr_reg:x4;
val_offset:16*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
fcsr_val:0*/
TEST_FPID_OP(fcvt.wu.d, x31, f31, dyn, 0, 0, x4, 16*FLEN/8, x5, x1, x2,FLREG)
#endif
RVTEST_CODE_END
RVMODEL_HALT
RVTEST_DATA_BEGIN
.align 4
rvtest_data:
.word 0xbabecafe
.word 0xabecafeb
.word 0xbecafeba
.word 0xecafebab
test_dataset_0:
NAN_BOXED(4369351494470010614,64,FLEN)
NAN_BOXED(4593818368519663827,64,FLEN)
NAN_BOXED(4600778710533613932,64,FLEN)
NAN_BOXED(4610891533192108602,64,FLEN)
NAN_BOXED(4615336721960794565,64,FLEN)
NAN_BOXED(4618534502842412089,64,FLEN)
NAN_BOXED(4621035893055613763,64,FLEN)
NAN_BOXED(4631326933921979375,64,FLEN)
NAN_BOXED(4638077838352651716,64,FLEN)
NAN_BOXED(4640306763955614505,64,FLEN)
NAN_BOXED(4648896204934643469,64,FLEN)
NAN_BOXED(4655307257518962220,64,FLEN)
NAN_BOXED(4658354964109640371,64,FLEN)
NAN_BOXED(4672994990543913398,64,FLEN)
NAN_BOXED(4677361703570418210,64,FLEN)
NAN_BOXED(4679843370855813347,64,FLEN)
NAN_BOXED(4687840036054730320,64,FLEN)
NAN_BOXED(4693832498796310654,64,FLEN)
NAN_BOXED(4699726807839813954,64,FLEN)
NAN_BOXED(4703874585615907223,64,FLEN)
NAN_BOXED(4708894174956063846,64,FLEN)
NAN_BOXED(4713025646552733045,64,FLEN)
NAN_BOXED(4720845951218080959,64,FLEN)
NAN_BOXED(4726512510388178185,64,FLEN)
test_dataset_1:
NAN_BOXED(4738151372785550676,64,FLEN)
NAN_BOXED(4759283114051108871,64,FLEN)
NAN_BOXED(6678705328603284080,64,FLEN)
NAN_BOXED(13828134130799532672,64,FLEN)
NAN_BOXED(13852859960080232326,64,FLEN)
NAN_BOXED(13867860556282066179,64,FLEN)
NAN_BOXED(13888055685934564043,64,FLEN)
NAN_BOXED(13890179326181076829,64,FLEN)
NAN_BOXED(13913268222339967668,64,FLEN)
NAN_BOXED(13939651000867015119,64,FLEN)
NAN_BOXED(13954883879667454778,64,FLEN)
NAN_BOXED(13959057841646001890,64,FLEN)
NAN_BOXED(13968217045429995078,64,FLEN)
NAN_BOXED(13974277660852480932,64,FLEN)
NAN_BOXED(13975178168501287414,64,FLEN)
NAN_BOXED(13984426080451787161,64,FLEN)
NAN_BOXED(13888055685934564043,64,FLEN)
RVTEST_DATA_END
RVMODEL_DATA_BEGIN
rvtest_sig_begin:
sig_begin_canary:
CANARY;
signature_x3_0:
.fill 0*((SIGALIGN)/4),4,0xdeadbeef
signature_x3_1:
.fill 54*((SIGALIGN)/4),4,0xdeadbeef
signature_x1_0:
.fill 28*((SIGALIGN)/4),4,0xdeadbeef
#ifdef rvtest_mtrap_routine
tsig_begin_canary:
CANARY;
tsig_begin_canary:
CANARY;
mtrap_sigptr:
.fill 64*(XLEN/32),4,0xdeadbeef
tsig_end_canary:
CANARY;
tsig_end_canary:
CANARY;
#endif
#ifdef rvtest_gpr_save
gpr_save:
.fill 32*XLEN/32,4,0xdeadbeef
#endif
sig_end_canary:
CANARY;
rvtest_sig_end:
RVMODEL_DATA_END

421
vendor/riscv-arch-tests/riscv-test-suite/rv32i_m/D/src/fcvt.wu.d_b23-01.S vendored
View file

@ -1,421 +0,0 @@
// -----------
// This file was generated by riscv_ctg (https://github.com/riscv-software-src/riscv-ctg)
// version : 0.7.1
// timestamp : Fri Jun 17 14:03:51 2022 GMT
// usage : riscv_ctg \
// -- cgf // --cgf /scratch/pawan/work/normalised/RV32D/fcvt.wu.d.cgf \
\
// -- xlen 32 \
// --randomize \
// -----------
//
// -----------
// Copyright (c) 2020. RISC-V International. All rights reserved.
// SPDX-License-Identifier: BSD-3-Clause
// -----------
//
// This assembly file tests the fcvt.wu.d instruction of the RISC-V RV32FD_Zicsr,RV64FD_Zicsr extension for the fcvt.wu.d_b23 covergroup.
//
#include "model_test.h"
#include "arch_test.h"
RVTEST_ISA("RV32IFD_Zicsr,RV64IFD_Zicsr")
.section .text.init
.org 0x80
.globl rvtest_entry_point
rvtest_entry_point:
RVMODEL_BOOT
RVTEST_CODE_BEGIN
#ifdef TEST_CASE_1
RVTEST_CASE(0,"//check ISA:=regex(.*I.*D.*);def TEST_CASE_1=True;",fcvt.wu.d_b23)
RVTEST_FP_ENABLE()
RVTEST_VALBASEUPD(x8,test_dataset_0)
RVTEST_SIGBASE(x5,signature_x5_1)
inst_0:// rs1==f22, rd==x12,fs1 == 0 and fe1 == 0x43d and fm1 == 0xffffffffffffc and fcsr == 0x0 and rm_val == 7
/* opcode: fcvt.wu.d ; op1:f22; dest:x12; op1val:0x43dffffffffffffc; valaddr_reg:x8;
val_offset:0*FLEN/8; rmval:dyn; correctval:??; testreg:x3;
fcsr_val:0*/
TEST_FPID_OP(fcvt.wu.d, x12, f22, dyn, 0, 0, x8, 0*FLEN/8, x13, x5, x3,FLREG)
inst_1:// rs1==f29, rd==x20,fs1 == 0 and fe1 == 0x43d and fm1 == 0xffffffffffffc and fcsr == 0x20 and rm_val == 7
/* opcode: fcvt.wu.d ; op1:f29; dest:x20; op1val:0x43dffffffffffffc; valaddr_reg:x8;
val_offset:1*FLEN/8; rmval:dyn; correctval:??; testreg:x3;
fcsr_val:32*/
TEST_FPID_OP(fcvt.wu.d, x20, f29, dyn, 32, 0, x8, 1*FLEN/8, x13, x5, x3,FLREG)
inst_2:// rs1==f7, rd==x29,fs1 == 0 and fe1 == 0x43d and fm1 == 0xffffffffffffc and fcsr == 0x40 and rm_val == 7
/* opcode: fcvt.wu.d ; op1:f7; dest:x29; op1val:0x43dffffffffffffc; valaddr_reg:x8;
val_offset:2*FLEN/8; rmval:dyn; correctval:??; testreg:x3;
fcsr_val:64*/
TEST_FPID_OP(fcvt.wu.d, x29, f7, dyn, 64, 0, x8, 2*FLEN/8, x13, x5, x3,FLREG)
inst_3:// rs1==f6, rd==x0,fs1 == 0 and fe1 == 0x43d and fm1 == 0xffffffffffffc and fcsr == 0x60 and rm_val == 7
/* opcode: fcvt.wu.d ; op1:f6; dest:x0; op1val:0x43dffffffffffffc; valaddr_reg:x8;
val_offset:3*FLEN/8; rmval:dyn; correctval:??; testreg:x3;
fcsr_val:96*/
TEST_FPID_OP(fcvt.wu.d, x0, f6, dyn, 96, 0, x8, 3*FLEN/8, x13, x5, x3,FLREG)
inst_4:// rs1==f30, rd==x6,fs1 == 0 and fe1 == 0x43d and fm1 == 0xffffffffffffc and fcsr == 0x80 and rm_val == 7
/* opcode: fcvt.wu.d ; op1:f30; dest:x6; op1val:0x43dffffffffffffc; valaddr_reg:x8;
val_offset:4*FLEN/8; rmval:dyn; correctval:??; testreg:x3;
fcsr_val:128*/
TEST_FPID_OP(fcvt.wu.d, x6, f30, dyn, 128, 0, x8, 4*FLEN/8, x13, x5, x3,FLREG)
inst_5:// rs1==f15, rd==x9,fs1 == 0 and fe1 == 0x43d and fm1 == 0xffffffffffffd and fcsr == 0x0 and rm_val == 7
/* opcode: fcvt.wu.d ; op1:f15; dest:x9; op1val:0x43dffffffffffffd; valaddr_reg:x8;
val_offset:5*FLEN/8; rmval:dyn; correctval:??; testreg:x3;
fcsr_val:0*/
TEST_FPID_OP(fcvt.wu.d, x9, f15, dyn, 0, 0, x8, 5*FLEN/8, x13, x5, x3,FLREG)
inst_6:// rs1==f13, rd==x17,fs1 == 0 and fe1 == 0x43d and fm1 == 0xffffffffffffd and fcsr == 0x20 and rm_val == 7
/* opcode: fcvt.wu.d ; op1:f13; dest:x17; op1val:0x43dffffffffffffd; valaddr_reg:x8;
val_offset:6*FLEN/8; rmval:dyn; correctval:??; testreg:x3;
fcsr_val:32*/
TEST_FPID_OP(fcvt.wu.d, x17, f13, dyn, 32, 0, x8, 6*FLEN/8, x13, x5, x3,FLREG)
inst_7:// rs1==f19, rd==x4,fs1 == 0 and fe1 == 0x43d and fm1 == 0xffffffffffffd and fcsr == 0x40 and rm_val == 7
/* opcode: fcvt.wu.d ; op1:f19; dest:x4; op1val:0x43dffffffffffffd; valaddr_reg:x8;
val_offset:7*FLEN/8; rmval:dyn; correctval:??; testreg:x3;
fcsr_val:64*/
TEST_FPID_OP(fcvt.wu.d, x4, f19, dyn, 64, 0, x8, 7*FLEN/8, x13, x5, x3,FLREG)
inst_8:// rs1==f9, rd==x2,fs1 == 0 and fe1 == 0x43d and fm1 == 0xffffffffffffd and fcsr == 0x60 and rm_val == 7
/* opcode: fcvt.wu.d ; op1:f9; dest:x2; op1val:0x43dffffffffffffd; valaddr_reg:x8;
val_offset:8*FLEN/8; rmval:dyn; correctval:??; testreg:x3;
fcsr_val:96*/
TEST_FPID_OP(fcvt.wu.d, x2, f9, dyn, 96, 0, x8, 8*FLEN/8, x13, x5, x3,FLREG)
inst_9:// rs1==f10, rd==x16,fs1 == 0 and fe1 == 0x43d and fm1 == 0xffffffffffffd and fcsr == 0x80 and rm_val == 7
/* opcode: fcvt.wu.d ; op1:f10; dest:x16; op1val:0x43dffffffffffffd; valaddr_reg:x8;
val_offset:9*FLEN/8; rmval:dyn; correctval:??; testreg:x3;
fcsr_val:128*/
TEST_FPID_OP(fcvt.wu.d, x16, f10, dyn, 128, 0, x8, 9*FLEN/8, x13, x5, x3,FLREG)
inst_10:// rs1==f8, rd==x22,fs1 == 0 and fe1 == 0x43d and fm1 == 0xffffffffffffe and fcsr == 0x0 and rm_val == 7
/* opcode: fcvt.wu.d ; op1:f8; dest:x22; op1val:0x43dffffffffffffe; valaddr_reg:x8;
val_offset:10*FLEN/8; rmval:dyn; correctval:??; testreg:x3;
fcsr_val:0*/
TEST_FPID_OP(fcvt.wu.d, x22, f8, dyn, 0, 0, x8, 10*FLEN/8, x13, x5, x3,FLREG)
inst_11:// rs1==f11, rd==x28,fs1 == 0 and fe1 == 0x43d and fm1 == 0xffffffffffffe and fcsr == 0x20 and rm_val == 7
/* opcode: fcvt.wu.d ; op1:f11; dest:x28; op1val:0x43dffffffffffffe; valaddr_reg:x8;
val_offset:11*FLEN/8; rmval:dyn; correctval:??; testreg:x3;
fcsr_val:32*/
TEST_FPID_OP(fcvt.wu.d, x28, f11, dyn, 32, 0, x8, 11*FLEN/8, x13, x5, x3,FLREG)
inst_12:// rs1==f31, rd==x19,fs1 == 0 and fe1 == 0x43d and fm1 == 0xffffffffffffe and fcsr == 0x40 and rm_val == 7
/* opcode: fcvt.wu.d ; op1:f31; dest:x19; op1val:0x43dffffffffffffe; valaddr_reg:x8;
val_offset:12*FLEN/8; rmval:dyn; correctval:??; testreg:x3;
fcsr_val:64*/
TEST_FPID_OP(fcvt.wu.d, x19, f31, dyn, 64, 0, x8, 12*FLEN/8, x13, x5, x3,FLREG)
inst_13:// rs1==f21, rd==x11,fs1 == 0 and fe1 == 0x43d and fm1 == 0xffffffffffffe and fcsr == 0x60 and rm_val == 7
/* opcode: fcvt.wu.d ; op1:f21; dest:x11; op1val:0x43dffffffffffffe; valaddr_reg:x8;
val_offset:13*FLEN/8; rmval:dyn; correctval:??; testreg:x3;
fcsr_val:96*/
TEST_FPID_OP(fcvt.wu.d, x11, f21, dyn, 96, 0, x8, 13*FLEN/8, x13, x5, x3,FLREG)
inst_14:// rs1==f0, rd==x26,fs1 == 0 and fe1 == 0x43d and fm1 == 0xffffffffffffe and fcsr == 0x80 and rm_val == 7
/* opcode: fcvt.wu.d ; op1:f0; dest:x26; op1val:0x43dffffffffffffe; valaddr_reg:x8;
val_offset:14*FLEN/8; rmval:dyn; correctval:??; testreg:x3;
fcsr_val:128*/
TEST_FPID_OP(fcvt.wu.d, x26, f0, dyn, 128, 0, x8, 14*FLEN/8, x13, x5, x3,FLREG)
inst_15:// rs1==f4, rd==x30,fs1 == 0 and fe1 == 0x43d and fm1 == 0xfffffffffffff and fcsr == 0x0 and rm_val == 7
/* opcode: fcvt.wu.d ; op1:f4; dest:x30; op1val:0x43dfffffffffffff; valaddr_reg:x8;
val_offset:15*FLEN/8; rmval:dyn; correctval:??; testreg:x3;
fcsr_val:0*/
TEST_FPID_OP(fcvt.wu.d, x30, f4, dyn, 0, 0, x8, 15*FLEN/8, x13, x5, x3,FLREG)
inst_16:// rs1==f20, rd==x10,fs1 == 0 and fe1 == 0x43d and fm1 == 0xfffffffffffff and fcsr == 0x20 and rm_val == 7
/* opcode: fcvt.wu.d ; op1:f20; dest:x10; op1val:0x43dfffffffffffff; valaddr_reg:x8;
val_offset:16*FLEN/8; rmval:dyn; correctval:??; testreg:x3;
fcsr_val:32*/
TEST_FPID_OP(fcvt.wu.d, x10, f20, dyn, 32, 0, x8, 16*FLEN/8, x13, x5, x3,FLREG)
inst_17:// rs1==f5, rd==x1,fs1 == 0 and fe1 == 0x43d and fm1 == 0xfffffffffffff and fcsr == 0x40 and rm_val == 7
/* opcode: fcvt.wu.d ; op1:f5; dest:x1; op1val:0x43dfffffffffffff; valaddr_reg:x8;
val_offset:17*FLEN/8; rmval:dyn; correctval:??; testreg:x3;
fcsr_val:64*/
TEST_FPID_OP(fcvt.wu.d, x1, f5, dyn, 64, 0, x8, 17*FLEN/8, x13, x5, x3,FLREG)
inst_18:// rs1==f2, rd==x7,fs1 == 0 and fe1 == 0x43d and fm1 == 0xfffffffffffff and fcsr == 0x60 and rm_val == 7
/* opcode: fcvt.wu.d ; op1:f2; dest:x7; op1val:0x43dfffffffffffff; valaddr_reg:x8;
val_offset:18*FLEN/8; rmval:dyn; correctval:??; testreg:x3;
fcsr_val:96*/
TEST_FPID_OP(fcvt.wu.d, x7, f2, dyn, 96, 0, x8, 18*FLEN/8, x13, x5, x3,FLREG)
inst_19:// rs1==f3, rd==x25,fs1 == 0 and fe1 == 0x43d and fm1 == 0xfffffffffffff and fcsr == 0x80 and rm_val == 7
/* opcode: fcvt.wu.d ; op1:f3; dest:x25; op1val:0x43dfffffffffffff; valaddr_reg:x8;
val_offset:19*FLEN/8; rmval:dyn; correctval:??; testreg:x3;
fcsr_val:128*/
TEST_FPID_OP(fcvt.wu.d, x25, f3, dyn, 128, 0, x8, 19*FLEN/8, x13, x5, x3,FLREG)
inst_20:// rs1==f24, rd==x27,fs1 == 0 and fe1 == 0x43e and fm1 == 0x0000000000000 and fcsr == 0x0 and rm_val == 7
/* opcode: fcvt.wu.d ; op1:f24; dest:x27; op1val:0x43e0000000000000; valaddr_reg:x8;
val_offset:20*FLEN/8; rmval:dyn; correctval:??; testreg:x3;
fcsr_val:0*/
TEST_FPID_OP(fcvt.wu.d, x27, f24, dyn, 0, 0, x8, 20*FLEN/8, x13, x5, x3,FLREG)
inst_21:// rs1==f27, rd==x31,fs1 == 0 and fe1 == 0x43e and fm1 == 0x0000000000000 and fcsr == 0x20 and rm_val == 7
/* opcode: fcvt.wu.d ; op1:f27; dest:x31; op1val:0x43e0000000000000; valaddr_reg:x8;
val_offset:21*FLEN/8; rmval:dyn; correctval:??; testreg:x3;
fcsr_val:32*/
TEST_FPID_OP(fcvt.wu.d, x31, f27, dyn, 32, 0, x8, 21*FLEN/8, x13, x5, x3,FLREG)
inst_22:// rs1==f12, rd==x14,fs1 == 0 and fe1 == 0x43e and fm1 == 0x0000000000000 and fcsr == 0x40 and rm_val == 7
/* opcode: fcvt.wu.d ; op1:f12; dest:x14; op1val:0x43e0000000000000; valaddr_reg:x8;
val_offset:22*FLEN/8; rmval:dyn; correctval:??; testreg:x3;
fcsr_val:64*/
TEST_FPID_OP(fcvt.wu.d, x14, f12, dyn, 64, 0, x8, 22*FLEN/8, x13, x5, x3,FLREG)
inst_23:// rs1==f1, rd==x21,fs1 == 0 and fe1 == 0x43e and fm1 == 0x0000000000000 and fcsr == 0x60 and rm_val == 7
/* opcode: fcvt.wu.d ; op1:f1; dest:x21; op1val:0x43e0000000000000; valaddr_reg:x8;
val_offset:23*FLEN/8; rmval:dyn; correctval:??; testreg:x3;
fcsr_val:96*/
TEST_FPID_OP(fcvt.wu.d, x21, f1, dyn, 96, 0, x8, 23*FLEN/8, x13, x5, x3,FLREG)
inst_24:// rs1==f25, rd==x15,fs1 == 0 and fe1 == 0x43e and fm1 == 0x0000000000000 and fcsr == 0x80 and rm_val == 7
/* opcode: fcvt.wu.d ; op1:f25; dest:x15; op1val:0x43e0000000000000; valaddr_reg:x8;
val_offset:24*FLEN/8; rmval:dyn; correctval:??; testreg:x3;
fcsr_val:128*/
TEST_FPID_OP(fcvt.wu.d, x15, f25, dyn, 128, 0, x8, 24*FLEN/8, x13, x5, x3,FLREG)
RVTEST_VALBASEUPD(x4,test_dataset_1)
inst_25:// rs1==f14, rd==x18,fs1 == 0 and fe1 == 0x43e and fm1 == 0x0000000000001 and fcsr == 0x0 and rm_val == 7
/* opcode: fcvt.wu.d ; op1:f14; dest:x18; op1val:0x43e0000000000001; valaddr_reg:x4;
val_offset:0*FLEN/8; rmval:dyn; correctval:??; testreg:x3;
fcsr_val:0*/
TEST_FPID_OP(fcvt.wu.d, x18, f14, dyn, 0, 0, x4, 0*FLEN/8, x6, x5, x3,FLREG)
inst_26:// rs1==f17, rd==x8,fs1 == 0 and fe1 == 0x43e and fm1 == 0x0000000000001 and fcsr == 0x20 and rm_val == 7
/* opcode: fcvt.wu.d ; op1:f17; dest:x8; op1val:0x43e0000000000001; valaddr_reg:x4;
val_offset:1*FLEN/8; rmval:dyn; correctval:??; testreg:x3;
fcsr_val:32*/
TEST_FPID_OP(fcvt.wu.d, x8, f17, dyn, 32, 0, x4, 1*FLEN/8, x6, x5, x3,FLREG)
inst_27:// rs1==f23, rd==x3,fs1 == 0 and fe1 == 0x43e and fm1 == 0x0000000000001 and fcsr == 0x40 and rm_val == 7
/* opcode: fcvt.wu.d ; op1:f23; dest:x3; op1val:0x43e0000000000001; valaddr_reg:x4;
val_offset:2*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
fcsr_val:64*/
TEST_FPID_OP(fcvt.wu.d, x3, f23, dyn, 64, 0, x4, 2*FLEN/8, x6, x5, x2,FLREG)
RVTEST_SIGBASE(x1,signature_x1_0)
inst_28:// rs1==f28, rd==x24,fs1 == 0 and fe1 == 0x43e and fm1 == 0x0000000000001 and fcsr == 0x60 and rm_val == 7
/* opcode: fcvt.wu.d ; op1:f28; dest:x24; op1val:0x43e0000000000001; valaddr_reg:x4;
val_offset:3*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
fcsr_val:96*/
TEST_FPID_OP(fcvt.wu.d, x24, f28, dyn, 96, 0, x4, 3*FLEN/8, x6, x1, x2,FLREG)
inst_29:// rs1==f26, rd==x5,fs1 == 0 and fe1 == 0x43e and fm1 == 0x0000000000001 and fcsr == 0x80 and rm_val == 7
/* opcode: fcvt.wu.d ; op1:f26; dest:x5; op1val:0x43e0000000000001; valaddr_reg:x4;
val_offset:4*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
fcsr_val:128*/
TEST_FPID_OP(fcvt.wu.d, x5, f26, dyn, 128, 0, x4, 4*FLEN/8, x6, x1, x2,FLREG)
inst_30:// rs1==f18, rd==x23,fs1 == 0 and fe1 == 0x43e and fm1 == 0x0000000000002 and fcsr == 0x0 and rm_val == 7
/* opcode: fcvt.wu.d ; op1:f18; dest:x23; op1val:0x43e0000000000002; valaddr_reg:x4;
val_offset:5*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
fcsr_val:0*/
TEST_FPID_OP(fcvt.wu.d, x23, f18, dyn, 0, 0, x4, 5*FLEN/8, x6, x1, x2,FLREG)
inst_31:// rs1==f16, rd==x13,fs1 == 0 and fe1 == 0x43e and fm1 == 0x0000000000002 and fcsr == 0x20 and rm_val == 7
/* opcode: fcvt.wu.d ; op1:f16; dest:x13; op1val:0x43e0000000000002; valaddr_reg:x4;
val_offset:6*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
fcsr_val:32*/
TEST_FPID_OP(fcvt.wu.d, x13, f16, dyn, 32, 0, x4, 6*FLEN/8, x6, x1, x2,FLREG)
inst_32:// fs1 == 0 and fe1 == 0x43e and fm1 == 0x0000000000002 and fcsr == 0x40 and rm_val == 7
/* opcode: fcvt.wu.d ; op1:f31; dest:x31; op1val:0x43e0000000000002; valaddr_reg:x4;
val_offset:7*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
fcsr_val:64*/
TEST_FPID_OP(fcvt.wu.d, x31, f31, dyn, 64, 0, x4, 7*FLEN/8, x6, x1, x2,FLREG)
inst_33:// fs1 == 0 and fe1 == 0x43e and fm1 == 0x0000000000002 and fcsr == 0x60 and rm_val == 7
/* opcode: fcvt.wu.d ; op1:f31; dest:x31; op1val:0x43e0000000000002; valaddr_reg:x4;
val_offset:8*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
fcsr_val:96*/
TEST_FPID_OP(fcvt.wu.d, x31, f31, dyn, 96, 0, x4, 8*FLEN/8, x6, x1, x2,FLREG)
inst_34:// fs1 == 0 and fe1 == 0x43e and fm1 == 0x0000000000002 and fcsr == 0x80 and rm_val == 7
/* opcode: fcvt.wu.d ; op1:f31; dest:x31; op1val:0x43e0000000000002; valaddr_reg:x4;
val_offset:9*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
fcsr_val:128*/
TEST_FPID_OP(fcvt.wu.d, x31, f31, dyn, 128, 0, x4, 9*FLEN/8, x6, x1, x2,FLREG)
inst_35:// fs1 == 0 and fe1 == 0x43e and fm1 == 0x0000000000003 and fcsr == 0x0 and rm_val == 7
/* opcode: fcvt.wu.d ; op1:f31; dest:x31; op1val:0x43e0000000000003; valaddr_reg:x4;
val_offset:10*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
fcsr_val:0*/
TEST_FPID_OP(fcvt.wu.d, x31, f31, dyn, 0, 0, x4, 10*FLEN/8, x6, x1, x2,FLREG)
inst_36:// fs1 == 0 and fe1 == 0x43e and fm1 == 0x0000000000003 and fcsr == 0x20 and rm_val == 7
/* opcode: fcvt.wu.d ; op1:f31; dest:x31; op1val:0x43e0000000000003; valaddr_reg:x4;
val_offset:11*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
fcsr_val:32*/
TEST_FPID_OP(fcvt.wu.d, x31, f31, dyn, 32, 0, x4, 11*FLEN/8, x6, x1, x2,FLREG)
inst_37:// fs1 == 0 and fe1 == 0x43e and fm1 == 0x0000000000003 and fcsr == 0x40 and rm_val == 7
/* opcode: fcvt.wu.d ; op1:f31; dest:x31; op1val:0x43e0000000000003; valaddr_reg:x4;
val_offset:12*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
fcsr_val:64*/
TEST_FPID_OP(fcvt.wu.d, x31, f31, dyn, 64, 0, x4, 12*FLEN/8, x6, x1, x2,FLREG)
inst_38:// fs1 == 0 and fe1 == 0x43e and fm1 == 0x0000000000003 and fcsr == 0x60 and rm_val == 7
/* opcode: fcvt.wu.d ; op1:f31; dest:x31; op1val:0x43e0000000000003; valaddr_reg:x4;
val_offset:13*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
fcsr_val:96*/
TEST_FPID_OP(fcvt.wu.d, x31, f31, dyn, 96, 0, x4, 13*FLEN/8, x6, x1, x2,FLREG)
inst_39:// fs1 == 0 and fe1 == 0x43e and fm1 == 0x0000000000003 and fcsr == 0x80 and rm_val == 7
/* opcode: fcvt.wu.d ; op1:f31; dest:x31; op1val:0x43e0000000000003; valaddr_reg:x4;
val_offset:14*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
fcsr_val:128*/
TEST_FPID_OP(fcvt.wu.d, x31, f31, dyn, 128, 0, x4, 14*FLEN/8, x6, x1, x2,FLREG)
inst_40:// fs1 == 0 and fe1 == 0x43e and fm1 == 0x0000000000004 and fcsr == 0x0 and rm_val == 7
/* opcode: fcvt.wu.d ; op1:f31; dest:x31; op1val:0x43e0000000000004; valaddr_reg:x4;
val_offset:15*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
fcsr_val:0*/
TEST_FPID_OP(fcvt.wu.d, x31, f31, dyn, 0, 0, x4, 15*FLEN/8, x6, x1, x2,FLREG)
inst_41:// fs1 == 0 and fe1 == 0x43e and fm1 == 0x0000000000004 and fcsr == 0x20 and rm_val == 7
/* opcode: fcvt.wu.d ; op1:f31; dest:x31; op1val:0x43e0000000000004; valaddr_reg:x4;
val_offset:16*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
fcsr_val:32*/
TEST_FPID_OP(fcvt.wu.d, x31, f31, dyn, 32, 0, x4, 16*FLEN/8, x6, x1, x2,FLREG)
inst_42:// fs1 == 0 and fe1 == 0x43e and fm1 == 0x0000000000004 and fcsr == 0x40 and rm_val == 7
/* opcode: fcvt.wu.d ; op1:f31; dest:x31; op1val:0x43e0000000000004; valaddr_reg:x4;
val_offset:17*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
fcsr_val:64*/
TEST_FPID_OP(fcvt.wu.d, x31, f31, dyn, 64, 0, x4, 17*FLEN/8, x6, x1, x2,FLREG)
inst_43:// fs1 == 0 and fe1 == 0x43e and fm1 == 0x0000000000004 and fcsr == 0x60 and rm_val == 7
/* opcode: fcvt.wu.d ; op1:f31; dest:x31; op1val:0x43e0000000000004; valaddr_reg:x4;
val_offset:18*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
fcsr_val:96*/
TEST_FPID_OP(fcvt.wu.d, x31, f31, dyn, 96, 0, x4, 18*FLEN/8, x6, x1, x2,FLREG)
inst_44:// fs1 == 0 and fe1 == 0x43e and fm1 == 0x0000000000004 and fcsr == 0x80 and rm_val == 7
/* opcode: fcvt.wu.d ; op1:f31; dest:x31; op1val:0x43e0000000000004; valaddr_reg:x4;
val_offset:19*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
fcsr_val:128*/
TEST_FPID_OP(fcvt.wu.d, x31, f31, dyn, 128, 0, x4, 19*FLEN/8, x6, x1, x2,FLREG)
inst_45:// fs1 == 0 and fe1 == 0x43d and fm1 == 0xffffffffffffc and fcsr == 0x60 and rm_val == 7
/* opcode: fcvt.wu.d ; op1:f31; dest:x31; op1val:0x43dffffffffffffc; valaddr_reg:x4;
val_offset:20*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
fcsr_val:96*/
TEST_FPID_OP(fcvt.wu.d, x31, f31, dyn, 96, 0, x4, 20*FLEN/8, x6, x1, x2,FLREG)
#endif
RVTEST_CODE_END
RVMODEL_HALT
RVTEST_DATA_BEGIN
.align 4
rvtest_data:
.word 0xbabecafe
.word 0xabecafeb
.word 0xbecafeba
.word 0xecafebab
test_dataset_0:
NAN_BOXED(4890909195324358652,64,FLEN)
NAN_BOXED(4890909195324358652,64,FLEN)
NAN_BOXED(4890909195324358652,64,FLEN)
NAN_BOXED(4890909195324358652,64,FLEN)
NAN_BOXED(4890909195324358652,64,FLEN)
NAN_BOXED(4890909195324358653,64,FLEN)
NAN_BOXED(4890909195324358653,64,FLEN)
NAN_BOXED(4890909195324358653,64,FLEN)
NAN_BOXED(4890909195324358653,64,FLEN)
NAN_BOXED(4890909195324358653,64,FLEN)
NAN_BOXED(4890909195324358654,64,FLEN)
NAN_BOXED(4890909195324358654,64,FLEN)
NAN_BOXED(4890909195324358654,64,FLEN)
NAN_BOXED(4890909195324358654,64,FLEN)
NAN_BOXED(4890909195324358654,64,FLEN)
NAN_BOXED(4890909195324358655,64,FLEN)
NAN_BOXED(4890909195324358655,64,FLEN)
NAN_BOXED(4890909195324358655,64,FLEN)
NAN_BOXED(4890909195324358655,64,FLEN)
NAN_BOXED(4890909195324358655,64,FLEN)
NAN_BOXED(4890909195324358656,64,FLEN)
NAN_BOXED(4890909195324358656,64,FLEN)
NAN_BOXED(4890909195324358656,64,FLEN)
NAN_BOXED(4890909195324358656,64,FLEN)
NAN_BOXED(4890909195324358656,64,FLEN)
test_dataset_1:
NAN_BOXED(4890909195324358657,64,FLEN)
NAN_BOXED(4890909195324358657,64,FLEN)
NAN_BOXED(4890909195324358657,64,FLEN)
NAN_BOXED(4890909195324358657,64,FLEN)
NAN_BOXED(4890909195324358657,64,FLEN)
NAN_BOXED(4890909195324358658,64,FLEN)
NAN_BOXED(4890909195324358658,64,FLEN)
NAN_BOXED(4890909195324358658,64,FLEN)
NAN_BOXED(4890909195324358658,64,FLEN)
NAN_BOXED(4890909195324358658,64,FLEN)
NAN_BOXED(4890909195324358659,64,FLEN)
NAN_BOXED(4890909195324358659,64,FLEN)
NAN_BOXED(4890909195324358659,64,FLEN)
NAN_BOXED(4890909195324358659,64,FLEN)
NAN_BOXED(4890909195324358659,64,FLEN)
NAN_BOXED(4890909195324358660,64,FLEN)
NAN_BOXED(4890909195324358660,64,FLEN)
NAN_BOXED(4890909195324358660,64,FLEN)
NAN_BOXED(4890909195324358660,64,FLEN)
NAN_BOXED(4890909195324358660,64,FLEN)
NAN_BOXED(4890909195324358652,64,FLEN)
RVTEST_DATA_END
RVMODEL_DATA_BEGIN
rvtest_sig_begin:
sig_begin_canary:
CANARY;
signature_x5_0:
.fill 0*((SIGALIGN)/4),4,0xdeadbeef
signature_x5_1:
.fill 56*((SIGALIGN)/4),4,0xdeadbeef
signature_x1_0:
.fill 36*((SIGALIGN)/4),4,0xdeadbeef
#ifdef rvtest_mtrap_routine
tsig_begin_canary:
CANARY;
tsig_begin_canary:
CANARY;
mtrap_sigptr:
.fill 64*(XLEN/32),4,0xdeadbeef
tsig_end_canary:
CANARY;
tsig_end_canary:
CANARY;
#endif
#ifdef rvtest_gpr_save
gpr_save:
.fill 32*XLEN/32,4,0xdeadbeef
#endif
sig_end_canary:
CANARY;
rvtest_sig_end:
RVMODEL_DATA_END

841
vendor/riscv-arch-tests/riscv-test-suite/rv32i_m/D/src/fcvt.wu.d_b24-01.S vendored
View file

@ -1,841 +0,0 @@
// -----------
// This file was generated by riscv_ctg (https://github.com/riscv-software-src/riscv-ctg)
// version : 0.7.1
// timestamp : Fri Jun 17 14:03:51 2022 GMT
// usage : riscv_ctg \
// -- cgf // --cgf /scratch/pawan/work/normalised/RV32D/fcvt.wu.d.cgf \
\
// -- xlen 32 \
// --randomize \
// -----------
//
// -----------
// Copyright (c) 2020. RISC-V International. All rights reserved.
// SPDX-License-Identifier: BSD-3-Clause
// -----------
//
// This assembly file tests the fcvt.wu.d instruction of the RISC-V RV32FD_Zicsr,RV64FD_Zicsr extension for the fcvt.wu.d_b24 covergroup.
//
#include "model_test.h"
#include "arch_test.h"
RVTEST_ISA("RV32IFD_Zicsr,RV64IFD_Zicsr")
.section .text.init
.org 0x80
.globl rvtest_entry_point
rvtest_entry_point:
RVMODEL_BOOT
RVTEST_CODE_BEGIN
#ifdef TEST_CASE_1
RVTEST_CASE(0,"//check ISA:=regex(.*I.*D.*);def TEST_CASE_1=True;",fcvt.wu.d_b24)
RVTEST_FP_ENABLE()
RVTEST_VALBASEUPD(x10,test_dataset_0)
RVTEST_SIGBASE(x17,signature_x17_1)
inst_0:// rs1==f31, rd==x1,fs1 == 0 and fe1 == 0x000 and fm1 == 0x0000000000000 and fcsr == 0x0 and rm_val == 7
/* opcode: fcvt.wu.d ; op1:f31; dest:x1; op1val:0x0; valaddr_reg:x10;
val_offset:0*FLEN/8; rmval:dyn; correctval:??; testreg:x3;
fcsr_val:0*/
TEST_FPID_OP(fcvt.wu.d, x1, f31, dyn, 0, 0, x10, 0*FLEN/8, x14, x17, x3,FLREG)
inst_1:// rs1==f6, rd==x18,fs1 == 0 and fe1 == 0x000 and fm1 == 0x0000000000000 and fcsr == 0x20 and rm_val == 7
/* opcode: fcvt.wu.d ; op1:f6; dest:x18; op1val:0x0; valaddr_reg:x10;
val_offset:1*FLEN/8; rmval:dyn; correctval:??; testreg:x3;
fcsr_val:32*/
TEST_FPID_OP(fcvt.wu.d, x18, f6, dyn, 32, 0, x10, 1*FLEN/8, x14, x17, x3,FLREG)
inst_2:// rs1==f8, rd==x16,fs1 == 0 and fe1 == 0x000 and fm1 == 0x0000000000000 and fcsr == 0x40 and rm_val == 7
/* opcode: fcvt.wu.d ; op1:f8; dest:x16; op1val:0x0; valaddr_reg:x10;
val_offset:2*FLEN/8; rmval:dyn; correctval:??; testreg:x3;
fcsr_val:64*/
TEST_FPID_OP(fcvt.wu.d, x16, f8, dyn, 64, 0, x10, 2*FLEN/8, x14, x17, x3,FLREG)
inst_3:// rs1==f11, rd==x22,fs1 == 0 and fe1 == 0x000 and fm1 == 0x0000000000000 and fcsr == 0x60 and rm_val == 7
/* opcode: fcvt.wu.d ; op1:f11; dest:x22; op1val:0x0; valaddr_reg:x10;
val_offset:3*FLEN/8; rmval:dyn; correctval:??; testreg:x3;
fcsr_val:96*/
TEST_FPID_OP(fcvt.wu.d, x22, f11, dyn, 96, 0, x10, 3*FLEN/8, x14, x17, x3,FLREG)
inst_4:// rs1==f21, rd==x7,fs1 == 0 and fe1 == 0x000 and fm1 == 0x0000000000000 and fcsr == 0x80 and rm_val == 7
/* opcode: fcvt.wu.d ; op1:f21; dest:x7; op1val:0x0; valaddr_reg:x10;
val_offset:4*FLEN/8; rmval:dyn; correctval:??; testreg:x3;
fcsr_val:128*/
TEST_FPID_OP(fcvt.wu.d, x7, f21, dyn, 128, 0, x10, 4*FLEN/8, x14, x17, x3,FLREG)
inst_5:// rs1==f5, rd==x19,fs1 == 0 and fe1 == 0x3f8 and fm1 == 0x47ae147ae147b and fcsr == 0x0 and rm_val == 7
/* opcode: fcvt.wu.d ; op1:f5; dest:x19; op1val:0x3f847ae147ae147b; valaddr_reg:x10;
val_offset:5*FLEN/8; rmval:dyn; correctval:??; testreg:x3;
fcsr_val:0*/
TEST_FPID_OP(fcvt.wu.d, x19, f5, dyn, 0, 0, x10, 5*FLEN/8, x14, x17, x3,FLREG)
inst_6:// rs1==f1, rd==x8,fs1 == 0 and fe1 == 0x3f8 and fm1 == 0x47ae147ae147b and fcsr == 0x20 and rm_val == 7
/* opcode: fcvt.wu.d ; op1:f1; dest:x8; op1val:0x3f847ae147ae147b; valaddr_reg:x10;
val_offset:6*FLEN/8; rmval:dyn; correctval:??; testreg:x3;
fcsr_val:32*/
TEST_FPID_OP(fcvt.wu.d, x8, f1, dyn, 32, 0, x10, 6*FLEN/8, x14, x17, x3,FLREG)
inst_7:// rs1==f10, rd==x6,fs1 == 0 and fe1 == 0x3f8 and fm1 == 0x47ae147ae147b and fcsr == 0x40 and rm_val == 7
/* opcode: fcvt.wu.d ; op1:f10; dest:x6; op1val:0x3f847ae147ae147b; valaddr_reg:x10;
val_offset:7*FLEN/8; rmval:dyn; correctval:??; testreg:x3;
fcsr_val:64*/
TEST_FPID_OP(fcvt.wu.d, x6, f10, dyn, 64, 0, x10, 7*FLEN/8, x14, x17, x3,FLREG)
inst_8:// rs1==f19, rd==x5,fs1 == 0 and fe1 == 0x3f8 and fm1 == 0x47ae147ae147b and fcsr == 0x60 and rm_val == 7
/* opcode: fcvt.wu.d ; op1:f19; dest:x5; op1val:0x3f847ae147ae147b; valaddr_reg:x10;
val_offset:8*FLEN/8; rmval:dyn; correctval:??; testreg:x3;
fcsr_val:96*/
TEST_FPID_OP(fcvt.wu.d, x5, f19, dyn, 96, 0, x10, 8*FLEN/8, x14, x17, x3,FLREG)
inst_9:// rs1==f27, rd==x23,fs1 == 0 and fe1 == 0x3f8 and fm1 == 0x47ae147ae147b and fcsr == 0x80 and rm_val == 7
/* opcode: fcvt.wu.d ; op1:f27; dest:x23; op1val:0x3f847ae147ae147b; valaddr_reg:x10;
val_offset:9*FLEN/8; rmval:dyn; correctval:??; testreg:x3;
fcsr_val:128*/
TEST_FPID_OP(fcvt.wu.d, x23, f27, dyn, 128, 0, x10, 9*FLEN/8, x14, x17, x3,FLREG)
inst_10:// rs1==f0, rd==x28,fs1 == 0 and fe1 == 0x3fb and fm1 == 0x999999999999a and fcsr == 0x0 and rm_val == 7
/* opcode: fcvt.wu.d ; op1:f0; dest:x28; op1val:0x3fb999999999999a; valaddr_reg:x10;
val_offset:10*FLEN/8; rmval:dyn; correctval:??; testreg:x3;
fcsr_val:0*/
TEST_FPID_OP(fcvt.wu.d, x28, f0, dyn, 0, 0, x10, 10*FLEN/8, x14, x17, x3,FLREG)
inst_11:// rs1==f24, rd==x2,fs1 == 0 and fe1 == 0x3fb and fm1 == 0x999999999999a and fcsr == 0x20 and rm_val == 7
/* opcode: fcvt.wu.d ; op1:f24; dest:x2; op1val:0x3fb999999999999a; valaddr_reg:x10;
val_offset:11*FLEN/8; rmval:dyn; correctval:??; testreg:x3;
fcsr_val:32*/
TEST_FPID_OP(fcvt.wu.d, x2, f24, dyn, 32, 0, x10, 11*FLEN/8, x14, x17, x3,FLREG)
inst_12:// rs1==f18, rd==x20,fs1 == 0 and fe1 == 0x3fb and fm1 == 0x999999999999a and fcsr == 0x40 and rm_val == 7
/* opcode: fcvt.wu.d ; op1:f18; dest:x20; op1val:0x3fb999999999999a; valaddr_reg:x10;
val_offset:12*FLEN/8; rmval:dyn; correctval:??; testreg:x3;
fcsr_val:64*/
TEST_FPID_OP(fcvt.wu.d, x20, f18, dyn, 64, 0, x10, 12*FLEN/8, x14, x17, x3,FLREG)
inst_13:// rs1==f29, rd==x21,fs1 == 0 and fe1 == 0x3fb and fm1 == 0x999999999999a and fcsr == 0x60 and rm_val == 7
/* opcode: fcvt.wu.d ; op1:f29; dest:x21; op1val:0x3fb999999999999a; valaddr_reg:x10;
val_offset:13*FLEN/8; rmval:dyn; correctval:??; testreg:x3;
fcsr_val:96*/
TEST_FPID_OP(fcvt.wu.d, x21, f29, dyn, 96, 0, x10, 13*FLEN/8, x14, x17, x3,FLREG)
inst_14:// rs1==f17, rd==x12,fs1 == 0 and fe1 == 0x3fb and fm1 == 0x999999999999a and fcsr == 0x80 and rm_val == 7
/* opcode: fcvt.wu.d ; op1:f17; dest:x12; op1val:0x3fb999999999999a; valaddr_reg:x10;
val_offset:14*FLEN/8; rmval:dyn; correctval:??; testreg:x3;
fcsr_val:128*/
TEST_FPID_OP(fcvt.wu.d, x12, f17, dyn, 128, 0, x10, 14*FLEN/8, x14, x17, x3,FLREG)
inst_15:// rs1==f12, rd==x25,fs1 == 0 and fe1 == 0x3fb and fm1 == 0xc28f5c28f5c29 and fcsr == 0x0 and rm_val == 7
/* opcode: fcvt.wu.d ; op1:f12; dest:x25; op1val:0x3fbc28f5c28f5c29; valaddr_reg:x10;
val_offset:15*FLEN/8; rmval:dyn; correctval:??; testreg:x3;
fcsr_val:0*/
TEST_FPID_OP(fcvt.wu.d, x25, f12, dyn, 0, 0, x10, 15*FLEN/8, x14, x17, x3,FLREG)
inst_16:// rs1==f13, rd==x13,fs1 == 0 and fe1 == 0x3fb and fm1 == 0xc28f5c28f5c29 and fcsr == 0x20 and rm_val == 7
/* opcode: fcvt.wu.d ; op1:f13; dest:x13; op1val:0x3fbc28f5c28f5c29; valaddr_reg:x10;
val_offset:16*FLEN/8; rmval:dyn; correctval:??; testreg:x3;
fcsr_val:32*/
TEST_FPID_OP(fcvt.wu.d, x13, f13, dyn, 32, 0, x10, 16*FLEN/8, x14, x17, x3,FLREG)
inst_17:// rs1==f28, rd==x0,fs1 == 0 and fe1 == 0x3fb and fm1 == 0xc28f5c28f5c29 and fcsr == 0x40 and rm_val == 7
/* opcode: fcvt.wu.d ; op1:f28; dest:x0; op1val:0x3fbc28f5c28f5c29; valaddr_reg:x10;
val_offset:17*FLEN/8; rmval:dyn; correctval:??; testreg:x3;
fcsr_val:64*/
TEST_FPID_OP(fcvt.wu.d, x0, f28, dyn, 64, 0, x10, 17*FLEN/8, x14, x17, x3,FLREG)
inst_18:// rs1==f16, rd==x15,fs1 == 0 and fe1 == 0x3fb and fm1 == 0xc28f5c28f5c29 and fcsr == 0x60 and rm_val == 7
/* opcode: fcvt.wu.d ; op1:f16; dest:x15; op1val:0x3fbc28f5c28f5c29; valaddr_reg:x10;
val_offset:18*FLEN/8; rmval:dyn; correctval:??; testreg:x3;
fcsr_val:96*/
TEST_FPID_OP(fcvt.wu.d, x15, f16, dyn, 96, 0, x10, 18*FLEN/8, x14, x17, x3,FLREG)
inst_19:// rs1==f14, rd==x9,fs1 == 0 and fe1 == 0x3fb and fm1 == 0xc28f5c28f5c29 and fcsr == 0x80 and rm_val == 7
/* opcode: fcvt.wu.d ; op1:f14; dest:x9; op1val:0x3fbc28f5c28f5c29; valaddr_reg:x10;
val_offset:19*FLEN/8; rmval:dyn; correctval:??; testreg:x3;
fcsr_val:128*/
TEST_FPID_OP(fcvt.wu.d, x9, f14, dyn, 128, 0, x10, 19*FLEN/8, x14, x17, x3,FLREG)
inst_20:// rs1==f20, rd==x24,fs1 == 0 and fe1 == 0x3fe and fm1 == 0xc7ae147ae147b and fcsr == 0x0 and rm_val == 7
/* opcode: fcvt.wu.d ; op1:f20; dest:x24; op1val:0x3fec7ae147ae147b; valaddr_reg:x10;
val_offset:20*FLEN/8; rmval:dyn; correctval:??; testreg:x3;
fcsr_val:0*/
TEST_FPID_OP(fcvt.wu.d, x24, f20, dyn, 0, 0, x10, 20*FLEN/8, x14, x17, x3,FLREG)
inst_21:// rs1==f22, rd==x27,fs1 == 0 and fe1 == 0x3fe and fm1 == 0xc7ae147ae147b and fcsr == 0x20 and rm_val == 7
/* opcode: fcvt.wu.d ; op1:f22; dest:x27; op1val:0x3fec7ae147ae147b; valaddr_reg:x10;
val_offset:21*FLEN/8; rmval:dyn; correctval:??; testreg:x3;
fcsr_val:32*/
TEST_FPID_OP(fcvt.wu.d, x27, f22, dyn, 32, 0, x10, 21*FLEN/8, x14, x17, x3,FLREG)
inst_22:// rs1==f2, rd==x11,fs1 == 0 and fe1 == 0x3fe and fm1 == 0xc7ae147ae147b and fcsr == 0x40 and rm_val == 7
/* opcode: fcvt.wu.d ; op1:f2; dest:x11; op1val:0x3fec7ae147ae147b; valaddr_reg:x10;
val_offset:22*FLEN/8; rmval:dyn; correctval:??; testreg:x3;
fcsr_val:64*/
TEST_FPID_OP(fcvt.wu.d, x11, f2, dyn, 64, 0, x10, 22*FLEN/8, x14, x17, x3,FLREG)
inst_23:// rs1==f25, rd==x26,fs1 == 0 and fe1 == 0x3fe and fm1 == 0xc7ae147ae147b and fcsr == 0x60 and rm_val == 7
/* opcode: fcvt.wu.d ; op1:f25; dest:x26; op1val:0x3fec7ae147ae147b; valaddr_reg:x10;
val_offset:23*FLEN/8; rmval:dyn; correctval:??; testreg:x3;
fcsr_val:96*/
TEST_FPID_OP(fcvt.wu.d, x26, f25, dyn, 96, 0, x10, 23*FLEN/8, x14, x17, x3,FLREG)
inst_24:// rs1==f4, rd==x4,fs1 == 0 and fe1 == 0x3fe and fm1 == 0xc7ae147ae147b and fcsr == 0x80 and rm_val == 7
/* opcode: fcvt.wu.d ; op1:f4; dest:x4; op1val:0x3fec7ae147ae147b; valaddr_reg:x10;
val_offset:24*FLEN/8; rmval:dyn; correctval:??; testreg:x3;
fcsr_val:128*/
TEST_FPID_OP(fcvt.wu.d, x4, f4, dyn, 128, 0, x10, 24*FLEN/8, x14, x17, x3,FLREG)
RVTEST_VALBASEUPD(x4,test_dataset_1)
inst_25:// rs1==f30, rd==x14,fs1 == 0 and fe1 == 0x3fe and fm1 == 0xccccccccccccd and fcsr == 0x0 and rm_val == 7
/* opcode: fcvt.wu.d ; op1:f30; dest:x14; op1val:0x3feccccccccccccd; valaddr_reg:x4;
val_offset:0*FLEN/8; rmval:dyn; correctval:??; testreg:x3;
fcsr_val:0*/
TEST_FPID_OP(fcvt.wu.d, x14, f30, dyn, 0, 0, x4, 0*FLEN/8, x5, x17, x3,FLREG)
inst_26:// rs1==f23, rd==x10,fs1 == 0 and fe1 == 0x3fe and fm1 == 0xccccccccccccd and fcsr == 0x20 and rm_val == 7
/* opcode: fcvt.wu.d ; op1:f23; dest:x10; op1val:0x3feccccccccccccd; valaddr_reg:x4;
val_offset:1*FLEN/8; rmval:dyn; correctval:??; testreg:x3;
fcsr_val:32*/
TEST_FPID_OP(fcvt.wu.d, x10, f23, dyn, 32, 0, x4, 1*FLEN/8, x5, x17, x3,FLREG)
inst_27:// rs1==f15, rd==x3,fs1 == 0 and fe1 == 0x3fe and fm1 == 0xccccccccccccd and fcsr == 0x40 and rm_val == 7
/* opcode: fcvt.wu.d ; op1:f15; dest:x3; op1val:0x3feccccccccccccd; valaddr_reg:x4;
val_offset:2*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
fcsr_val:64*/
TEST_FPID_OP(fcvt.wu.d, x3, f15, dyn, 64, 0, x4, 2*FLEN/8, x5, x17, x2,FLREG)
RVTEST_SIGBASE(x1,signature_x1_0)
inst_28:// rs1==f7, rd==x17,fs1 == 0 and fe1 == 0x3fe and fm1 == 0xccccccccccccd and fcsr == 0x60 and rm_val == 7
/* opcode: fcvt.wu.d ; op1:f7; dest:x17; op1val:0x3feccccccccccccd; valaddr_reg:x4;
val_offset:3*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
fcsr_val:96*/
TEST_FPID_OP(fcvt.wu.d, x17, f7, dyn, 96, 0, x4, 3*FLEN/8, x5, x1, x2,FLREG)
inst_29:// rs1==f3, rd==x29,fs1 == 0 and fe1 == 0x3fe and fm1 == 0xccccccccccccd and fcsr == 0x80 and rm_val == 7
/* opcode: fcvt.wu.d ; op1:f3; dest:x29; op1val:0x3feccccccccccccd; valaddr_reg:x4;
val_offset:4*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
fcsr_val:128*/
TEST_FPID_OP(fcvt.wu.d, x29, f3, dyn, 128, 0, x4, 4*FLEN/8, x5, x1, x2,FLREG)
inst_30:// rs1==f26, rd==x30,fs1 == 0 and fe1 == 0x3fe and fm1 == 0xfae147ae147ae and fcsr == 0x0 and rm_val == 7
/* opcode: fcvt.wu.d ; op1:f26; dest:x30; op1val:0x3fefae147ae147ae; valaddr_reg:x4;
val_offset:5*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
fcsr_val:0*/
TEST_FPID_OP(fcvt.wu.d, x30, f26, dyn, 0, 0, x4, 5*FLEN/8, x5, x1, x2,FLREG)
inst_31:// rs1==f9, rd==x31,fs1 == 0 and fe1 == 0x3fe and fm1 == 0xfae147ae147ae and fcsr == 0x20 and rm_val == 7
/* opcode: fcvt.wu.d ; op1:f9; dest:x31; op1val:0x3fefae147ae147ae; valaddr_reg:x4;
val_offset:6*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
fcsr_val:32*/
TEST_FPID_OP(fcvt.wu.d, x31, f9, dyn, 32, 0, x4, 6*FLEN/8, x5, x1, x2,FLREG)
inst_32:// fs1 == 0 and fe1 == 0x3fe and fm1 == 0xfae147ae147ae and fcsr == 0x40 and rm_val == 7
/* opcode: fcvt.wu.d ; op1:f31; dest:x31; op1val:0x3fefae147ae147ae; valaddr_reg:x4;
val_offset:7*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
fcsr_val:64*/
TEST_FPID_OP(fcvt.wu.d, x31, f31, dyn, 64, 0, x4, 7*FLEN/8, x5, x1, x2,FLREG)
inst_33:// fs1 == 0 and fe1 == 0x3fe and fm1 == 0xfae147ae147ae and fcsr == 0x60 and rm_val == 7
/* opcode: fcvt.wu.d ; op1:f31; dest:x31; op1val:0x3fefae147ae147ae; valaddr_reg:x4;
val_offset:8*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
fcsr_val:96*/
TEST_FPID_OP(fcvt.wu.d, x31, f31, dyn, 96, 0, x4, 8*FLEN/8, x5, x1, x2,FLREG)
inst_34:// fs1 == 0 and fe1 == 0x3fe and fm1 == 0xfae147ae147ae and fcsr == 0x80 and rm_val == 7
/* opcode: fcvt.wu.d ; op1:f31; dest:x31; op1val:0x3fefae147ae147ae; valaddr_reg:x4;
val_offset:9*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
fcsr_val:128*/
TEST_FPID_OP(fcvt.wu.d, x31, f31, dyn, 128, 0, x4, 9*FLEN/8, x5, x1, x2,FLREG)
inst_35:// fs1 == 0 and fe1 == 0x3ff and fm1 == 0x0000000000000 and fcsr == 0x0 and rm_val == 7
/* opcode: fcvt.wu.d ; op1:f31; dest:x31; op1val:0x3ff0000000000000; valaddr_reg:x4;
val_offset:10*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
fcsr_val:0*/
TEST_FPID_OP(fcvt.wu.d, x31, f31, dyn, 0, 0, x4, 10*FLEN/8, x5, x1, x2,FLREG)
inst_36:// fs1 == 0 and fe1 == 0x3ff and fm1 == 0x0000000000000 and fcsr == 0x20 and rm_val == 7
/* opcode: fcvt.wu.d ; op1:f31; dest:x31; op1val:0x3ff0000000000000; valaddr_reg:x4;
val_offset:11*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
fcsr_val:32*/
TEST_FPID_OP(fcvt.wu.d, x31, f31, dyn, 32, 0, x4, 11*FLEN/8, x5, x1, x2,FLREG)
inst_37:// fs1 == 0 and fe1 == 0x3ff and fm1 == 0x0000000000000 and fcsr == 0x40 and rm_val == 7
/* opcode: fcvt.wu.d ; op1:f31; dest:x31; op1val:0x3ff0000000000000; valaddr_reg:x4;
val_offset:12*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
fcsr_val:64*/
TEST_FPID_OP(fcvt.wu.d, x31, f31, dyn, 64, 0, x4, 12*FLEN/8, x5, x1, x2,FLREG)
inst_38:// fs1 == 0 and fe1 == 0x3ff and fm1 == 0x0000000000000 and fcsr == 0x60 and rm_val == 7
/* opcode: fcvt.wu.d ; op1:f31; dest:x31; op1val:0x3ff0000000000000; valaddr_reg:x4;
val_offset:13*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
fcsr_val:96*/
TEST_FPID_OP(fcvt.wu.d, x31, f31, dyn, 96, 0, x4, 13*FLEN/8, x5, x1, x2,FLREG)
inst_39:// fs1 == 0 and fe1 == 0x3ff and fm1 == 0x0000000000000 and fcsr == 0x80 and rm_val == 7
/* opcode: fcvt.wu.d ; op1:f31; dest:x31; op1val:0x3ff0000000000000; valaddr_reg:x4;
val_offset:14*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
fcsr_val:128*/
TEST_FPID_OP(fcvt.wu.d, x31, f31, dyn, 128, 0, x4, 14*FLEN/8, x5, x1, x2,FLREG)
inst_40:// fs1 == 0 and fe1 == 0x3ff and fm1 == 0x028f5c28f5c29 and fcsr == 0x0 and rm_val == 7
/* opcode: fcvt.wu.d ; op1:f31; dest:x31; op1val:0x3ff028f5c28f5c29; valaddr_reg:x4;
val_offset:15*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
fcsr_val:0*/
TEST_FPID_OP(fcvt.wu.d, x31, f31, dyn, 0, 0, x4, 15*FLEN/8, x5, x1, x2,FLREG)
inst_41:// fs1 == 0 and fe1 == 0x3ff and fm1 == 0x028f5c28f5c29 and fcsr == 0x20 and rm_val == 7
/* opcode: fcvt.wu.d ; op1:f31; dest:x31; op1val:0x3ff028f5c28f5c29; valaddr_reg:x4;
val_offset:16*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
fcsr_val:32*/
TEST_FPID_OP(fcvt.wu.d, x31, f31, dyn, 32, 0, x4, 16*FLEN/8, x5, x1, x2,FLREG)
inst_42:// fs1 == 0 and fe1 == 0x3ff and fm1 == 0x028f5c28f5c29 and fcsr == 0x40 and rm_val == 7
/* opcode: fcvt.wu.d ; op1:f31; dest:x31; op1val:0x3ff028f5c28f5c29; valaddr_reg:x4;
val_offset:17*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
fcsr_val:64*/
TEST_FPID_OP(fcvt.wu.d, x31, f31, dyn, 64, 0, x4, 17*FLEN/8, x5, x1, x2,FLREG)
inst_43:// fs1 == 0 and fe1 == 0x3ff and fm1 == 0x028f5c28f5c29 and fcsr == 0x60 and rm_val == 7
/* opcode: fcvt.wu.d ; op1:f31; dest:x31; op1val:0x3ff028f5c28f5c29; valaddr_reg:x4;
val_offset:18*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
fcsr_val:96*/
TEST_FPID_OP(fcvt.wu.d, x31, f31, dyn, 96, 0, x4, 18*FLEN/8, x5, x1, x2,FLREG)
inst_44:// fs1 == 0 and fe1 == 0x3ff and fm1 == 0x028f5c28f5c29 and fcsr == 0x80 and rm_val == 7
/* opcode: fcvt.wu.d ; op1:f31; dest:x31; op1val:0x3ff028f5c28f5c29; valaddr_reg:x4;
val_offset:19*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
fcsr_val:128*/
TEST_FPID_OP(fcvt.wu.d, x31, f31, dyn, 128, 0, x4, 19*FLEN/8, x5, x1, x2,FLREG)
inst_45:// fs1 == 0 and fe1 == 0x3ff and fm1 == 0x199999999999a and fcsr == 0x0 and rm_val == 7
/* opcode: fcvt.wu.d ; op1:f31; dest:x31; op1val:0x3ff199999999999a; valaddr_reg:x4;
val_offset:20*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
fcsr_val:0*/
TEST_FPID_OP(fcvt.wu.d, x31, f31, dyn, 0, 0, x4, 20*FLEN/8, x5, x1, x2,FLREG)
inst_46:// fs1 == 0 and fe1 == 0x3ff and fm1 == 0x199999999999a and fcsr == 0x20 and rm_val == 7
/* opcode: fcvt.wu.d ; op1:f31; dest:x31; op1val:0x3ff199999999999a; valaddr_reg:x4;
val_offset:21*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
fcsr_val:32*/
TEST_FPID_OP(fcvt.wu.d, x31, f31, dyn, 32, 0, x4, 21*FLEN/8, x5, x1, x2,FLREG)
inst_47:// fs1 == 0 and fe1 == 0x3ff and fm1 == 0x199999999999a and fcsr == 0x40 and rm_val == 7
/* opcode: fcvt.wu.d ; op1:f31; dest:x31; op1val:0x3ff199999999999a; valaddr_reg:x4;
val_offset:22*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
fcsr_val:64*/
TEST_FPID_OP(fcvt.wu.d, x31, f31, dyn, 64, 0, x4, 22*FLEN/8, x5, x1, x2,FLREG)
inst_48:// fs1 == 0 and fe1 == 0x3ff and fm1 == 0x199999999999a and fcsr == 0x60 and rm_val == 7
/* opcode: fcvt.wu.d ; op1:f31; dest:x31; op1val:0x3ff199999999999a; valaddr_reg:x4;
val_offset:23*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
fcsr_val:96*/
TEST_FPID_OP(fcvt.wu.d, x31, f31, dyn, 96, 0, x4, 23*FLEN/8, x5, x1, x2,FLREG)
inst_49:// fs1 == 0 and fe1 == 0x3ff and fm1 == 0x199999999999a and fcsr == 0x80 and rm_val == 7
/* opcode: fcvt.wu.d ; op1:f31; dest:x31; op1val:0x3ff199999999999a; valaddr_reg:x4;
val_offset:24*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
fcsr_val:128*/
TEST_FPID_OP(fcvt.wu.d, x31, f31, dyn, 128, 0, x4, 24*FLEN/8, x5, x1, x2,FLREG)
inst_50:// fs1 == 0 and fe1 == 0x3ff and fm1 == 0x1c28f5c28f5c3 and fcsr == 0x0 and rm_val == 7
/* opcode: fcvt.wu.d ; op1:f31; dest:x31; op1val:0x3ff1c28f5c28f5c3; valaddr_reg:x4;
val_offset:25*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
fcsr_val:0*/
TEST_FPID_OP(fcvt.wu.d, x31, f31, dyn, 0, 0, x4, 25*FLEN/8, x5, x1, x2,FLREG)
inst_51:// fs1 == 0 and fe1 == 0x3ff and fm1 == 0x1c28f5c28f5c3 and fcsr == 0x20 and rm_val == 7
/* opcode: fcvt.wu.d ; op1:f31; dest:x31; op1val:0x3ff1c28f5c28f5c3; valaddr_reg:x4;
val_offset:26*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
fcsr_val:32*/
TEST_FPID_OP(fcvt.wu.d, x31, f31, dyn, 32, 0, x4, 26*FLEN/8, x5, x1, x2,FLREG)
inst_52:// fs1 == 0 and fe1 == 0x3ff and fm1 == 0x1c28f5c28f5c3 and fcsr == 0x40 and rm_val == 7
/* opcode: fcvt.wu.d ; op1:f31; dest:x31; op1val:0x3ff1c28f5c28f5c3; valaddr_reg:x4;
val_offset:27*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
fcsr_val:64*/
TEST_FPID_OP(fcvt.wu.d, x31, f31, dyn, 64, 0, x4, 27*FLEN/8, x5, x1, x2,FLREG)
inst_53:// fs1 == 0 and fe1 == 0x3ff and fm1 == 0x1c28f5c28f5c3 and fcsr == 0x60 and rm_val == 7
/* opcode: fcvt.wu.d ; op1:f31; dest:x31; op1val:0x3ff1c28f5c28f5c3; valaddr_reg:x4;
val_offset:28*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
fcsr_val:96*/
TEST_FPID_OP(fcvt.wu.d, x31, f31, dyn, 96, 0, x4, 28*FLEN/8, x5, x1, x2,FLREG)
inst_54:// fs1 == 0 and fe1 == 0x3ff and fm1 == 0x1c28f5c28f5c3 and fcsr == 0x80 and rm_val == 7
/* opcode: fcvt.wu.d ; op1:f31; dest:x31; op1val:0x3ff1c28f5c28f5c3; valaddr_reg:x4;
val_offset:29*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
fcsr_val:128*/
TEST_FPID_OP(fcvt.wu.d, x31, f31, dyn, 128, 0, x4, 29*FLEN/8, x5, x1, x2,FLREG)
inst_55:// fs1 == 1 and fe1 == 0x3f8 and fm1 == 0x47ae147ae147b and fcsr == 0x0 and rm_val == 7
/* opcode: fcvt.wu.d ; op1:f31; dest:x31; op1val:0xbf847ae147ae147b; valaddr_reg:x4;
val_offset:30*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
fcsr_val:0*/
TEST_FPID_OP(fcvt.wu.d, x31, f31, dyn, 0, 0, x4, 30*FLEN/8, x5, x1, x2,FLREG)
inst_56:// fs1 == 1 and fe1 == 0x3f8 and fm1 == 0x47ae147ae147b and fcsr == 0x20 and rm_val == 7
/* opcode: fcvt.wu.d ; op1:f31; dest:x31; op1val:0xbf847ae147ae147b; valaddr_reg:x4;
val_offset:31*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
fcsr_val:32*/
TEST_FPID_OP(fcvt.wu.d, x31, f31, dyn, 32, 0, x4, 31*FLEN/8, x5, x1, x2,FLREG)
inst_57:// fs1 == 1 and fe1 == 0x3f8 and fm1 == 0x47ae147ae147b and fcsr == 0x40 and rm_val == 7
/* opcode: fcvt.wu.d ; op1:f31; dest:x31; op1val:0xbf847ae147ae147b; valaddr_reg:x4;
val_offset:32*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
fcsr_val:64*/
TEST_FPID_OP(fcvt.wu.d, x31, f31, dyn, 64, 0, x4, 32*FLEN/8, x5, x1, x2,FLREG)
inst_58:// fs1 == 1 and fe1 == 0x3f8 and fm1 == 0x47ae147ae147b and fcsr == 0x60 and rm_val == 7
/* opcode: fcvt.wu.d ; op1:f31; dest:x31; op1val:0xbf847ae147ae147b; valaddr_reg:x4;
val_offset:33*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
fcsr_val:96*/
TEST_FPID_OP(fcvt.wu.d, x31, f31, dyn, 96, 0, x4, 33*FLEN/8, x5, x1, x2,FLREG)
inst_59:// fs1 == 1 and fe1 == 0x3f8 and fm1 == 0x47ae147ae147b and fcsr == 0x80 and rm_val == 7
/* opcode: fcvt.wu.d ; op1:f31; dest:x31; op1val:0xbf847ae147ae147b; valaddr_reg:x4;
val_offset:34*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
fcsr_val:128*/
TEST_FPID_OP(fcvt.wu.d, x31, f31, dyn, 128, 0, x4, 34*FLEN/8, x5, x1, x2,FLREG)
inst_60:// fs1 == 1 and fe1 == 0x3fb and fm1 == 0x999999999999a and fcsr == 0x0 and rm_val == 7
/* opcode: fcvt.wu.d ; op1:f31; dest:x31; op1val:0xbfb999999999999a; valaddr_reg:x4;
val_offset:35*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
fcsr_val:0*/
TEST_FPID_OP(fcvt.wu.d, x31, f31, dyn, 0, 0, x4, 35*FLEN/8, x5, x1, x2,FLREG)
inst_61:// fs1 == 1 and fe1 == 0x3fb and fm1 == 0x999999999999a and fcsr == 0x20 and rm_val == 7
/* opcode: fcvt.wu.d ; op1:f31; dest:x31; op1val:0xbfb999999999999a; valaddr_reg:x4;
val_offset:36*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
fcsr_val:32*/
TEST_FPID_OP(fcvt.wu.d, x31, f31, dyn, 32, 0, x4, 36*FLEN/8, x5, x1, x2,FLREG)
inst_62:// fs1 == 1 and fe1 == 0x3fb and fm1 == 0x999999999999a and fcsr == 0x40 and rm_val == 7
/* opcode: fcvt.wu.d ; op1:f31; dest:x31; op1val:0xbfb999999999999a; valaddr_reg:x4;
val_offset:37*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
fcsr_val:64*/
TEST_FPID_OP(fcvt.wu.d, x31, f31, dyn, 64, 0, x4, 37*FLEN/8, x5, x1, x2,FLREG)
inst_63:// fs1 == 1 and fe1 == 0x3fb and fm1 == 0x999999999999a and fcsr == 0x60 and rm_val == 7
/* opcode: fcvt.wu.d ; op1:f31; dest:x31; op1val:0xbfb999999999999a; valaddr_reg:x4;
val_offset:38*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
fcsr_val:96*/
TEST_FPID_OP(fcvt.wu.d, x31, f31, dyn, 96, 0, x4, 38*FLEN/8, x5, x1, x2,FLREG)
inst_64:// fs1 == 1 and fe1 == 0x3fb and fm1 == 0x999999999999a and fcsr == 0x80 and rm_val == 7
/* opcode: fcvt.wu.d ; op1:f31; dest:x31; op1val:0xbfb999999999999a; valaddr_reg:x4;
val_offset:39*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
fcsr_val:128*/
TEST_FPID_OP(fcvt.wu.d, x31, f31, dyn, 128, 0, x4, 39*FLEN/8, x5, x1, x2,FLREG)
inst_65:// fs1 == 1 and fe1 == 0x3fb and fm1 == 0xc28f5c28f5c29 and fcsr == 0x0 and rm_val == 7
/* opcode: fcvt.wu.d ; op1:f31; dest:x31; op1val:0xbfbc28f5c28f5c29; valaddr_reg:x4;
val_offset:40*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
fcsr_val:0*/
TEST_FPID_OP(fcvt.wu.d, x31, f31, dyn, 0, 0, x4, 40*FLEN/8, x5, x1, x2,FLREG)
inst_66:// fs1 == 1 and fe1 == 0x3fb and fm1 == 0xc28f5c28f5c29 and fcsr == 0x20 and rm_val == 7
/* opcode: fcvt.wu.d ; op1:f31; dest:x31; op1val:0xbfbc28f5c28f5c29; valaddr_reg:x4;
val_offset:41*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
fcsr_val:32*/
TEST_FPID_OP(fcvt.wu.d, x31, f31, dyn, 32, 0, x4, 41*FLEN/8, x5, x1, x2,FLREG)
inst_67:// fs1 == 1 and fe1 == 0x3fb and fm1 == 0xc28f5c28f5c29 and fcsr == 0x40 and rm_val == 7
/* opcode: fcvt.wu.d ; op1:f31; dest:x31; op1val:0xbfbc28f5c28f5c29; valaddr_reg:x4;
val_offset:42*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
fcsr_val:64*/
TEST_FPID_OP(fcvt.wu.d, x31, f31, dyn, 64, 0, x4, 42*FLEN/8, x5, x1, x2,FLREG)
inst_68:// fs1 == 1 and fe1 == 0x3fb and fm1 == 0xc28f5c28f5c29 and fcsr == 0x60 and rm_val == 7
/* opcode: fcvt.wu.d ; op1:f31; dest:x31; op1val:0xbfbc28f5c28f5c29; valaddr_reg:x4;
val_offset:43*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
fcsr_val:96*/
TEST_FPID_OP(fcvt.wu.d, x31, f31, dyn, 96, 0, x4, 43*FLEN/8, x5, x1, x2,FLREG)
inst_69:// fs1 == 1 and fe1 == 0x3fb and fm1 == 0xc28f5c28f5c29 and fcsr == 0x80 and rm_val == 7
/* opcode: fcvt.wu.d ; op1:f31; dest:x31; op1val:0xbfbc28f5c28f5c29; valaddr_reg:x4;
val_offset:44*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
fcsr_val:128*/
TEST_FPID_OP(fcvt.wu.d, x31, f31, dyn, 128, 0, x4, 44*FLEN/8, x5, x1, x2,FLREG)
inst_70:// fs1 == 1 and fe1 == 0x3fe and fm1 == 0xc7ae147ae147b and fcsr == 0x0 and rm_val == 7
/* opcode: fcvt.wu.d ; op1:f31; dest:x31; op1val:0xbfec7ae147ae147b; valaddr_reg:x4;
val_offset:45*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
fcsr_val:0*/
TEST_FPID_OP(fcvt.wu.d, x31, f31, dyn, 0, 0, x4, 45*FLEN/8, x5, x1, x2,FLREG)
inst_71:// fs1 == 1 and fe1 == 0x3fe and fm1 == 0xc7ae147ae147b and fcsr == 0x20 and rm_val == 7
/* opcode: fcvt.wu.d ; op1:f31; dest:x31; op1val:0xbfec7ae147ae147b; valaddr_reg:x4;
val_offset:46*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
fcsr_val:32*/
TEST_FPID_OP(fcvt.wu.d, x31, f31, dyn, 32, 0, x4, 46*FLEN/8, x5, x1, x2,FLREG)
inst_72:// fs1 == 1 and fe1 == 0x3fe and fm1 == 0xc7ae147ae147b and fcsr == 0x40 and rm_val == 7
/* opcode: fcvt.wu.d ; op1:f31; dest:x31; op1val:0xbfec7ae147ae147b; valaddr_reg:x4;
val_offset:47*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
fcsr_val:64*/
TEST_FPID_OP(fcvt.wu.d, x31, f31, dyn, 64, 0, x4, 47*FLEN/8, x5, x1, x2,FLREG)
inst_73:// fs1 == 1 and fe1 == 0x3fe and fm1 == 0xc7ae147ae147b and fcsr == 0x60 and rm_val == 7
/* opcode: fcvt.wu.d ; op1:f31; dest:x31; op1val:0xbfec7ae147ae147b; valaddr_reg:x4;
val_offset:48*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
fcsr_val:96*/
TEST_FPID_OP(fcvt.wu.d, x31, f31, dyn, 96, 0, x4, 48*FLEN/8, x5, x1, x2,FLREG)
inst_74:// fs1 == 1 and fe1 == 0x3fe and fm1 == 0xc7ae147ae147b and fcsr == 0x80 and rm_val == 7
/* opcode: fcvt.wu.d ; op1:f31; dest:x31; op1val:0xbfec7ae147ae147b; valaddr_reg:x4;
val_offset:49*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
fcsr_val:128*/
TEST_FPID_OP(fcvt.wu.d, x31, f31, dyn, 128, 0, x4, 49*FLEN/8, x5, x1, x2,FLREG)
inst_75:// fs1 == 1 and fe1 == 0x3fe and fm1 == 0xccccccccccccd and fcsr == 0x0 and rm_val == 7
/* opcode: fcvt.wu.d ; op1:f31; dest:x31; op1val:0xbfeccccccccccccd; valaddr_reg:x4;
val_offset:50*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
fcsr_val:0*/
TEST_FPID_OP(fcvt.wu.d, x31, f31, dyn, 0, 0, x4, 50*FLEN/8, x5, x1, x2,FLREG)
inst_76:// fs1 == 1 and fe1 == 0x3fe and fm1 == 0xccccccccccccd and fcsr == 0x20 and rm_val == 7
/* opcode: fcvt.wu.d ; op1:f31; dest:x31; op1val:0xbfeccccccccccccd; valaddr_reg:x4;
val_offset:51*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
fcsr_val:32*/
TEST_FPID_OP(fcvt.wu.d, x31, f31, dyn, 32, 0, x4, 51*FLEN/8, x5, x1, x2,FLREG)
inst_77:// fs1 == 1 and fe1 == 0x3fe and fm1 == 0xccccccccccccd and fcsr == 0x40 and rm_val == 7
/* opcode: fcvt.wu.d ; op1:f31; dest:x31; op1val:0xbfeccccccccccccd; valaddr_reg:x4;
val_offset:52*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
fcsr_val:64*/
TEST_FPID_OP(fcvt.wu.d, x31, f31, dyn, 64, 0, x4, 52*FLEN/8, x5, x1, x2,FLREG)
inst_78:// fs1 == 1 and fe1 == 0x3fe and fm1 == 0xccccccccccccd and fcsr == 0x60 and rm_val == 7
/* opcode: fcvt.wu.d ; op1:f31; dest:x31; op1val:0xbfeccccccccccccd; valaddr_reg:x4;
val_offset:53*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
fcsr_val:96*/
TEST_FPID_OP(fcvt.wu.d, x31, f31, dyn, 96, 0, x4, 53*FLEN/8, x5, x1, x2,FLREG)
inst_79:// fs1 == 1 and fe1 == 0x3fe and fm1 == 0xccccccccccccd and fcsr == 0x80 and rm_val == 7
/* opcode: fcvt.wu.d ; op1:f31; dest:x31; op1val:0xbfeccccccccccccd; valaddr_reg:x4;
val_offset:54*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
fcsr_val:128*/
TEST_FPID_OP(fcvt.wu.d, x31, f31, dyn, 128, 0, x4, 54*FLEN/8, x5, x1, x2,FLREG)
inst_80:// fs1 == 1 and fe1 == 0x3fe and fm1 == 0xfae147ae147ae and fcsr == 0x0 and rm_val == 7
/* opcode: fcvt.wu.d ; op1:f31; dest:x31; op1val:0xbfefae147ae147ae; valaddr_reg:x4;
val_offset:55*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
fcsr_val:0*/
TEST_FPID_OP(fcvt.wu.d, x31, f31, dyn, 0, 0, x4, 55*FLEN/8, x5, x1, x2,FLREG)
inst_81:// fs1 == 1 and fe1 == 0x3fe and fm1 == 0xfae147ae147ae and fcsr == 0x20 and rm_val == 7
/* opcode: fcvt.wu.d ; op1:f31; dest:x31; op1val:0xbfefae147ae147ae; valaddr_reg:x4;
val_offset:56*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
fcsr_val:32*/
TEST_FPID_OP(fcvt.wu.d, x31, f31, dyn, 32, 0, x4, 56*FLEN/8, x5, x1, x2,FLREG)
inst_82:// fs1 == 1 and fe1 == 0x3fe and fm1 == 0xfae147ae147ae and fcsr == 0x40 and rm_val == 7
/* opcode: fcvt.wu.d ; op1:f31; dest:x31; op1val:0xbfefae147ae147ae; valaddr_reg:x4;
val_offset:57*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
fcsr_val:64*/
TEST_FPID_OP(fcvt.wu.d, x31, f31, dyn, 64, 0, x4, 57*FLEN/8, x5, x1, x2,FLREG)
inst_83:// fs1 == 1 and fe1 == 0x3fe and fm1 == 0xfae147ae147ae and fcsr == 0x60 and rm_val == 7
/* opcode: fcvt.wu.d ; op1:f31; dest:x31; op1val:0xbfefae147ae147ae; valaddr_reg:x4;
val_offset:58*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
fcsr_val:96*/
TEST_FPID_OP(fcvt.wu.d, x31, f31, dyn, 96, 0, x4, 58*FLEN/8, x5, x1, x2,FLREG)
inst_84:// fs1 == 1 and fe1 == 0x3fe and fm1 == 0xfae147ae147ae and fcsr == 0x80 and rm_val == 7
/* opcode: fcvt.wu.d ; op1:f31; dest:x31; op1val:0xbfefae147ae147ae; valaddr_reg:x4;
val_offset:59*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
fcsr_val:128*/
TEST_FPID_OP(fcvt.wu.d, x31, f31, dyn, 128, 0, x4, 59*FLEN/8, x5, x1, x2,FLREG)
inst_85:// fs1 == 1 and fe1 == 0x3ff and fm1 == 0x0000000000000 and fcsr == 0x0 and rm_val == 7
/* opcode: fcvt.wu.d ; op1:f31; dest:x31; op1val:0xbff0000000000000; valaddr_reg:x4;
val_offset:60*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
fcsr_val:0*/
TEST_FPID_OP(fcvt.wu.d, x31, f31, dyn, 0, 0, x4, 60*FLEN/8, x5, x1, x2,FLREG)
inst_86:// fs1 == 1 and fe1 == 0x3ff and fm1 == 0x0000000000000 and fcsr == 0x20 and rm_val == 7
/* opcode: fcvt.wu.d ; op1:f31; dest:x31; op1val:0xbff0000000000000; valaddr_reg:x4;
val_offset:61*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
fcsr_val:32*/
TEST_FPID_OP(fcvt.wu.d, x31, f31, dyn, 32, 0, x4, 61*FLEN/8, x5, x1, x2,FLREG)
inst_87:// fs1 == 1 and fe1 == 0x3ff and fm1 == 0x0000000000000 and fcsr == 0x40 and rm_val == 7
/* opcode: fcvt.wu.d ; op1:f31; dest:x31; op1val:0xbff0000000000000; valaddr_reg:x4;
val_offset:62*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
fcsr_val:64*/
TEST_FPID_OP(fcvt.wu.d, x31, f31, dyn, 64, 0, x4, 62*FLEN/8, x5, x1, x2,FLREG)
inst_88:// fs1 == 1 and fe1 == 0x3ff and fm1 == 0x0000000000000 and fcsr == 0x60 and rm_val == 7
/* opcode: fcvt.wu.d ; op1:f31; dest:x31; op1val:0xbff0000000000000; valaddr_reg:x4;
val_offset:63*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
fcsr_val:96*/
TEST_FPID_OP(fcvt.wu.d, x31, f31, dyn, 96, 0, x4, 63*FLEN/8, x5, x1, x2,FLREG)
inst_89:// fs1 == 1 and fe1 == 0x3ff and fm1 == 0x0000000000000 and fcsr == 0x80 and rm_val == 7
/* opcode: fcvt.wu.d ; op1:f31; dest:x31; op1val:0xbff0000000000000; valaddr_reg:x4;
val_offset:64*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
fcsr_val:128*/
TEST_FPID_OP(fcvt.wu.d, x31, f31, dyn, 128, 0, x4, 64*FLEN/8, x5, x1, x2,FLREG)
inst_90:// fs1 == 1 and fe1 == 0x3ff and fm1 == 0x028f5c28f5c29 and fcsr == 0x0 and rm_val == 7
/* opcode: fcvt.wu.d ; op1:f31; dest:x31; op1val:0xbff028f5c28f5c29; valaddr_reg:x4;
val_offset:65*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
fcsr_val:0*/
TEST_FPID_OP(fcvt.wu.d, x31, f31, dyn, 0, 0, x4, 65*FLEN/8, x5, x1, x2,FLREG)
inst_91:// fs1 == 1 and fe1 == 0x3ff and fm1 == 0x028f5c28f5c29 and fcsr == 0x20 and rm_val == 7
/* opcode: fcvt.wu.d ; op1:f31; dest:x31; op1val:0xbff028f5c28f5c29; valaddr_reg:x4;
val_offset:66*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
fcsr_val:32*/
TEST_FPID_OP(fcvt.wu.d, x31, f31, dyn, 32, 0, x4, 66*FLEN/8, x5, x1, x2,FLREG)
inst_92:// fs1 == 1 and fe1 == 0x3ff and fm1 == 0x028f5c28f5c29 and fcsr == 0x40 and rm_val == 7
/* opcode: fcvt.wu.d ; op1:f31; dest:x31; op1val:0xbff028f5c28f5c29; valaddr_reg:x4;
val_offset:67*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
fcsr_val:64*/
TEST_FPID_OP(fcvt.wu.d, x31, f31, dyn, 64, 0, x4, 67*FLEN/8, x5, x1, x2,FLREG)
inst_93:// fs1 == 1 and fe1 == 0x3ff and fm1 == 0x028f5c28f5c29 and fcsr == 0x60 and rm_val == 7
/* opcode: fcvt.wu.d ; op1:f31; dest:x31; op1val:0xbff028f5c28f5c29; valaddr_reg:x4;
val_offset:68*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
fcsr_val:96*/
TEST_FPID_OP(fcvt.wu.d, x31, f31, dyn, 96, 0, x4, 68*FLEN/8, x5, x1, x2,FLREG)
inst_94:// fs1 == 1 and fe1 == 0x3ff and fm1 == 0x028f5c28f5c29 and fcsr == 0x80 and rm_val == 7
/* opcode: fcvt.wu.d ; op1:f31; dest:x31; op1val:0xbff028f5c28f5c29; valaddr_reg:x4;
val_offset:69*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
fcsr_val:128*/
TEST_FPID_OP(fcvt.wu.d, x31, f31, dyn, 128, 0, x4, 69*FLEN/8, x5, x1, x2,FLREG)
inst_95:// fs1 == 1 and fe1 == 0x3ff and fm1 == 0x199999999999a and fcsr == 0x0 and rm_val == 7
/* opcode: fcvt.wu.d ; op1:f31; dest:x31; op1val:0xbff199999999999a; valaddr_reg:x4;
val_offset:70*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
fcsr_val:0*/
TEST_FPID_OP(fcvt.wu.d, x31, f31, dyn, 0, 0, x4, 70*FLEN/8, x5, x1, x2,FLREG)
inst_96:// fs1 == 1 and fe1 == 0x3ff and fm1 == 0x199999999999a and fcsr == 0x20 and rm_val == 7
/* opcode: fcvt.wu.d ; op1:f31; dest:x31; op1val:0xbff199999999999a; valaddr_reg:x4;
val_offset:71*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
fcsr_val:32*/
TEST_FPID_OP(fcvt.wu.d, x31, f31, dyn, 32, 0, x4, 71*FLEN/8, x5, x1, x2,FLREG)
inst_97:// fs1 == 1 and fe1 == 0x3ff and fm1 == 0x199999999999a and fcsr == 0x40 and rm_val == 7
/* opcode: fcvt.wu.d ; op1:f31; dest:x31; op1val:0xbff199999999999a; valaddr_reg:x4;
val_offset:72*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
fcsr_val:64*/
TEST_FPID_OP(fcvt.wu.d, x31, f31, dyn, 64, 0, x4, 72*FLEN/8, x5, x1, x2,FLREG)
inst_98:// fs1 == 1 and fe1 == 0x3ff and fm1 == 0x199999999999a and fcsr == 0x60 and rm_val == 7
/* opcode: fcvt.wu.d ; op1:f31; dest:x31; op1val:0xbff199999999999a; valaddr_reg:x4;
val_offset:73*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
fcsr_val:96*/
TEST_FPID_OP(fcvt.wu.d, x31, f31, dyn, 96, 0, x4, 73*FLEN/8, x5, x1, x2,FLREG)
inst_99:// fs1 == 1 and fe1 == 0x3ff and fm1 == 0x199999999999a and fcsr == 0x80 and rm_val == 7
/* opcode: fcvt.wu.d ; op1:f31; dest:x31; op1val:0xbff199999999999a; valaddr_reg:x4;
val_offset:74*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
fcsr_val:128*/
TEST_FPID_OP(fcvt.wu.d, x31, f31, dyn, 128, 0, x4, 74*FLEN/8, x5, x1, x2,FLREG)
inst_100:// fs1 == 1 and fe1 == 0x3ff and fm1 == 0x1c28f5c28f5c3 and fcsr == 0x0 and rm_val == 7
/* opcode: fcvt.wu.d ; op1:f31; dest:x31; op1val:0xbff1c28f5c28f5c3; valaddr_reg:x4;
val_offset:75*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
fcsr_val:0*/
TEST_FPID_OP(fcvt.wu.d, x31, f31, dyn, 0, 0, x4, 75*FLEN/8, x5, x1, x2,FLREG)
inst_101:// fs1 == 1 and fe1 == 0x3ff and fm1 == 0x1c28f5c28f5c3 and fcsr == 0x20 and rm_val == 7
/* opcode: fcvt.wu.d ; op1:f31; dest:x31; op1val:0xbff1c28f5c28f5c3; valaddr_reg:x4;
val_offset:76*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
fcsr_val:32*/
TEST_FPID_OP(fcvt.wu.d, x31, f31, dyn, 32, 0, x4, 76*FLEN/8, x5, x1, x2,FLREG)
inst_102:// fs1 == 1 and fe1 == 0x3ff and fm1 == 0x1c28f5c28f5c3 and fcsr == 0x40 and rm_val == 7
/* opcode: fcvt.wu.d ; op1:f31; dest:x31; op1val:0xbff1c28f5c28f5c3; valaddr_reg:x4;
val_offset:77*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
fcsr_val:64*/
TEST_FPID_OP(fcvt.wu.d, x31, f31, dyn, 64, 0, x4, 77*FLEN/8, x5, x1, x2,FLREG)
inst_103:// fs1 == 1 and fe1 == 0x3ff and fm1 == 0x1c28f5c28f5c3 and fcsr == 0x60 and rm_val == 7
/* opcode: fcvt.wu.d ; op1:f31; dest:x31; op1val:0xbff1c28f5c28f5c3; valaddr_reg:x4;
val_offset:78*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
fcsr_val:96*/
TEST_FPID_OP(fcvt.wu.d, x31, f31, dyn, 96, 0, x4, 78*FLEN/8, x5, x1, x2,FLREG)
inst_104:// fs1 == 1 and fe1 == 0x3ff and fm1 == 0x1c28f5c28f5c3 and fcsr == 0x80 and rm_val == 7
/* opcode: fcvt.wu.d ; op1:f31; dest:x31; op1val:0xbff1c28f5c28f5c3; valaddr_reg:x4;
val_offset:79*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
fcsr_val:128*/
TEST_FPID_OP(fcvt.wu.d, x31, f31, dyn, 128, 0, x4, 79*FLEN/8, x5, x1, x2,FLREG)
inst_105:// fs1 == 0 and fe1 == 0x3fb and fm1 == 0xc28f5c28f5c29 and fcsr == 0x40 and rm_val == 7
/* opcode: fcvt.wu.d ; op1:f31; dest:x31; op1val:0x3fbc28f5c28f5c29; valaddr_reg:x4;
val_offset:80*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
fcsr_val:64*/
TEST_FPID_OP(fcvt.wu.d, x31, f31, dyn, 64, 0, x4, 80*FLEN/8, x5, x1, x2,FLREG)
#endif
RVTEST_CODE_END
RVMODEL_HALT
RVTEST_DATA_BEGIN
.align 4
rvtest_data:
.word 0xbabecafe
.word 0xabecafeb
.word 0xbecafeba
.word 0xecafebab
test_dataset_0:
NAN_BOXED(0,64,FLEN)
NAN_BOXED(0,64,FLEN)
NAN_BOXED(0,64,FLEN)
NAN_BOXED(0,64,FLEN)
NAN_BOXED(0,64,FLEN)
NAN_BOXED(4576918229304087675,64,FLEN)
NAN_BOXED(4576918229304087675,64,FLEN)
NAN_BOXED(4576918229304087675,64,FLEN)
NAN_BOXED(4576918229304087675,64,FLEN)
NAN_BOXED(4576918229304087675,64,FLEN)
NAN_BOXED(4591870180066957722,64,FLEN)
NAN_BOXED(4591870180066957722,64,FLEN)
NAN_BOXED(4591870180066957722,64,FLEN)
NAN_BOXED(4591870180066957722,64,FLEN)
NAN_BOXED(4591870180066957722,64,FLEN)
NAN_BOXED(4592590756007337001,64,FLEN)
NAN_BOXED(4592590756007337001,64,FLEN)
NAN_BOXED(4592590756007337001,64,FLEN)
NAN_BOXED(4592590756007337001,64,FLEN)
NAN_BOXED(4592590756007337001,64,FLEN)
NAN_BOXED(4606191626881995899,64,FLEN)
NAN_BOXED(4606191626881995899,64,FLEN)
NAN_BOXED(4606191626881995899,64,FLEN)
NAN_BOXED(4606191626881995899,64,FLEN)
NAN_BOXED(4606191626881995899,64,FLEN)
test_dataset_1:
NAN_BOXED(4606281698874543309,64,FLEN)
NAN_BOXED(4606281698874543309,64,FLEN)
NAN_BOXED(4606281698874543309,64,FLEN)
NAN_BOXED(4606281698874543309,64,FLEN)
NAN_BOXED(4606281698874543309,64,FLEN)
NAN_BOXED(4607092346807469998,64,FLEN)
NAN_BOXED(4607092346807469998,64,FLEN)
NAN_BOXED(4607092346807469998,64,FLEN)
NAN_BOXED(4607092346807469998,64,FLEN)
NAN_BOXED(4607092346807469998,64,FLEN)
NAN_BOXED(4607182418800017408,64,FLEN)
NAN_BOXED(4607182418800017408,64,FLEN)
NAN_BOXED(4607182418800017408,64,FLEN)
NAN_BOXED(4607182418800017408,64,FLEN)
NAN_BOXED(4607182418800017408,64,FLEN)
NAN_BOXED(4607227454796291113,64,FLEN)
NAN_BOXED(4607227454796291113,64,FLEN)
NAN_BOXED(4607227454796291113,64,FLEN)
NAN_BOXED(4607227454796291113,64,FLEN)
NAN_BOXED(4607227454796291113,64,FLEN)
NAN_BOXED(4607632778762754458,64,FLEN)
NAN_BOXED(4607632778762754458,64,FLEN)
NAN_BOXED(4607632778762754458,64,FLEN)
NAN_BOXED(4607632778762754458,64,FLEN)
NAN_BOXED(4607632778762754458,64,FLEN)
NAN_BOXED(4607677814759028163,64,FLEN)
NAN_BOXED(4607677814759028163,64,FLEN)
NAN_BOXED(4607677814759028163,64,FLEN)
NAN_BOXED(4607677814759028163,64,FLEN)
NAN_BOXED(4607677814759028163,64,FLEN)
NAN_BOXED(13800290266158863483,64,FLEN)
NAN_BOXED(13800290266158863483,64,FLEN)
NAN_BOXED(13800290266158863483,64,FLEN)
NAN_BOXED(13800290266158863483,64,FLEN)
NAN_BOXED(13800290266158863483,64,FLEN)
NAN_BOXED(13815242216921733530,64,FLEN)
NAN_BOXED(13815242216921733530,64,FLEN)
NAN_BOXED(13815242216921733530,64,FLEN)
NAN_BOXED(13815242216921733530,64,FLEN)
NAN_BOXED(13815242216921733530,64,FLEN)
NAN_BOXED(13815962792862112809,64,FLEN)
NAN_BOXED(13815962792862112809,64,FLEN)
NAN_BOXED(13815962792862112809,64,FLEN)
NAN_BOXED(13815962792862112809,64,FLEN)
NAN_BOXED(13815962792862112809,64,FLEN)
NAN_BOXED(13829563663736771707,64,FLEN)
NAN_BOXED(13829563663736771707,64,FLEN)
NAN_BOXED(13829563663736771707,64,FLEN)
NAN_BOXED(13829563663736771707,64,FLEN)
NAN_BOXED(13829563663736771707,64,FLEN)
NAN_BOXED(13829653735729319117,64,FLEN)
NAN_BOXED(13829653735729319117,64,FLEN)
NAN_BOXED(13829653735729319117,64,FLEN)
NAN_BOXED(13829653735729319117,64,FLEN)
NAN_BOXED(13829653735729319117,64,FLEN)
NAN_BOXED(13830464383662245806,64,FLEN)
NAN_BOXED(13830464383662245806,64,FLEN)
NAN_BOXED(13830464383662245806,64,FLEN)
NAN_BOXED(13830464383662245806,64,FLEN)
NAN_BOXED(13830464383662245806,64,FLEN)
NAN_BOXED(13830554455654793216,64,FLEN)
NAN_BOXED(13830554455654793216,64,FLEN)
NAN_BOXED(13830554455654793216,64,FLEN)
NAN_BOXED(13830554455654793216,64,FLEN)
NAN_BOXED(13830554455654793216,64,FLEN)
NAN_BOXED(13830599491651066921,64,FLEN)
NAN_BOXED(13830599491651066921,64,FLEN)
NAN_BOXED(13830599491651066921,64,FLEN)
NAN_BOXED(13830599491651066921,64,FLEN)
NAN_BOXED(13830599491651066921,64,FLEN)
NAN_BOXED(13831004815617530266,64,FLEN)
NAN_BOXED(13831004815617530266,64,FLEN)
NAN_BOXED(13831004815617530266,64,FLEN)
NAN_BOXED(13831004815617530266,64,FLEN)
NAN_BOXED(13831004815617530266,64,FLEN)
NAN_BOXED(13831049851613803971,64,FLEN)
NAN_BOXED(13831049851613803971,64,FLEN)
NAN_BOXED(13831049851613803971,64,FLEN)
NAN_BOXED(13831049851613803971,64,FLEN)
NAN_BOXED(13831049851613803971,64,FLEN)
NAN_BOXED(4592590756007337001,64,FLEN)
RVTEST_DATA_END
RVMODEL_DATA_BEGIN
rvtest_sig_begin:
sig_begin_canary:
CANARY;
signature_x17_0:
.fill 0*((SIGALIGN)/4),4,0xdeadbeef
signature_x17_1:
.fill 56*((SIGALIGN)/4),4,0xdeadbeef
signature_x1_0:
.fill 156*((SIGALIGN)/4),4,0xdeadbeef
#ifdef rvtest_mtrap_routine
tsig_begin_canary:
CANARY;
tsig_begin_canary:
CANARY;
mtrap_sigptr:
.fill 64*(XLEN/32),4,0xdeadbeef
tsig_end_canary:
CANARY;
tsig_end_canary:
CANARY;
#endif
#ifdef rvtest_gpr_save
gpr_save:
.fill 32*XLEN/32,4,0xdeadbeef
#endif
sig_end_canary:
CANARY;
rvtest_sig_end:
RVMODEL_DATA_END

330
vendor/riscv-arch-tests/riscv-test-suite/rv32i_m/D/src/fcvt.wu.d_b27-01.S vendored
View file

@ -1,330 +0,0 @@
// -----------
// This file was generated by riscv_ctg (https://github.com/riscv-software-src/riscv-ctg)
// version : 0.7.1
// timestamp : Fri Jun 17 14:03:51 2022 GMT
// usage : riscv_ctg \
// -- cgf // --cgf /scratch/pawan/work/normalised/RV32D/fcvt.wu.d.cgf \
\
// -- xlen 32 \
// --randomize \
// -----------
//
// -----------
// Copyright (c) 2020. RISC-V International. All rights reserved.
// SPDX-License-Identifier: BSD-3-Clause
// -----------
//
// This assembly file tests the fcvt.wu.d instruction of the RISC-V RV32FD_Zicsr,RV64FD_Zicsr extension for the fcvt.wu.d_b27 covergroup.
//
#include "model_test.h"
#include "arch_test.h"
RVTEST_ISA("RV32IFD_Zicsr,RV64IFD_Zicsr")
.section .text.init
.org 0x80
.globl rvtest_entry_point
rvtest_entry_point:
RVMODEL_BOOT
RVTEST_CODE_BEGIN
#ifdef TEST_CASE_1
RVTEST_CASE(0,"//check ISA:=regex(.*I.*D.*);def TEST_CASE_1=True;",fcvt.wu.d_b27)
RVTEST_FP_ENABLE()
RVTEST_VALBASEUPD(x12,test_dataset_0)
RVTEST_SIGBASE(x2,signature_x2_1)
inst_0:// rs1==f7, rd==x5,fs1 == 0 and fe1 == 0x7ff and fm1 == 0x0000000000001 and fcsr == 0x0 and rm_val == 7
/* opcode: fcvt.wu.d ; op1:f7; dest:x5; op1val:0x7ff0000000000001; valaddr_reg:x12;
val_offset:0*FLEN/8; rmval:dyn; correctval:??; testreg:x14;
fcsr_val:0*/
TEST_FPID_OP(fcvt.wu.d, x5, f7, dyn, 0, 0, x12, 0*FLEN/8, x16, x2, x14,FLREG)
inst_1:// rs1==f29, rd==x30,fs1 == 0 and fe1 == 0x7ff and fm1 == 0x4aaaaaaaaaaaa and fcsr == 0x0 and rm_val == 7
/* opcode: fcvt.wu.d ; op1:f29; dest:x30; op1val:0x7ff4aaaaaaaaaaaa; valaddr_reg:x12;
val_offset:1*FLEN/8; rmval:dyn; correctval:??; testreg:x14;
fcsr_val:0*/
TEST_FPID_OP(fcvt.wu.d, x30, f29, dyn, 0, 0, x12, 1*FLEN/8, x16, x2, x14,FLREG)
inst_2:// rs1==f12, rd==x20,fs1 == 0 and fe1 == 0x7ff and fm1 == 0x8000000000001 and fcsr == 0x0 and rm_val == 7
/* opcode: fcvt.wu.d ; op1:f12; dest:x20; op1val:0x7ff8000000000001; valaddr_reg:x12;
val_offset:2*FLEN/8; rmval:dyn; correctval:??; testreg:x14;
fcsr_val:0*/
TEST_FPID_OP(fcvt.wu.d, x20, f12, dyn, 0, 0, x12, 2*FLEN/8, x16, x2, x14,FLREG)
inst_3:// rs1==f10, rd==x9,fs1 == 0 and fe1 == 0x7ff and fm1 == 0xc000000000001 and fcsr == 0x0 and rm_val == 7
/* opcode: fcvt.wu.d ; op1:f10; dest:x9; op1val:0x7ffc000000000001; valaddr_reg:x12;
val_offset:3*FLEN/8; rmval:dyn; correctval:??; testreg:x14;
fcsr_val:0*/
TEST_FPID_OP(fcvt.wu.d, x9, f10, dyn, 0, 0, x12, 3*FLEN/8, x16, x2, x14,FLREG)
inst_4:// rs1==f14, rd==x19,fs1 == 1 and fe1 == 0x7ff and fm1 == 0x0000000000001 and fcsr == 0x0 and rm_val == 7
/* opcode: fcvt.wu.d ; op1:f14; dest:x19; op1val:0xfff0000000000001; valaddr_reg:x12;
val_offset:4*FLEN/8; rmval:dyn; correctval:??; testreg:x14;
fcsr_val:0*/
TEST_FPID_OP(fcvt.wu.d, x19, f14, dyn, 0, 0, x12, 4*FLEN/8, x16, x2, x14,FLREG)
inst_5:// rs1==f15, rd==x13,fs1 == 1 and fe1 == 0x7ff and fm1 == 0x4aaaaaaaaaaaa and fcsr == 0x0 and rm_val == 7
/* opcode: fcvt.wu.d ; op1:f15; dest:x13; op1val:0xfff4aaaaaaaaaaaa; valaddr_reg:x12;
val_offset:5*FLEN/8; rmval:dyn; correctval:??; testreg:x14;
fcsr_val:0*/
TEST_FPID_OP(fcvt.wu.d, x13, f15, dyn, 0, 0, x12, 5*FLEN/8, x16, x2, x14,FLREG)
inst_6:// rs1==f19, rd==x29,fs1 == 1 and fe1 == 0x7ff and fm1 == 0x8000000000001 and fcsr == 0x0 and rm_val == 7
/* opcode: fcvt.wu.d ; op1:f19; dest:x29; op1val:0xfff8000000000001; valaddr_reg:x12;
val_offset:6*FLEN/8; rmval:dyn; correctval:??; testreg:x14;
fcsr_val:0*/
TEST_FPID_OP(fcvt.wu.d, x29, f19, dyn, 0, 0, x12, 6*FLEN/8, x16, x2, x14,FLREG)
inst_7:// rs1==f23, rd==x24,fs1 == 1 and fe1 == 0x7ff and fm1 == 0xc000000000001 and fcsr == 0x0 and rm_val == 7
/* opcode: fcvt.wu.d ; op1:f23; dest:x24; op1val:0xfffc000000000001; valaddr_reg:x12;
val_offset:7*FLEN/8; rmval:dyn; correctval:??; testreg:x14;
fcsr_val:0*/
TEST_FPID_OP(fcvt.wu.d, x24, f23, dyn, 0, 0, x12, 7*FLEN/8, x16, x2, x14,FLREG)
inst_8:// rs1==f9, rd==x23,
/* opcode: fcvt.wu.d ; op1:f9; dest:x23; op1val:0x0; valaddr_reg:x12;
val_offset:8*FLEN/8; rmval:dyn; correctval:??; testreg:x14;
fcsr_val:0*/
TEST_FPID_OP(fcvt.wu.d, x23, f9, dyn, 0, 0, x12, 8*FLEN/8, x16, x2, x14,FLREG)
inst_9:// rs1==f1, rd==x22,
/* opcode: fcvt.wu.d ; op1:f1; dest:x22; op1val:0x0; valaddr_reg:x12;
val_offset:9*FLEN/8; rmval:dyn; correctval:??; testreg:x14;
fcsr_val:0*/
TEST_FPID_OP(fcvt.wu.d, x22, f1, dyn, 0, 0, x12, 9*FLEN/8, x16, x2, x14,FLREG)
inst_10:// rs1==f25, rd==x27,
/* opcode: fcvt.wu.d ; op1:f25; dest:x27; op1val:0x0; valaddr_reg:x12;
val_offset:10*FLEN/8; rmval:dyn; correctval:??; testreg:x14;
fcsr_val:0*/
TEST_FPID_OP(fcvt.wu.d, x27, f25, dyn, 0, 0, x12, 10*FLEN/8, x16, x2, x14,FLREG)
inst_11:// rs1==f22, rd==x0,
/* opcode: fcvt.wu.d ; op1:f22; dest:x0; op1val:0x0; valaddr_reg:x12;
val_offset:11*FLEN/8; rmval:dyn; correctval:??; testreg:x14;
fcsr_val:0*/
TEST_FPID_OP(fcvt.wu.d, x0, f22, dyn, 0, 0, x12, 11*FLEN/8, x16, x2, x14,FLREG)
inst_12:// rs1==f6, rd==x25,
/* opcode: fcvt.wu.d ; op1:f6; dest:x25; op1val:0x0; valaddr_reg:x12;
val_offset:12*FLEN/8; rmval:dyn; correctval:??; testreg:x14;
fcsr_val:0*/
TEST_FPID_OP(fcvt.wu.d, x25, f6, dyn, 0, 0, x12, 12*FLEN/8, x16, x2, x14,FLREG)
inst_13:// rs1==f28, rd==x31,
/* opcode: fcvt.wu.d ; op1:f28; dest:x31; op1val:0x0; valaddr_reg:x12;
val_offset:13*FLEN/8; rmval:dyn; correctval:??; testreg:x14;
fcsr_val:0*/
TEST_FPID_OP(fcvt.wu.d, x31, f28, dyn, 0, 0, x12, 13*FLEN/8, x16, x2, x14,FLREG)
inst_14:// rs1==f13, rd==x15,
/* opcode: fcvt.wu.d ; op1:f13; dest:x15; op1val:0x0; valaddr_reg:x12;
val_offset:14*FLEN/8; rmval:dyn; correctval:??; testreg:x14;
fcsr_val:0*/
TEST_FPID_OP(fcvt.wu.d, x15, f13, dyn, 0, 0, x12, 14*FLEN/8, x16, x2, x14,FLREG)
inst_15:// rs1==f4, rd==x8,
/* opcode: fcvt.wu.d ; op1:f4; dest:x8; op1val:0x0; valaddr_reg:x12;
val_offset:15*FLEN/8; rmval:dyn; correctval:??; testreg:x14;
fcsr_val:0*/
TEST_FPID_OP(fcvt.wu.d, x8, f4, dyn, 0, 0, x12, 15*FLEN/8, x16, x2, x14,FLREG)
inst_16:// rs1==f30, rd==x10,
/* opcode: fcvt.wu.d ; op1:f30; dest:x10; op1val:0x0; valaddr_reg:x12;
val_offset:16*FLEN/8; rmval:dyn; correctval:??; testreg:x14;
fcsr_val:0*/
TEST_FPID_OP(fcvt.wu.d, x10, f30, dyn, 0, 0, x12, 16*FLEN/8, x16, x2, x14,FLREG)
inst_17:// rs1==f16, rd==x4,
/* opcode: fcvt.wu.d ; op1:f16; dest:x4; op1val:0x0; valaddr_reg:x12;
val_offset:17*FLEN/8; rmval:dyn; correctval:??; testreg:x14;
fcsr_val:0*/
TEST_FPID_OP(fcvt.wu.d, x4, f16, dyn, 0, 0, x12, 17*FLEN/8, x16, x2, x14,FLREG)
inst_18:// rs1==f3, rd==x7,
/* opcode: fcvt.wu.d ; op1:f3; dest:x7; op1val:0x0; valaddr_reg:x12;
val_offset:18*FLEN/8; rmval:dyn; correctval:??; testreg:x14;
fcsr_val:0*/
TEST_FPID_OP(fcvt.wu.d, x7, f3, dyn, 0, 0, x12, 18*FLEN/8, x16, x2, x14,FLREG)
inst_19:// rs1==f21, rd==x28,
/* opcode: fcvt.wu.d ; op1:f21; dest:x28; op1val:0x0; valaddr_reg:x12;
val_offset:19*FLEN/8; rmval:dyn; correctval:??; testreg:x14;
fcsr_val:0*/
TEST_FPID_OP(fcvt.wu.d, x28, f21, dyn, 0, 0, x12, 19*FLEN/8, x16, x2, x14,FLREG)
inst_20:// rs1==f2, rd==x11,
/* opcode: fcvt.wu.d ; op1:f2; dest:x11; op1val:0x0; valaddr_reg:x12;
val_offset:20*FLEN/8; rmval:dyn; correctval:??; testreg:x14;
fcsr_val:0*/
TEST_FPID_OP(fcvt.wu.d, x11, f2, dyn, 0, 0, x12, 20*FLEN/8, x16, x2, x14,FLREG)
inst_21:// rs1==f0, rd==x1,
/* opcode: fcvt.wu.d ; op1:f0; dest:x1; op1val:0x0; valaddr_reg:x12;
val_offset:21*FLEN/8; rmval:dyn; correctval:??; testreg:x14;
fcsr_val:0*/
TEST_FPID_OP(fcvt.wu.d, x1, f0, dyn, 0, 0, x12, 21*FLEN/8, x16, x2, x14,FLREG)
inst_22:// rs1==f18, rd==x6,
/* opcode: fcvt.wu.d ; op1:f18; dest:x6; op1val:0x0; valaddr_reg:x12;
val_offset:22*FLEN/8; rmval:dyn; correctval:??; testreg:x14;
fcsr_val:0*/
TEST_FPID_OP(fcvt.wu.d, x6, f18, dyn, 0, 0, x12, 22*FLEN/8, x16, x2, x14,FLREG)
inst_23:// rs1==f5, rd==x26,
/* opcode: fcvt.wu.d ; op1:f5; dest:x26; op1val:0x0; valaddr_reg:x12;
val_offset:23*FLEN/8; rmval:dyn; correctval:??; testreg:x14;
fcsr_val:0*/
TEST_FPID_OP(fcvt.wu.d, x26, f5, dyn, 0, 0, x12, 23*FLEN/8, x16, x2, x14,FLREG)
inst_24:// rs1==f11, rd==x3,
/* opcode: fcvt.wu.d ; op1:f11; dest:x3; op1val:0x0; valaddr_reg:x12;
val_offset:24*FLEN/8; rmval:dyn; correctval:??; testreg:x14;
fcsr_val:0*/
TEST_FPID_OP(fcvt.wu.d, x3, f11, dyn, 0, 0, x12, 24*FLEN/8, x16, x2, x14,FLREG)
RVTEST_VALBASEUPD(x4,test_dataset_1)
inst_25:// rs1==f31, rd==x12,
/* opcode: fcvt.wu.d ; op1:f31; dest:x12; op1val:0x0; valaddr_reg:x4;
val_offset:0*FLEN/8; rmval:dyn; correctval:??; testreg:x14;
fcsr_val:0*/
TEST_FPID_OP(fcvt.wu.d, x12, f31, dyn, 0, 0, x4, 0*FLEN/8, x5, x2, x14,FLREG)
inst_26:// rs1==f26, rd==x16,
/* opcode: fcvt.wu.d ; op1:f26; dest:x16; op1val:0x0; valaddr_reg:x4;
val_offset:1*FLEN/8; rmval:dyn; correctval:??; testreg:x14;
fcsr_val:0*/
TEST_FPID_OP(fcvt.wu.d, x16, f26, dyn, 0, 0, x4, 1*FLEN/8, x5, x2, x14,FLREG)
inst_27:// rs1==f20, rd==x21,
/* opcode: fcvt.wu.d ; op1:f20; dest:x21; op1val:0x0; valaddr_reg:x4;
val_offset:2*FLEN/8; rmval:dyn; correctval:??; testreg:x3;
fcsr_val:0*/
TEST_FPID_OP(fcvt.wu.d, x21, f20, dyn, 0, 0, x4, 2*FLEN/8, x5, x2, x3,FLREG)
RVTEST_SIGBASE(x1,signature_x1_0)
inst_28:// rs1==f24, rd==x2,
/* opcode: fcvt.wu.d ; op1:f24; dest:x2; op1val:0x0; valaddr_reg:x4;
val_offset:3*FLEN/8; rmval:dyn; correctval:??; testreg:x3;
fcsr_val:0*/
TEST_FPID_OP(fcvt.wu.d, x2, f24, dyn, 0, 0, x4, 3*FLEN/8, x5, x1, x3,FLREG)
inst_29:// rs1==f17, rd==x18,
/* opcode: fcvt.wu.d ; op1:f17; dest:x18; op1val:0x0; valaddr_reg:x4;
val_offset:4*FLEN/8; rmval:dyn; correctval:??; testreg:x3;
fcsr_val:0*/
TEST_FPID_OP(fcvt.wu.d, x18, f17, dyn, 0, 0, x4, 4*FLEN/8, x5, x1, x3,FLREG)
inst_30:// rs1==f8, rd==x14,
/* opcode: fcvt.wu.d ; op1:f8; dest:x14; op1val:0x0; valaddr_reg:x4;
val_offset:5*FLEN/8; rmval:dyn; correctval:??; testreg:x3;
fcsr_val:0*/
TEST_FPID_OP(fcvt.wu.d, x14, f8, dyn, 0, 0, x4, 5*FLEN/8, x5, x1, x3,FLREG)
inst_31:// rs1==f27, rd==x17,
/* opcode: fcvt.wu.d ; op1:f27; dest:x17; op1val:0x0; valaddr_reg:x4;
val_offset:6*FLEN/8; rmval:dyn; correctval:??; testreg:x3;
fcsr_val:0*/
TEST_FPID_OP(fcvt.wu.d, x17, f27, dyn, 0, 0, x4, 6*FLEN/8, x5, x1, x3,FLREG)
inst_32://
/* opcode: fcvt.wu.d ; op1:f31; dest:x31; op1val:0x0; valaddr_reg:x4;
val_offset:7*FLEN/8; rmval:dyn; correctval:??; testreg:x3;
fcsr_val:0*/
TEST_FPID_OP(fcvt.wu.d, x31, f31, dyn, 0, 0, x4, 7*FLEN/8, x5, x1, x3,FLREG)
#endif
RVTEST_CODE_END
RVMODEL_HALT
RVTEST_DATA_BEGIN
.align 4
rvtest_data:
.word 0xbabecafe
.word 0xabecafeb
.word 0xbecafeba
.word 0xecafebab
test_dataset_0:
NAN_BOXED(9218868437227405313,64,FLEN)
NAN_BOXED(9220181987118721706,64,FLEN)
NAN_BOXED(9221120237041090561,64,FLEN)
NAN_BOXED(9222246136947933185,64,FLEN)
NAN_BOXED(18442240474082181121,64,FLEN)
NAN_BOXED(18443554023973497514,64,FLEN)
NAN_BOXED(18444492273895866369,64,FLEN)
NAN_BOXED(18445618173802708993,64,FLEN)
NAN_BOXED(0,64,FLEN)
NAN_BOXED(0,64,FLEN)
NAN_BOXED(0,64,FLEN)
NAN_BOXED(0,64,FLEN)
NAN_BOXED(0,64,FLEN)
NAN_BOXED(0,64,FLEN)
NAN_BOXED(0,64,FLEN)
NAN_BOXED(0,64,FLEN)
NAN_BOXED(0,64,FLEN)
NAN_BOXED(0,64,FLEN)
NAN_BOXED(0,64,FLEN)
NAN_BOXED(0,64,FLEN)
NAN_BOXED(0,64,FLEN)
NAN_BOXED(0,64,FLEN)
NAN_BOXED(0,64,FLEN)
NAN_BOXED(0,64,FLEN)
NAN_BOXED(0,64,FLEN)
test_dataset_1:
NAN_BOXED(0,64,FLEN)
NAN_BOXED(0,64,FLEN)
NAN_BOXED(0,64,FLEN)
NAN_BOXED(0,64,FLEN)
NAN_BOXED(0,64,FLEN)
NAN_BOXED(0,64,FLEN)
NAN_BOXED(0,64,FLEN)
NAN_BOXED(0,64,FLEN)
RVTEST_DATA_END
RVMODEL_DATA_BEGIN
rvtest_sig_begin:
sig_begin_canary:
CANARY;
signature_x2_0:
.fill 0*((SIGALIGN)/4),4,0xdeadbeef
signature_x2_1:
.fill 56*((SIGALIGN)/4),4,0xdeadbeef
signature_x1_0:
.fill 10*((SIGALIGN)/4),4,0xdeadbeef
#ifdef rvtest_mtrap_routine
tsig_begin_canary:
CANARY;
tsig_begin_canary:
CANARY;
mtrap_sigptr:
.fill 64*(XLEN/32),4,0xdeadbeef
tsig_end_canary:
CANARY;
tsig_end_canary:
CANARY;
#endif
#ifdef rvtest_gpr_save
gpr_save:
.fill 32*XLEN/32,4,0xdeadbeef
#endif
sig_end_canary:
CANARY;
rvtest_sig_end:
RVMODEL_DATA_END

330
vendor/riscv-arch-tests/riscv-test-suite/rv32i_m/D/src/fcvt.wu.d_b28-01.S vendored
View file

@ -1,330 +0,0 @@
// -----------
// This file was generated by riscv_ctg (https://github.com/riscv-software-src/riscv-ctg)
// version : 0.7.1
// timestamp : Fri Jun 17 14:03:51 2022 GMT
// usage : riscv_ctg \
// -- cgf // --cgf /scratch/pawan/work/normalised/RV32D/fcvt.wu.d.cgf \
\
// -- xlen 32 \
// --randomize \
// -----------
//
// -----------
// Copyright (c) 2020. RISC-V International. All rights reserved.
// SPDX-License-Identifier: BSD-3-Clause
// -----------
//
// This assembly file tests the fcvt.wu.d instruction of the RISC-V RV32FD_Zicsr,RV64FD_Zicsr extension for the fcvt.wu.d_b28 covergroup.
//
#include "model_test.h"
#include "arch_test.h"
RVTEST_ISA("RV32IFD_Zicsr,RV64IFD_Zicsr")
.section .text.init
.org 0x80
.globl rvtest_entry_point
rvtest_entry_point:
RVMODEL_BOOT
RVTEST_CODE_BEGIN
#ifdef TEST_CASE_1
RVTEST_CASE(0,"//check ISA:=regex(.*I.*D.*);def TEST_CASE_1=True;",fcvt.wu.d_b28)
RVTEST_FP_ENABLE()
RVTEST_VALBASEUPD(x2,test_dataset_0)
RVTEST_SIGBASE(x8,signature_x8_1)
inst_0:// rs1==f26, rd==x21,fs1 == 0 and fe1 == 0x000 and fm1 == 0x0000000000000 and fcsr == 0x0 and rm_val == 7
/* opcode: fcvt.wu.d ; op1:f26; dest:x21; op1val:0x0; valaddr_reg:x2;
val_offset:0*FLEN/8; rmval:dyn; correctval:??; testreg:x6;
fcsr_val:0*/
TEST_FPID_OP(fcvt.wu.d, x21, f26, dyn, 0, 0, x2, 0*FLEN/8, x12, x8, x6,FLREG)
inst_1:// rs1==f17, rd==x17,fs1 == 0 and fe1 == 0x3fe and fm1 == 0x248ee18215dfa and fcsr == 0x0 and rm_val == 7
/* opcode: fcvt.wu.d ; op1:f17; dest:x17; op1val:0x3fe248ee18215dfa; valaddr_reg:x2;
val_offset:1*FLEN/8; rmval:dyn; correctval:??; testreg:x6;
fcsr_val:0*/
TEST_FPID_OP(fcvt.wu.d, x17, f17, dyn, 0, 0, x2, 1*FLEN/8, x12, x8, x6,FLREG)
inst_2:// rs1==f7, rd==x15,fs1 == 0 and fe1 == 0x3ff and fm1 == 0x0000000000000 and fcsr == 0x0 and rm_val == 7
/* opcode: fcvt.wu.d ; op1:f7; dest:x15; op1val:0x3ff0000000000000; valaddr_reg:x2;
val_offset:2*FLEN/8; rmval:dyn; correctval:??; testreg:x6;
fcsr_val:0*/
TEST_FPID_OP(fcvt.wu.d, x15, f7, dyn, 0, 0, x2, 2*FLEN/8, x12, x8, x6,FLREG)
inst_3:// rs1==f21, rd==x7,fs1 == 0 and fe1 == 0x3ff and fm1 == 0x4000000000000 and fcsr == 0x0 and rm_val == 7
/* opcode: fcvt.wu.d ; op1:f21; dest:x7; op1val:0x3ff4000000000000; valaddr_reg:x2;
val_offset:3*FLEN/8; rmval:dyn; correctval:??; testreg:x6;
fcsr_val:0*/
TEST_FPID_OP(fcvt.wu.d, x7, f21, dyn, 0, 0, x2, 3*FLEN/8, x12, x8, x6,FLREG)
inst_4:// rs1==f15, rd==x22,fs1 == 0 and fe1 == 0x3ff and fm1 == 0x8000000000000 and fcsr == 0x0 and rm_val == 7
/* opcode: fcvt.wu.d ; op1:f15; dest:x22; op1val:0x3ff8000000000000; valaddr_reg:x2;
val_offset:4*FLEN/8; rmval:dyn; correctval:??; testreg:x6;
fcsr_val:0*/
TEST_FPID_OP(fcvt.wu.d, x22, f15, dyn, 0, 0, x2, 4*FLEN/8, x12, x8, x6,FLREG)
inst_5:// rs1==f3, rd==x27,fs1 == 0 and fe1 == 0x3ff and fm1 == 0xc000000000000 and fcsr == 0x0 and rm_val == 7
/* opcode: fcvt.wu.d ; op1:f3; dest:x27; op1val:0x3ffc000000000000; valaddr_reg:x2;
val_offset:5*FLEN/8; rmval:dyn; correctval:??; testreg:x6;
fcsr_val:0*/
TEST_FPID_OP(fcvt.wu.d, x27, f3, dyn, 0, 0, x2, 5*FLEN/8, x12, x8, x6,FLREG)
inst_6:// rs1==f1, rd==x14,fs1 == 0 and fe1 == 0x400 and fm1 == 0x0000000000000 and fcsr == 0x0 and rm_val == 7
/* opcode: fcvt.wu.d ; op1:f1; dest:x14; op1val:0x4000000000000000; valaddr_reg:x2;
val_offset:6*FLEN/8; rmval:dyn; correctval:??; testreg:x6;
fcsr_val:0*/
TEST_FPID_OP(fcvt.wu.d, x14, f1, dyn, 0, 0, x2, 6*FLEN/8, x12, x8, x6,FLREG)
inst_7:// rs1==f18, rd==x16,fs1 == 0 and fe1 == 0x400 and fm1 == 0x2000000000000 and fcsr == 0x0 and rm_val == 7
/* opcode: fcvt.wu.d ; op1:f18; dest:x16; op1val:0x4002000000000000; valaddr_reg:x2;
val_offset:7*FLEN/8; rmval:dyn; correctval:??; testreg:x6;
fcsr_val:0*/
TEST_FPID_OP(fcvt.wu.d, x16, f18, dyn, 0, 0, x2, 7*FLEN/8, x12, x8, x6,FLREG)
inst_8:// rs1==f30, rd==x28,fs1 == 0 and fe1 == 0x400 and fm1 == 0x4000000000000 and fcsr == 0x0 and rm_val == 7
/* opcode: fcvt.wu.d ; op1:f30; dest:x28; op1val:0x4004000000000000; valaddr_reg:x2;
val_offset:8*FLEN/8; rmval:dyn; correctval:??; testreg:x6;
fcsr_val:0*/
TEST_FPID_OP(fcvt.wu.d, x28, f30, dyn, 0, 0, x2, 8*FLEN/8, x12, x8, x6,FLREG)
inst_9:// rs1==f9, rd==x26,fs1 == 0 and fe1 == 0x400 and fm1 == 0x6000000000000 and fcsr == 0x0 and rm_val == 7
/* opcode: fcvt.wu.d ; op1:f9; dest:x26; op1val:0x4006000000000000; valaddr_reg:x2;
val_offset:9*FLEN/8; rmval:dyn; correctval:??; testreg:x6;
fcsr_val:0*/
TEST_FPID_OP(fcvt.wu.d, x26, f9, dyn, 0, 0, x2, 9*FLEN/8, x12, x8, x6,FLREG)
inst_10:// rs1==f11, rd==x9,fs1 == 0 and fe1 == 0x43c and fm1 == 0xb72eb13dc494a and fcsr == 0x0 and rm_val == 7
/* opcode: fcvt.wu.d ; op1:f11; dest:x9; op1val:0x43cb72eb13dc494a; valaddr_reg:x2;
val_offset:10*FLEN/8; rmval:dyn; correctval:??; testreg:x6;
fcsr_val:0*/
TEST_FPID_OP(fcvt.wu.d, x9, f11, dyn, 0, 0, x2, 10*FLEN/8, x12, x8, x6,FLREG)
inst_11:// rs1==f4, rd==x5,fs1 == 0 and fe1 == 0x43e and fm1 == 0x0000000000000 and fcsr == 0x0 and rm_val == 7
/* opcode: fcvt.wu.d ; op1:f4; dest:x5; op1val:0x43e0000000000000; valaddr_reg:x2;
val_offset:11*FLEN/8; rmval:dyn; correctval:??; testreg:x6;
fcsr_val:0*/
TEST_FPID_OP(fcvt.wu.d, x5, f4, dyn, 0, 0, x2, 11*FLEN/8, x12, x8, x6,FLREG)
inst_12:// rs1==f16, rd==x4,fs1 == 0 and fe1 == 0x7ff and fm1 == 0x0000000000000 and fcsr == 0x0 and rm_val == 7
/* opcode: fcvt.wu.d ; op1:f16; dest:x4; op1val:0x7ff0000000000000; valaddr_reg:x2;
val_offset:12*FLEN/8; rmval:dyn; correctval:??; testreg:x6;
fcsr_val:0*/
TEST_FPID_OP(fcvt.wu.d, x4, f16, dyn, 0, 0, x2, 12*FLEN/8, x12, x8, x6,FLREG)
inst_13:// rs1==f8, rd==x13,fs1 == 0 and fe1 == 0x7ff and fm1 == 0x0000000000001 and fcsr == 0x0 and rm_val == 7
/* opcode: fcvt.wu.d ; op1:f8; dest:x13; op1val:0x7ff0000000000001; valaddr_reg:x2;
val_offset:13*FLEN/8; rmval:dyn; correctval:??; testreg:x6;
fcsr_val:0*/
TEST_FPID_OP(fcvt.wu.d, x13, f8, dyn, 0, 0, x2, 13*FLEN/8, x12, x8, x6,FLREG)
inst_14:// rs1==f2, rd==x11,fs1 == 0 and fe1 == 0x7ff and fm1 == 0x8000000000001 and fcsr == 0x0 and rm_val == 7
/* opcode: fcvt.wu.d ; op1:f2; dest:x11; op1val:0x7ff8000000000001; valaddr_reg:x2;
val_offset:14*FLEN/8; rmval:dyn; correctval:??; testreg:x6;
fcsr_val:0*/
TEST_FPID_OP(fcvt.wu.d, x11, f2, dyn, 0, 0, x2, 14*FLEN/8, x12, x8, x6,FLREG)
inst_15:// rs1==f23, rd==x3,fs1 == 1 and fe1 == 0x000 and fm1 == 0x0000000000000 and fcsr == 0x0 and rm_val == 7
/* opcode: fcvt.wu.d ; op1:f23; dest:x3; op1val:0x8000000000000000; valaddr_reg:x2;
val_offset:15*FLEN/8; rmval:dyn; correctval:??; testreg:x6;
fcsr_val:0*/
TEST_FPID_OP(fcvt.wu.d, x3, f23, dyn, 0, 0, x2, 15*FLEN/8, x12, x8, x6,FLREG)
inst_16:// rs1==f14, rd==x29,fs1 == 1 and fe1 == 0x3f8 and fm1 == 0x0000000000000 and fcsr == 0x0 and rm_val == 7
/* opcode: fcvt.wu.d ; op1:f14; dest:x29; op1val:0xbf80000000000000; valaddr_reg:x2;
val_offset:16*FLEN/8; rmval:dyn; correctval:??; testreg:x6;
fcsr_val:0*/
TEST_FPID_OP(fcvt.wu.d, x29, f14, dyn, 0, 0, x2, 16*FLEN/8, x12, x8, x6,FLREG)
inst_17:// rs1==f13, rd==x31,fs1 == 1 and fe1 == 0x3fd and fm1 == 0xb008d57e19f88 and fcsr == 0x0 and rm_val == 7
/* opcode: fcvt.wu.d ; op1:f13; dest:x31; op1val:0xbfdb008d57e19f88; valaddr_reg:x2;
val_offset:17*FLEN/8; rmval:dyn; correctval:??; testreg:x6;
fcsr_val:0*/
TEST_FPID_OP(fcvt.wu.d, x31, f13, dyn, 0, 0, x2, 17*FLEN/8, x12, x8, x6,FLREG)
inst_18:// rs1==f25, rd==x25,fs1 == 1 and fe1 == 0x3ff and fm1 == 0x4000000000000 and fcsr == 0x0 and rm_val == 7
/* opcode: fcvt.wu.d ; op1:f25; dest:x25; op1val:0xbff4000000000000; valaddr_reg:x2;
val_offset:18*FLEN/8; rmval:dyn; correctval:??; testreg:x6;
fcsr_val:0*/
TEST_FPID_OP(fcvt.wu.d, x25, f25, dyn, 0, 0, x2, 18*FLEN/8, x12, x8, x6,FLREG)
inst_19:// rs1==f31, rd==x30,fs1 == 1 and fe1 == 0x3ff and fm1 == 0x8000000000000 and fcsr == 0x0 and rm_val == 7
/* opcode: fcvt.wu.d ; op1:f31; dest:x30; op1val:0xbff8000000000000; valaddr_reg:x2;
val_offset:19*FLEN/8; rmval:dyn; correctval:??; testreg:x6;
fcsr_val:0*/
TEST_FPID_OP(fcvt.wu.d, x30, f31, dyn, 0, 0, x2, 19*FLEN/8, x12, x8, x6,FLREG)
inst_20:// rs1==f29, rd==x0,fs1 == 1 and fe1 == 0x3ff and fm1 == 0xc000000000000 and fcsr == 0x0 and rm_val == 7
/* opcode: fcvt.wu.d ; op1:f29; dest:x0; op1val:0xbffc000000000000; valaddr_reg:x2;
val_offset:20*FLEN/8; rmval:dyn; correctval:??; testreg:x6;
fcsr_val:0*/
TEST_FPID_OP(fcvt.wu.d, x0, f29, dyn, 0, 0, x2, 20*FLEN/8, x12, x8, x6,FLREG)
inst_21:// rs1==f12, rd==x10,fs1 == 1 and fe1 == 0x400 and fm1 == 0x0000000000000 and fcsr == 0x0 and rm_val == 7
/* opcode: fcvt.wu.d ; op1:f12; dest:x10; op1val:0xc000000000000000; valaddr_reg:x2;
val_offset:21*FLEN/8; rmval:dyn; correctval:??; testreg:x6;
fcsr_val:0*/
TEST_FPID_OP(fcvt.wu.d, x10, f12, dyn, 0, 0, x2, 21*FLEN/8, x12, x8, x6,FLREG)
inst_22:// rs1==f10, rd==x20,fs1 == 1 and fe1 == 0x400 and fm1 == 0x2000000000000 and fcsr == 0x0 and rm_val == 7
/* opcode: fcvt.wu.d ; op1:f10; dest:x20; op1val:0xc002000000000000; valaddr_reg:x2;
val_offset:22*FLEN/8; rmval:dyn; correctval:??; testreg:x6;
fcsr_val:0*/
TEST_FPID_OP(fcvt.wu.d, x20, f10, dyn, 0, 0, x2, 22*FLEN/8, x12, x8, x6,FLREG)
inst_23:// rs1==f0, rd==x18,fs1 == 1 and fe1 == 0x400 and fm1 == 0x4000000000000 and fcsr == 0x0 and rm_val == 7
/* opcode: fcvt.wu.d ; op1:f0; dest:x18; op1val:0xc004000000000000; valaddr_reg:x2;
val_offset:23*FLEN/8; rmval:dyn; correctval:??; testreg:x6;
fcsr_val:0*/
TEST_FPID_OP(fcvt.wu.d, x18, f0, dyn, 0, 0, x2, 23*FLEN/8, x12, x8, x6,FLREG)
inst_24:// rs1==f24, rd==x1,fs1 == 1 and fe1 == 0x400 and fm1 == 0x6000000000000 and fcsr == 0x0 and rm_val == 7
/* opcode: fcvt.wu.d ; op1:f24; dest:x1; op1val:0xc006000000000000; valaddr_reg:x2;
val_offset:24*FLEN/8; rmval:dyn; correctval:??; testreg:x6;
fcsr_val:0*/
TEST_FPID_OP(fcvt.wu.d, x1, f24, dyn, 0, 0, x2, 24*FLEN/8, x12, x8, x6,FLREG)
RVTEST_VALBASEUPD(x3,test_dataset_1)
inst_25:// rs1==f19, rd==x2,fs1 == 1 and fe1 == 0x43d and fm1 == 0x967a4ae26514c and fcsr == 0x0 and rm_val == 7
/* opcode: fcvt.wu.d ; op1:f19; dest:x2; op1val:0xc3d967a4ae26514c; valaddr_reg:x3;
val_offset:0*FLEN/8; rmval:dyn; correctval:??; testreg:x6;
fcsr_val:0*/
TEST_FPID_OP(fcvt.wu.d, x2, f19, dyn, 0, 0, x3, 0*FLEN/8, x4, x8, x6,FLREG)
inst_26:// rs1==f27, rd==x19,fs1 == 1 and fe1 == 0x43e and fm1 == 0x0000000000000 and fcsr == 0x0 and rm_val == 7
/* opcode: fcvt.wu.d ; op1:f27; dest:x19; op1val:0xc3e0000000000000; valaddr_reg:x3;
val_offset:1*FLEN/8; rmval:dyn; correctval:??; testreg:x6;
fcsr_val:0*/
TEST_FPID_OP(fcvt.wu.d, x19, f27, dyn, 0, 0, x3, 1*FLEN/8, x4, x8, x6,FLREG)
inst_27:// rs1==f28, rd==x6,fs1 == 1 and fe1 == 0x7ff and fm1 == 0x0000000000000 and fcsr == 0x0 and rm_val == 7
/* opcode: fcvt.wu.d ; op1:f28; dest:x6; op1val:0xfff0000000000000; valaddr_reg:x3;
val_offset:2*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
fcsr_val:0*/
TEST_FPID_OP(fcvt.wu.d, x6, f28, dyn, 0, 0, x3, 2*FLEN/8, x4, x8, x2,FLREG)
RVTEST_SIGBASE(x1,signature_x1_0)
inst_28:// rs1==f22, rd==x12,
/* opcode: fcvt.wu.d ; op1:f22; dest:x12; op1val:0x0; valaddr_reg:x3;
val_offset:3*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
fcsr_val:0*/
TEST_FPID_OP(fcvt.wu.d, x12, f22, dyn, 0, 0, x3, 3*FLEN/8, x4, x1, x2,FLREG)
inst_29:// rs1==f5, rd==x24,
/* opcode: fcvt.wu.d ; op1:f5; dest:x24; op1val:0x0; valaddr_reg:x3;
val_offset:4*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
fcsr_val:0*/
TEST_FPID_OP(fcvt.wu.d, x24, f5, dyn, 0, 0, x3, 4*FLEN/8, x4, x1, x2,FLREG)
inst_30:// rs1==f20, rd==x23,
/* opcode: fcvt.wu.d ; op1:f20; dest:x23; op1val:0x0; valaddr_reg:x3;
val_offset:5*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
fcsr_val:0*/
TEST_FPID_OP(fcvt.wu.d, x23, f20, dyn, 0, 0, x3, 5*FLEN/8, x4, x1, x2,FLREG)
inst_31:// rs1==f6, rd==x8,
/* opcode: fcvt.wu.d ; op1:f6; dest:x8; op1val:0x0; valaddr_reg:x3;
val_offset:6*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
fcsr_val:0*/
TEST_FPID_OP(fcvt.wu.d, x8, f6, dyn, 0, 0, x3, 6*FLEN/8, x4, x1, x2,FLREG)
inst_32:// fs1 == 1 and fe1 == 0x3ff and fm1 == 0xc000000000000 and fcsr == 0x0 and rm_val == 7
/* opcode: fcvt.wu.d ; op1:f31; dest:x31; op1val:0xbffc000000000000; valaddr_reg:x3;
val_offset:7*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
fcsr_val:0*/
TEST_FPID_OP(fcvt.wu.d, x31, f31, dyn, 0, 0, x3, 7*FLEN/8, x4, x1, x2,FLREG)
#endif
RVTEST_CODE_END
RVMODEL_HALT
RVTEST_DATA_BEGIN
.align 4
rvtest_data:
.word 0xbabecafe
.word 0xabecafeb
.word 0xbecafeba
.word 0xecafebab
test_dataset_0:
NAN_BOXED(0,64,FLEN)
NAN_BOXED(4603321956570324474,64,FLEN)
NAN_BOXED(4607182418800017408,64,FLEN)
NAN_BOXED(4608308318706860032,64,FLEN)
NAN_BOXED(4609434218613702656,64,FLEN)
NAN_BOXED(4610560118520545280,64,FLEN)
NAN_BOXED(4611686018427387904,64,FLEN)
NAN_BOXED(4612248968380809216,64,FLEN)
NAN_BOXED(4612811918334230528,64,FLEN)
NAN_BOXED(4613374868287651840,64,FLEN)
NAN_BOXED(4885124574789519690,64,FLEN)
NAN_BOXED(4890909195324358656,64,FLEN)
NAN_BOXED(9218868437227405312,64,FLEN)
NAN_BOXED(9218868437227405313,64,FLEN)
NAN_BOXED(9221120237041090561,64,FLEN)
NAN_BOXED(9223372036854775808,64,FLEN)
NAN_BOXED(13799029258263199744,64,FLEN)
NAN_BOXED(13824644088208662408,64,FLEN)
NAN_BOXED(13831680355561635840,64,FLEN)
NAN_BOXED(13832806255468478464,64,FLEN)
NAN_BOXED(13833932155375321088,64,FLEN)
NAN_BOXED(13835058055282163712,64,FLEN)
NAN_BOXED(13835621005235585024,64,FLEN)
NAN_BOXED(13836183955189006336,64,FLEN)
NAN_BOXED(13836746905142427648,64,FLEN)
test_dataset_1:
NAN_BOXED(14112424864336204108,64,FLEN)
NAN_BOXED(14114281232179134464,64,FLEN)
NAN_BOXED(18442240474082181120,64,FLEN)
NAN_BOXED(0,64,FLEN)
NAN_BOXED(0,64,FLEN)
NAN_BOXED(0,64,FLEN)
NAN_BOXED(0,64,FLEN)
NAN_BOXED(13833932155375321088,64,FLEN)
RVTEST_DATA_END
RVMODEL_DATA_BEGIN
rvtest_sig_begin:
sig_begin_canary:
CANARY;
signature_x8_0:
.fill 0*((SIGALIGN)/4),4,0xdeadbeef
signature_x8_1:
.fill 56*((SIGALIGN)/4),4,0xdeadbeef
signature_x1_0:
.fill 10*((SIGALIGN)/4),4,0xdeadbeef
#ifdef rvtest_mtrap_routine
tsig_begin_canary:
CANARY;
tsig_begin_canary:
CANARY;
mtrap_sigptr:
.fill 64*(XLEN/32),4,0xdeadbeef
tsig_end_canary:
CANARY;
tsig_end_canary:
CANARY;
#endif
#ifdef rvtest_gpr_save
gpr_save:
.fill 32*XLEN/32,4,0xdeadbeef
#endif
sig_end_canary:
CANARY;
rvtest_sig_end:
RVMODEL_DATA_END

666
vendor/riscv-arch-tests/riscv-test-suite/rv32i_m/D/src/fcvt.wu.d_b29-01.S vendored
View file

@ -1,666 +0,0 @@
// -----------
// This file was generated by riscv_ctg (https://github.com/riscv-software-src/riscv-ctg)
// version : 0.7.1
// timestamp : Fri Jun 17 14:03:51 2022 GMT
// usage : riscv_ctg \
// -- cgf // --cgf /scratch/pawan/work/normalised/RV32D/fcvt.wu.d.cgf \
\
// -- xlen 32 \
// --randomize \
// -----------
//
// -----------
// Copyright (c) 2020. RISC-V International. All rights reserved.
// SPDX-License-Identifier: BSD-3-Clause
// -----------
//
// This assembly file tests the fcvt.wu.d instruction of the RISC-V RV32FD_Zicsr,RV64FD_Zicsr extension for the fcvt.wu.d_b29 covergroup.
//
#include "model_test.h"
#include "arch_test.h"
RVTEST_ISA("RV32IFD_Zicsr,RV64IFD_Zicsr")
.section .text.init
.org 0x80
.globl rvtest_entry_point
rvtest_entry_point:
RVMODEL_BOOT
RVTEST_CODE_BEGIN
#ifdef TEST_CASE_1
RVTEST_CASE(0,"//check ISA:=regex(.*I.*D.*);def TEST_CASE_1=True;",fcvt.wu.d_b29)
RVTEST_FP_ENABLE()
RVTEST_VALBASEUPD(x5,test_dataset_0)
RVTEST_SIGBASE(x4,signature_x4_1)
inst_0:// rs1==f6, rd==x17,fs1 == 0 and fe1 == 0x3fc and fm1 == 0x08574923b8698 and fcsr == 0x0 and rm_val == 7
/* opcode: fcvt.wu.d ; op1:f6; dest:x17; op1val:0x3fc08574923b8698; valaddr_reg:x5;
val_offset:0*FLEN/8; rmval:dyn; correctval:??; testreg:x13;
fcsr_val:0*/
TEST_FPID_OP(fcvt.wu.d, x17, f6, dyn, 0, 0, x5, 0*FLEN/8, x19, x4, x13,FLREG)
inst_1:// rs1==f29, rd==x14,fs1 == 0 and fe1 == 0x3fc and fm1 == 0x08574923b8698 and fcsr == 0x20 and rm_val == 7
/* opcode: fcvt.wu.d ; op1:f29; dest:x14; op1val:0x3fc08574923b8698; valaddr_reg:x5;
val_offset:1*FLEN/8; rmval:dyn; correctval:??; testreg:x13;
fcsr_val:32*/
TEST_FPID_OP(fcvt.wu.d, x14, f29, dyn, 32, 0, x5, 1*FLEN/8, x19, x4, x13,FLREG)
inst_2:// rs1==f30, rd==x29,fs1 == 0 and fe1 == 0x3fc and fm1 == 0x08574923b8698 and fcsr == 0x40 and rm_val == 7
/* opcode: fcvt.wu.d ; op1:f30; dest:x29; op1val:0x3fc08574923b8698; valaddr_reg:x5;
val_offset:2*FLEN/8; rmval:dyn; correctval:??; testreg:x13;
fcsr_val:64*/
TEST_FPID_OP(fcvt.wu.d, x29, f30, dyn, 64, 0, x5, 2*FLEN/8, x19, x4, x13,FLREG)
inst_3:// rs1==f12, rd==x15,fs1 == 0 and fe1 == 0x3fc and fm1 == 0x08574923b8698 and fcsr == 0x60 and rm_val == 7
/* opcode: fcvt.wu.d ; op1:f12; dest:x15; op1val:0x3fc08574923b8698; valaddr_reg:x5;
val_offset:3*FLEN/8; rmval:dyn; correctval:??; testreg:x13;
fcsr_val:96*/
TEST_FPID_OP(fcvt.wu.d, x15, f12, dyn, 96, 0, x5, 3*FLEN/8, x19, x4, x13,FLREG)
inst_4:// rs1==f8, rd==x24,fs1 == 0 and fe1 == 0x3fc and fm1 == 0x08574923b8698 and fcsr == 0x80 and rm_val == 7
/* opcode: fcvt.wu.d ; op1:f8; dest:x24; op1val:0x3fc08574923b8698; valaddr_reg:x5;
val_offset:4*FLEN/8; rmval:dyn; correctval:??; testreg:x13;
fcsr_val:128*/
TEST_FPID_OP(fcvt.wu.d, x24, f8, dyn, 128, 0, x5, 4*FLEN/8, x19, x4, x13,FLREG)
inst_5:// rs1==f16, rd==x1,fs1 == 0 and fe1 == 0x3fc and fm1 == 0x08574923b8699 and fcsr == 0x0 and rm_val == 7
/* opcode: fcvt.wu.d ; op1:f16; dest:x1; op1val:0x3fc08574923b8699; valaddr_reg:x5;
val_offset:5*FLEN/8; rmval:dyn; correctval:??; testreg:x13;
fcsr_val:0*/
TEST_FPID_OP(fcvt.wu.d, x1, f16, dyn, 0, 0, x5, 5*FLEN/8, x19, x4, x13,FLREG)
inst_6:// rs1==f25, rd==x23,fs1 == 0 and fe1 == 0x3fc and fm1 == 0x08574923b8699 and fcsr == 0x20 and rm_val == 7
/* opcode: fcvt.wu.d ; op1:f25; dest:x23; op1val:0x3fc08574923b8699; valaddr_reg:x5;
val_offset:6*FLEN/8; rmval:dyn; correctval:??; testreg:x13;
fcsr_val:32*/
TEST_FPID_OP(fcvt.wu.d, x23, f25, dyn, 32, 0, x5, 6*FLEN/8, x19, x4, x13,FLREG)
inst_7:// rs1==f21, rd==x25,fs1 == 0 and fe1 == 0x3fc and fm1 == 0x08574923b8699 and fcsr == 0x40 and rm_val == 7
/* opcode: fcvt.wu.d ; op1:f21; dest:x25; op1val:0x3fc08574923b8699; valaddr_reg:x5;
val_offset:7*FLEN/8; rmval:dyn; correctval:??; testreg:x13;
fcsr_val:64*/
TEST_FPID_OP(fcvt.wu.d, x25, f21, dyn, 64, 0, x5, 7*FLEN/8, x19, x4, x13,FLREG)
inst_8:// rs1==f27, rd==x20,fs1 == 0 and fe1 == 0x3fc and fm1 == 0x08574923b8699 and fcsr == 0x60 and rm_val == 7
/* opcode: fcvt.wu.d ; op1:f27; dest:x20; op1val:0x3fc08574923b8699; valaddr_reg:x5;
val_offset:8*FLEN/8; rmval:dyn; correctval:??; testreg:x13;
fcsr_val:96*/
TEST_FPID_OP(fcvt.wu.d, x20, f27, dyn, 96, 0, x5, 8*FLEN/8, x19, x4, x13,FLREG)
inst_9:// rs1==f3, rd==x22,fs1 == 0 and fe1 == 0x3fc and fm1 == 0x08574923b8699 and fcsr == 0x80 and rm_val == 7
/* opcode: fcvt.wu.d ; op1:f3; dest:x22; op1val:0x3fc08574923b8699; valaddr_reg:x5;
val_offset:9*FLEN/8; rmval:dyn; correctval:??; testreg:x13;
fcsr_val:128*/
TEST_FPID_OP(fcvt.wu.d, x22, f3, dyn, 128, 0, x5, 9*FLEN/8, x19, x4, x13,FLREG)
inst_10:// rs1==f17, rd==x10,fs1 == 0 and fe1 == 0x3fc and fm1 == 0x08574923b869a and fcsr == 0x0 and rm_val == 7
/* opcode: fcvt.wu.d ; op1:f17; dest:x10; op1val:0x3fc08574923b869a; valaddr_reg:x5;
val_offset:10*FLEN/8; rmval:dyn; correctval:??; testreg:x13;
fcsr_val:0*/
TEST_FPID_OP(fcvt.wu.d, x10, f17, dyn, 0, 0, x5, 10*FLEN/8, x19, x4, x13,FLREG)
inst_11:// rs1==f1, rd==x7,fs1 == 0 and fe1 == 0x3fc and fm1 == 0x08574923b869a and fcsr == 0x20 and rm_val == 7
/* opcode: fcvt.wu.d ; op1:f1; dest:x7; op1val:0x3fc08574923b869a; valaddr_reg:x5;
val_offset:11*FLEN/8; rmval:dyn; correctval:??; testreg:x13;
fcsr_val:32*/
TEST_FPID_OP(fcvt.wu.d, x7, f1, dyn, 32, 0, x5, 11*FLEN/8, x19, x4, x13,FLREG)
inst_12:// rs1==f0, rd==x27,fs1 == 0 and fe1 == 0x3fc and fm1 == 0x08574923b869a and fcsr == 0x40 and rm_val == 7
/* opcode: fcvt.wu.d ; op1:f0; dest:x27; op1val:0x3fc08574923b869a; valaddr_reg:x5;
val_offset:12*FLEN/8; rmval:dyn; correctval:??; testreg:x13;
fcsr_val:64*/
TEST_FPID_OP(fcvt.wu.d, x27, f0, dyn, 64, 0, x5, 12*FLEN/8, x19, x4, x13,FLREG)
inst_13:// rs1==f24, rd==x28,fs1 == 0 and fe1 == 0x3fc and fm1 == 0x08574923b869a and fcsr == 0x60 and rm_val == 7
/* opcode: fcvt.wu.d ; op1:f24; dest:x28; op1val:0x3fc08574923b869a; valaddr_reg:x5;
val_offset:13*FLEN/8; rmval:dyn; correctval:??; testreg:x13;
fcsr_val:96*/
TEST_FPID_OP(fcvt.wu.d, x28, f24, dyn, 96, 0, x5, 13*FLEN/8, x19, x4, x13,FLREG)
inst_14:// rs1==f28, rd==x11,fs1 == 0 and fe1 == 0x3fc and fm1 == 0x08574923b869a and fcsr == 0x80 and rm_val == 7
/* opcode: fcvt.wu.d ; op1:f28; dest:x11; op1val:0x3fc08574923b869a; valaddr_reg:x5;
val_offset:14*FLEN/8; rmval:dyn; correctval:??; testreg:x13;
fcsr_val:128*/
TEST_FPID_OP(fcvt.wu.d, x11, f28, dyn, 128, 0, x5, 14*FLEN/8, x19, x4, x13,FLREG)
inst_15:// rs1==f14, rd==x18,fs1 == 0 and fe1 == 0x3fc and fm1 == 0x08574923b869b and fcsr == 0x0 and rm_val == 7
/* opcode: fcvt.wu.d ; op1:f14; dest:x18; op1val:0x3fc08574923b869b; valaddr_reg:x5;
val_offset:15*FLEN/8; rmval:dyn; correctval:??; testreg:x13;
fcsr_val:0*/
TEST_FPID_OP(fcvt.wu.d, x18, f14, dyn, 0, 0, x5, 15*FLEN/8, x19, x4, x13,FLREG)
inst_16:// rs1==f4, rd==x26,fs1 == 0 and fe1 == 0x3fc and fm1 == 0x08574923b869b and fcsr == 0x20 and rm_val == 7
/* opcode: fcvt.wu.d ; op1:f4; dest:x26; op1val:0x3fc08574923b869b; valaddr_reg:x5;
val_offset:16*FLEN/8; rmval:dyn; correctval:??; testreg:x13;
fcsr_val:32*/
TEST_FPID_OP(fcvt.wu.d, x26, f4, dyn, 32, 0, x5, 16*FLEN/8, x19, x4, x13,FLREG)
inst_17:// rs1==f13, rd==x2,fs1 == 0 and fe1 == 0x3fc and fm1 == 0x08574923b869b and fcsr == 0x40 and rm_val == 7
/* opcode: fcvt.wu.d ; op1:f13; dest:x2; op1val:0x3fc08574923b869b; valaddr_reg:x5;
val_offset:17*FLEN/8; rmval:dyn; correctval:??; testreg:x13;
fcsr_val:64*/
TEST_FPID_OP(fcvt.wu.d, x2, f13, dyn, 64, 0, x5, 17*FLEN/8, x19, x4, x13,FLREG)
inst_18:// rs1==f26, rd==x9,fs1 == 0 and fe1 == 0x3fc and fm1 == 0x08574923b869b and fcsr == 0x60 and rm_val == 7
/* opcode: fcvt.wu.d ; op1:f26; dest:x9; op1val:0x3fc08574923b869b; valaddr_reg:x5;
val_offset:18*FLEN/8; rmval:dyn; correctval:??; testreg:x13;
fcsr_val:96*/
TEST_FPID_OP(fcvt.wu.d, x9, f26, dyn, 96, 0, x5, 18*FLEN/8, x19, x4, x13,FLREG)
inst_19:// rs1==f15, rd==x0,fs1 == 0 and fe1 == 0x3fc and fm1 == 0x08574923b869b and fcsr == 0x80 and rm_val == 7
/* opcode: fcvt.wu.d ; op1:f15; dest:x0; op1val:0x3fc08574923b869b; valaddr_reg:x5;
val_offset:19*FLEN/8; rmval:dyn; correctval:??; testreg:x13;
fcsr_val:128*/
TEST_FPID_OP(fcvt.wu.d, x0, f15, dyn, 128, 0, x5, 19*FLEN/8, x19, x4, x13,FLREG)
inst_20:// rs1==f5, rd==x8,fs1 == 0 and fe1 == 0x3fc and fm1 == 0x08574923b869c and fcsr == 0x0 and rm_val == 7
/* opcode: fcvt.wu.d ; op1:f5; dest:x8; op1val:0x3fc08574923b869c; valaddr_reg:x5;
val_offset:20*FLEN/8; rmval:dyn; correctval:??; testreg:x13;
fcsr_val:0*/
TEST_FPID_OP(fcvt.wu.d, x8, f5, dyn, 0, 0, x5, 20*FLEN/8, x19, x4, x13,FLREG)
inst_21:// rs1==f10, rd==x6,fs1 == 0 and fe1 == 0x3fc and fm1 == 0x08574923b869c and fcsr == 0x20 and rm_val == 7
/* opcode: fcvt.wu.d ; op1:f10; dest:x6; op1val:0x3fc08574923b869c; valaddr_reg:x5;
val_offset:21*FLEN/8; rmval:dyn; correctval:??; testreg:x13;
fcsr_val:32*/
TEST_FPID_OP(fcvt.wu.d, x6, f10, dyn, 32, 0, x5, 21*FLEN/8, x19, x4, x13,FLREG)
inst_22:// rs1==f22, rd==x16,fs1 == 0 and fe1 == 0x3fc and fm1 == 0x08574923b869c and fcsr == 0x40 and rm_val == 7
/* opcode: fcvt.wu.d ; op1:f22; dest:x16; op1val:0x3fc08574923b869c; valaddr_reg:x5;
val_offset:22*FLEN/8; rmval:dyn; correctval:??; testreg:x13;
fcsr_val:64*/
TEST_FPID_OP(fcvt.wu.d, x16, f22, dyn, 64, 0, x5, 22*FLEN/8, x19, x4, x13,FLREG)
inst_23:// rs1==f2, rd==x12,fs1 == 0 and fe1 == 0x3fc and fm1 == 0x08574923b869c and fcsr == 0x60 and rm_val == 7
/* opcode: fcvt.wu.d ; op1:f2; dest:x12; op1val:0x3fc08574923b869c; valaddr_reg:x5;
val_offset:23*FLEN/8; rmval:dyn; correctval:??; testreg:x13;
fcsr_val:96*/
TEST_FPID_OP(fcvt.wu.d, x12, f2, dyn, 96, 0, x5, 23*FLEN/8, x19, x4, x13,FLREG)
inst_24:// rs1==f7, rd==x3,fs1 == 0 and fe1 == 0x3fc and fm1 == 0x08574923b869c and fcsr == 0x80 and rm_val == 7
/* opcode: fcvt.wu.d ; op1:f7; dest:x3; op1val:0x3fc08574923b869c; valaddr_reg:x5;
val_offset:24*FLEN/8; rmval:dyn; correctval:??; testreg:x13;
fcsr_val:128*/
TEST_FPID_OP(fcvt.wu.d, x3, f7, dyn, 128, 0, x5, 24*FLEN/8, x19, x4, x13,FLREG)
RVTEST_VALBASEUPD(x3,test_dataset_1)
inst_25:// rs1==f31, rd==x31,fs1 == 0 and fe1 == 0x3fc and fm1 == 0x08574923b869d and fcsr == 0x0 and rm_val == 7
/* opcode: fcvt.wu.d ; op1:f31; dest:x31; op1val:0x3fc08574923b869d; valaddr_reg:x3;
val_offset:0*FLEN/8; rmval:dyn; correctval:??; testreg:x13;
fcsr_val:0*/
TEST_FPID_OP(fcvt.wu.d, x31, f31, dyn, 0, 0, x3, 0*FLEN/8, x6, x4, x13,FLREG)
inst_26:// rs1==f18, rd==x5,fs1 == 0 and fe1 == 0x3fc and fm1 == 0x08574923b869d and fcsr == 0x20 and rm_val == 7
/* opcode: fcvt.wu.d ; op1:f18; dest:x5; op1val:0x3fc08574923b869d; valaddr_reg:x3;
val_offset:1*FLEN/8; rmval:dyn; correctval:??; testreg:x13;
fcsr_val:32*/
TEST_FPID_OP(fcvt.wu.d, x5, f18, dyn, 32, 0, x3, 1*FLEN/8, x6, x4, x13,FLREG)
inst_27:// rs1==f23, rd==x21,fs1 == 0 and fe1 == 0x3fc and fm1 == 0x08574923b869d and fcsr == 0x40 and rm_val == 7
/* opcode: fcvt.wu.d ; op1:f23; dest:x21; op1val:0x3fc08574923b869d; valaddr_reg:x3;
val_offset:2*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
fcsr_val:64*/
TEST_FPID_OP(fcvt.wu.d, x21, f23, dyn, 64, 0, x3, 2*FLEN/8, x6, x4, x2,FLREG)
RVTEST_SIGBASE(x1,signature_x1_0)
inst_28:// rs1==f11, rd==x13,fs1 == 0 and fe1 == 0x3fc and fm1 == 0x08574923b869d and fcsr == 0x60 and rm_val == 7
/* opcode: fcvt.wu.d ; op1:f11; dest:x13; op1val:0x3fc08574923b869d; valaddr_reg:x3;
val_offset:3*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
fcsr_val:96*/
TEST_FPID_OP(fcvt.wu.d, x13, f11, dyn, 96, 0, x3, 3*FLEN/8, x6, x1, x2,FLREG)
inst_29:// rs1==f20, rd==x4,fs1 == 0 and fe1 == 0x3fc and fm1 == 0x08574923b869d and fcsr == 0x80 and rm_val == 7
/* opcode: fcvt.wu.d ; op1:f20; dest:x4; op1val:0x3fc08574923b869d; valaddr_reg:x3;
val_offset:4*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
fcsr_val:128*/
TEST_FPID_OP(fcvt.wu.d, x4, f20, dyn, 128, 0, x3, 4*FLEN/8, x6, x1, x2,FLREG)
inst_30:// rs1==f9, rd==x19,fs1 == 0 and fe1 == 0x3fc and fm1 == 0x08574923b869e and fcsr == 0x0 and rm_val == 7
/* opcode: fcvt.wu.d ; op1:f9; dest:x19; op1val:0x3fc08574923b869e; valaddr_reg:x3;
val_offset:5*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
fcsr_val:0*/
TEST_FPID_OP(fcvt.wu.d, x19, f9, dyn, 0, 0, x3, 5*FLEN/8, x6, x1, x2,FLREG)
inst_31:// rs1==f19, rd==x30,fs1 == 0 and fe1 == 0x3fc and fm1 == 0x08574923b869e and fcsr == 0x20 and rm_val == 7
/* opcode: fcvt.wu.d ; op1:f19; dest:x30; op1val:0x3fc08574923b869e; valaddr_reg:x3;
val_offset:6*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
fcsr_val:32*/
TEST_FPID_OP(fcvt.wu.d, x30, f19, dyn, 32, 0, x3, 6*FLEN/8, x6, x1, x2,FLREG)
inst_32:// fs1 == 0 and fe1 == 0x3fc and fm1 == 0x08574923b869e and fcsr == 0x40 and rm_val == 7
/* opcode: fcvt.wu.d ; op1:f31; dest:x31; op1val:0x3fc08574923b869e; valaddr_reg:x3;
val_offset:7*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
fcsr_val:64*/
TEST_FPID_OP(fcvt.wu.d, x31, f31, dyn, 64, 0, x3, 7*FLEN/8, x6, x1, x2,FLREG)
inst_33:// fs1 == 0 and fe1 == 0x3fc and fm1 == 0x08574923b869e and fcsr == 0x60 and rm_val == 7
/* opcode: fcvt.wu.d ; op1:f31; dest:x31; op1val:0x3fc08574923b869e; valaddr_reg:x3;
val_offset:8*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
fcsr_val:96*/
TEST_FPID_OP(fcvt.wu.d, x31, f31, dyn, 96, 0, x3, 8*FLEN/8, x6, x1, x2,FLREG)
inst_34:// fs1 == 0 and fe1 == 0x3fc and fm1 == 0x08574923b869e and fcsr == 0x80 and rm_val == 7
/* opcode: fcvt.wu.d ; op1:f31; dest:x31; op1val:0x3fc08574923b869e; valaddr_reg:x3;
val_offset:9*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
fcsr_val:128*/
TEST_FPID_OP(fcvt.wu.d, x31, f31, dyn, 128, 0, x3, 9*FLEN/8, x6, x1, x2,FLREG)
inst_35:// fs1 == 0 and fe1 == 0x3fc and fm1 == 0x08574923b869f and fcsr == 0x0 and rm_val == 7
/* opcode: fcvt.wu.d ; op1:f31; dest:x31; op1val:0x3fc08574923b869f; valaddr_reg:x3;
val_offset:10*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
fcsr_val:0*/
TEST_FPID_OP(fcvt.wu.d, x31, f31, dyn, 0, 0, x3, 10*FLEN/8, x6, x1, x2,FLREG)
inst_36:// fs1 == 0 and fe1 == 0x3fc and fm1 == 0x08574923b869f and fcsr == 0x20 and rm_val == 7
/* opcode: fcvt.wu.d ; op1:f31; dest:x31; op1val:0x3fc08574923b869f; valaddr_reg:x3;
val_offset:11*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
fcsr_val:32*/
TEST_FPID_OP(fcvt.wu.d, x31, f31, dyn, 32, 0, x3, 11*FLEN/8, x6, x1, x2,FLREG)
inst_37:// fs1 == 0 and fe1 == 0x3fc and fm1 == 0x08574923b869f and fcsr == 0x40 and rm_val == 7
/* opcode: fcvt.wu.d ; op1:f31; dest:x31; op1val:0x3fc08574923b869f; valaddr_reg:x3;
val_offset:12*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
fcsr_val:64*/
TEST_FPID_OP(fcvt.wu.d, x31, f31, dyn, 64, 0, x3, 12*FLEN/8, x6, x1, x2,FLREG)
inst_38:// fs1 == 0 and fe1 == 0x3fc and fm1 == 0x08574923b869f and fcsr == 0x60 and rm_val == 7
/* opcode: fcvt.wu.d ; op1:f31; dest:x31; op1val:0x3fc08574923b869f; valaddr_reg:x3;
val_offset:13*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
fcsr_val:96*/
TEST_FPID_OP(fcvt.wu.d, x31, f31, dyn, 96, 0, x3, 13*FLEN/8, x6, x1, x2,FLREG)
inst_39:// fs1 == 0 and fe1 == 0x3fc and fm1 == 0x08574923b869f and fcsr == 0x80 and rm_val == 7
/* opcode: fcvt.wu.d ; op1:f31; dest:x31; op1val:0x3fc08574923b869f; valaddr_reg:x3;
val_offset:14*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
fcsr_val:128*/
TEST_FPID_OP(fcvt.wu.d, x31, f31, dyn, 128, 0, x3, 14*FLEN/8, x6, x1, x2,FLREG)
inst_40:// fs1 == 1 and fe1 == 0x3fc and fm1 == 0x08574923b8698 and fcsr == 0x0 and rm_val == 7
/* opcode: fcvt.wu.d ; op1:f31; dest:x31; op1val:0xbfc08574923b8698; valaddr_reg:x3;
val_offset:15*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
fcsr_val:0*/
TEST_FPID_OP(fcvt.wu.d, x31, f31, dyn, 0, 0, x3, 15*FLEN/8, x6, x1, x2,FLREG)
inst_41:// fs1 == 1 and fe1 == 0x3fc and fm1 == 0x08574923b8698 and fcsr == 0x20 and rm_val == 7
/* opcode: fcvt.wu.d ; op1:f31; dest:x31; op1val:0xbfc08574923b8698; valaddr_reg:x3;
val_offset:16*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
fcsr_val:32*/
TEST_FPID_OP(fcvt.wu.d, x31, f31, dyn, 32, 0, x3, 16*FLEN/8, x6, x1, x2,FLREG)
inst_42:// fs1 == 1 and fe1 == 0x3fc and fm1 == 0x08574923b8698 and fcsr == 0x40 and rm_val == 7
/* opcode: fcvt.wu.d ; op1:f31; dest:x31; op1val:0xbfc08574923b8698; valaddr_reg:x3;
val_offset:17*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
fcsr_val:64*/
TEST_FPID_OP(fcvt.wu.d, x31, f31, dyn, 64, 0, x3, 17*FLEN/8, x6, x1, x2,FLREG)
inst_43:// fs1 == 1 and fe1 == 0x3fc and fm1 == 0x08574923b8698 and fcsr == 0x60 and rm_val == 7
/* opcode: fcvt.wu.d ; op1:f31; dest:x31; op1val:0xbfc08574923b8698; valaddr_reg:x3;
val_offset:18*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
fcsr_val:96*/
TEST_FPID_OP(fcvt.wu.d, x31, f31, dyn, 96, 0, x3, 18*FLEN/8, x6, x1, x2,FLREG)
inst_44:// fs1 == 1 and fe1 == 0x3fc and fm1 == 0x08574923b8698 and fcsr == 0x80 and rm_val == 7
/* opcode: fcvt.wu.d ; op1:f31; dest:x31; op1val:0xbfc08574923b8698; valaddr_reg:x3;
val_offset:19*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
fcsr_val:128*/
TEST_FPID_OP(fcvt.wu.d, x31, f31, dyn, 128, 0, x3, 19*FLEN/8, x6, x1, x2,FLREG)
inst_45:// fs1 == 1 and fe1 == 0x3fc and fm1 == 0x08574923b8699 and fcsr == 0x0 and rm_val == 7
/* opcode: fcvt.wu.d ; op1:f31; dest:x31; op1val:0xbfc08574923b8699; valaddr_reg:x3;
val_offset:20*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
fcsr_val:0*/
TEST_FPID_OP(fcvt.wu.d, x31, f31, dyn, 0, 0, x3, 20*FLEN/8, x6, x1, x2,FLREG)
inst_46:// fs1 == 1 and fe1 == 0x3fc and fm1 == 0x08574923b8699 and fcsr == 0x20 and rm_val == 7
/* opcode: fcvt.wu.d ; op1:f31; dest:x31; op1val:0xbfc08574923b8699; valaddr_reg:x3;
val_offset:21*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
fcsr_val:32*/
TEST_FPID_OP(fcvt.wu.d, x31, f31, dyn, 32, 0, x3, 21*FLEN/8, x6, x1, x2,FLREG)
inst_47:// fs1 == 1 and fe1 == 0x3fc and fm1 == 0x08574923b8699 and fcsr == 0x40 and rm_val == 7
/* opcode: fcvt.wu.d ; op1:f31; dest:x31; op1val:0xbfc08574923b8699; valaddr_reg:x3;
val_offset:22*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
fcsr_val:64*/
TEST_FPID_OP(fcvt.wu.d, x31, f31, dyn, 64, 0, x3, 22*FLEN/8, x6, x1, x2,FLREG)
inst_48:// fs1 == 1 and fe1 == 0x3fc and fm1 == 0x08574923b8699 and fcsr == 0x60 and rm_val == 7
/* opcode: fcvt.wu.d ; op1:f31; dest:x31; op1val:0xbfc08574923b8699; valaddr_reg:x3;
val_offset:23*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
fcsr_val:96*/
TEST_FPID_OP(fcvt.wu.d, x31, f31, dyn, 96, 0, x3, 23*FLEN/8, x6, x1, x2,FLREG)
inst_49:// fs1 == 1 and fe1 == 0x3fc and fm1 == 0x08574923b8699 and fcsr == 0x80 and rm_val == 7
/* opcode: fcvt.wu.d ; op1:f31; dest:x31; op1val:0xbfc08574923b8699; valaddr_reg:x3;
val_offset:24*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
fcsr_val:128*/
TEST_FPID_OP(fcvt.wu.d, x31, f31, dyn, 128, 0, x3, 24*FLEN/8, x6, x1, x2,FLREG)
inst_50:// fs1 == 1 and fe1 == 0x3fc and fm1 == 0x08574923b869a and fcsr == 0x0 and rm_val == 7
/* opcode: fcvt.wu.d ; op1:f31; dest:x31; op1val:0xbfc08574923b869a; valaddr_reg:x3;
val_offset:25*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
fcsr_val:0*/
TEST_FPID_OP(fcvt.wu.d, x31, f31, dyn, 0, 0, x3, 25*FLEN/8, x6, x1, x2,FLREG)
inst_51:// fs1 == 1 and fe1 == 0x3fc and fm1 == 0x08574923b869a and fcsr == 0x20 and rm_val == 7
/* opcode: fcvt.wu.d ; op1:f31; dest:x31; op1val:0xbfc08574923b869a; valaddr_reg:x3;
val_offset:26*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
fcsr_val:32*/
TEST_FPID_OP(fcvt.wu.d, x31, f31, dyn, 32, 0, x3, 26*FLEN/8, x6, x1, x2,FLREG)
inst_52:// fs1 == 1 and fe1 == 0x3fc and fm1 == 0x08574923b869a and fcsr == 0x40 and rm_val == 7
/* opcode: fcvt.wu.d ; op1:f31; dest:x31; op1val:0xbfc08574923b869a; valaddr_reg:x3;
val_offset:27*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
fcsr_val:64*/
TEST_FPID_OP(fcvt.wu.d, x31, f31, dyn, 64, 0, x3, 27*FLEN/8, x6, x1, x2,FLREG)
inst_53:// fs1 == 1 and fe1 == 0x3fc and fm1 == 0x08574923b869a and fcsr == 0x60 and rm_val == 7
/* opcode: fcvt.wu.d ; op1:f31; dest:x31; op1val:0xbfc08574923b869a; valaddr_reg:x3;
val_offset:28*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
fcsr_val:96*/
TEST_FPID_OP(fcvt.wu.d, x31, f31, dyn, 96, 0, x3, 28*FLEN/8, x6, x1, x2,FLREG)
inst_54:// fs1 == 1 and fe1 == 0x3fc and fm1 == 0x08574923b869a and fcsr == 0x80 and rm_val == 7
/* opcode: fcvt.wu.d ; op1:f31; dest:x31; op1val:0xbfc08574923b869a; valaddr_reg:x3;
val_offset:29*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
fcsr_val:128*/
TEST_FPID_OP(fcvt.wu.d, x31, f31, dyn, 128, 0, x3, 29*FLEN/8, x6, x1, x2,FLREG)
inst_55:// fs1 == 1 and fe1 == 0x3fc and fm1 == 0x08574923b869b and fcsr == 0x0 and rm_val == 7
/* opcode: fcvt.wu.d ; op1:f31; dest:x31; op1val:0xbfc08574923b869b; valaddr_reg:x3;
val_offset:30*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
fcsr_val:0*/
TEST_FPID_OP(fcvt.wu.d, x31, f31, dyn, 0, 0, x3, 30*FLEN/8, x6, x1, x2,FLREG)
inst_56:// fs1 == 1 and fe1 == 0x3fc and fm1 == 0x08574923b869b and fcsr == 0x20 and rm_val == 7
/* opcode: fcvt.wu.d ; op1:f31; dest:x31; op1val:0xbfc08574923b869b; valaddr_reg:x3;
val_offset:31*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
fcsr_val:32*/
TEST_FPID_OP(fcvt.wu.d, x31, f31, dyn, 32, 0, x3, 31*FLEN/8, x6, x1, x2,FLREG)
inst_57:// fs1 == 1 and fe1 == 0x3fc and fm1 == 0x08574923b869b and fcsr == 0x40 and rm_val == 7
/* opcode: fcvt.wu.d ; op1:f31; dest:x31; op1val:0xbfc08574923b869b; valaddr_reg:x3;
val_offset:32*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
fcsr_val:64*/
TEST_FPID_OP(fcvt.wu.d, x31, f31, dyn, 64, 0, x3, 32*FLEN/8, x6, x1, x2,FLREG)
inst_58:// fs1 == 1 and fe1 == 0x3fc and fm1 == 0x08574923b869b and fcsr == 0x60 and rm_val == 7
/* opcode: fcvt.wu.d ; op1:f31; dest:x31; op1val:0xbfc08574923b869b; valaddr_reg:x3;
val_offset:33*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
fcsr_val:96*/
TEST_FPID_OP(fcvt.wu.d, x31, f31, dyn, 96, 0, x3, 33*FLEN/8, x6, x1, x2,FLREG)
inst_59:// fs1 == 1 and fe1 == 0x3fc and fm1 == 0x08574923b869b and fcsr == 0x80 and rm_val == 7
/* opcode: fcvt.wu.d ; op1:f31; dest:x31; op1val:0xbfc08574923b869b; valaddr_reg:x3;
val_offset:34*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
fcsr_val:128*/
TEST_FPID_OP(fcvt.wu.d, x31, f31, dyn, 128, 0, x3, 34*FLEN/8, x6, x1, x2,FLREG)
inst_60:// fs1 == 1 and fe1 == 0x3fc and fm1 == 0x08574923b869c and fcsr == 0x0 and rm_val == 7
/* opcode: fcvt.wu.d ; op1:f31; dest:x31; op1val:0xbfc08574923b869c; valaddr_reg:x3;
val_offset:35*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
fcsr_val:0*/
TEST_FPID_OP(fcvt.wu.d, x31, f31, dyn, 0, 0, x3, 35*FLEN/8, x6, x1, x2,FLREG)
inst_61:// fs1 == 1 and fe1 == 0x3fc and fm1 == 0x08574923b869c and fcsr == 0x20 and rm_val == 7
/* opcode: fcvt.wu.d ; op1:f31; dest:x31; op1val:0xbfc08574923b869c; valaddr_reg:x3;
val_offset:36*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
fcsr_val:32*/
TEST_FPID_OP(fcvt.wu.d, x31, f31, dyn, 32, 0, x3, 36*FLEN/8, x6, x1, x2,FLREG)
inst_62:// fs1 == 1 and fe1 == 0x3fc and fm1 == 0x08574923b869c and fcsr == 0x40 and rm_val == 7
/* opcode: fcvt.wu.d ; op1:f31; dest:x31; op1val:0xbfc08574923b869c; valaddr_reg:x3;
val_offset:37*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
fcsr_val:64*/
TEST_FPID_OP(fcvt.wu.d, x31, f31, dyn, 64, 0, x3, 37*FLEN/8, x6, x1, x2,FLREG)
inst_63:// fs1 == 1 and fe1 == 0x3fc and fm1 == 0x08574923b869c and fcsr == 0x60 and rm_val == 7
/* opcode: fcvt.wu.d ; op1:f31; dest:x31; op1val:0xbfc08574923b869c; valaddr_reg:x3;
val_offset:38*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
fcsr_val:96*/
TEST_FPID_OP(fcvt.wu.d, x31, f31, dyn, 96, 0, x3, 38*FLEN/8, x6, x1, x2,FLREG)
inst_64:// fs1 == 1 and fe1 == 0x3fc and fm1 == 0x08574923b869c and fcsr == 0x80 and rm_val == 7
/* opcode: fcvt.wu.d ; op1:f31; dest:x31; op1val:0xbfc08574923b869c; valaddr_reg:x3;
val_offset:39*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
fcsr_val:128*/
TEST_FPID_OP(fcvt.wu.d, x31, f31, dyn, 128, 0, x3, 39*FLEN/8, x6, x1, x2,FLREG)
inst_65:// fs1 == 1 and fe1 == 0x3fc and fm1 == 0x08574923b869d and fcsr == 0x0 and rm_val == 7
/* opcode: fcvt.wu.d ; op1:f31; dest:x31; op1val:0xbfc08574923b869d; valaddr_reg:x3;
val_offset:40*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
fcsr_val:0*/
TEST_FPID_OP(fcvt.wu.d, x31, f31, dyn, 0, 0, x3, 40*FLEN/8, x6, x1, x2,FLREG)
inst_66:// fs1 == 1 and fe1 == 0x3fc and fm1 == 0x08574923b869d and fcsr == 0x20 and rm_val == 7
/* opcode: fcvt.wu.d ; op1:f31; dest:x31; op1val:0xbfc08574923b869d; valaddr_reg:x3;
val_offset:41*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
fcsr_val:32*/
TEST_FPID_OP(fcvt.wu.d, x31, f31, dyn, 32, 0, x3, 41*FLEN/8, x6, x1, x2,FLREG)
inst_67:// fs1 == 1 and fe1 == 0x3fc and fm1 == 0x08574923b869d and fcsr == 0x40 and rm_val == 7
/* opcode: fcvt.wu.d ; op1:f31; dest:x31; op1val:0xbfc08574923b869d; valaddr_reg:x3;
val_offset:42*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
fcsr_val:64*/
TEST_FPID_OP(fcvt.wu.d, x31, f31, dyn, 64, 0, x3, 42*FLEN/8, x6, x1, x2,FLREG)
inst_68:// fs1 == 1 and fe1 == 0x3fc and fm1 == 0x08574923b869d and fcsr == 0x60 and rm_val == 7
/* opcode: fcvt.wu.d ; op1:f31; dest:x31; op1val:0xbfc08574923b869d; valaddr_reg:x3;
val_offset:43*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
fcsr_val:96*/
TEST_FPID_OP(fcvt.wu.d, x31, f31, dyn, 96, 0, x3, 43*FLEN/8, x6, x1, x2,FLREG)
inst_69:// fs1 == 1 and fe1 == 0x3fc and fm1 == 0x08574923b869d and fcsr == 0x80 and rm_val == 7
/* opcode: fcvt.wu.d ; op1:f31; dest:x31; op1val:0xbfc08574923b869d; valaddr_reg:x3;
val_offset:44*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
fcsr_val:128*/
TEST_FPID_OP(fcvt.wu.d, x31, f31, dyn, 128, 0, x3, 44*FLEN/8, x6, x1, x2,FLREG)
inst_70:// fs1 == 1 and fe1 == 0x3fc and fm1 == 0x08574923b869e and fcsr == 0x0 and rm_val == 7
/* opcode: fcvt.wu.d ; op1:f31; dest:x31; op1val:0xbfc08574923b869e; valaddr_reg:x3;
val_offset:45*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
fcsr_val:0*/
TEST_FPID_OP(fcvt.wu.d, x31, f31, dyn, 0, 0, x3, 45*FLEN/8, x6, x1, x2,FLREG)
inst_71:// fs1 == 1 and fe1 == 0x3fc and fm1 == 0x08574923b869e and fcsr == 0x20 and rm_val == 7
/* opcode: fcvt.wu.d ; op1:f31; dest:x31; op1val:0xbfc08574923b869e; valaddr_reg:x3;
val_offset:46*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
fcsr_val:32*/
TEST_FPID_OP(fcvt.wu.d, x31, f31, dyn, 32, 0, x3, 46*FLEN/8, x6, x1, x2,FLREG)
inst_72:// fs1 == 1 and fe1 == 0x3fc and fm1 == 0x08574923b869e and fcsr == 0x40 and rm_val == 7
/* opcode: fcvt.wu.d ; op1:f31; dest:x31; op1val:0xbfc08574923b869e; valaddr_reg:x3;
val_offset:47*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
fcsr_val:64*/
TEST_FPID_OP(fcvt.wu.d, x31, f31, dyn, 64, 0, x3, 47*FLEN/8, x6, x1, x2,FLREG)
inst_73:// fs1 == 1 and fe1 == 0x3fc and fm1 == 0x08574923b869e and fcsr == 0x60 and rm_val == 7
/* opcode: fcvt.wu.d ; op1:f31; dest:x31; op1val:0xbfc08574923b869e; valaddr_reg:x3;
val_offset:48*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
fcsr_val:96*/
TEST_FPID_OP(fcvt.wu.d, x31, f31, dyn, 96, 0, x3, 48*FLEN/8, x6, x1, x2,FLREG)
inst_74:// fs1 == 1 and fe1 == 0x3fc and fm1 == 0x08574923b869e and fcsr == 0x80 and rm_val == 7
/* opcode: fcvt.wu.d ; op1:f31; dest:x31; op1val:0xbfc08574923b869e; valaddr_reg:x3;
val_offset:49*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
fcsr_val:128*/
TEST_FPID_OP(fcvt.wu.d, x31, f31, dyn, 128, 0, x3, 49*FLEN/8, x6, x1, x2,FLREG)
inst_75:// fs1 == 1 and fe1 == 0x3fc and fm1 == 0x08574923b869f and fcsr == 0x0 and rm_val == 7
/* opcode: fcvt.wu.d ; op1:f31; dest:x31; op1val:0xbfc08574923b869f; valaddr_reg:x3;
val_offset:50*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
fcsr_val:0*/
TEST_FPID_OP(fcvt.wu.d, x31, f31, dyn, 0, 0, x3, 50*FLEN/8, x6, x1, x2,FLREG)
inst_76:// fs1 == 1 and fe1 == 0x3fc and fm1 == 0x08574923b869f and fcsr == 0x20 and rm_val == 7
/* opcode: fcvt.wu.d ; op1:f31; dest:x31; op1val:0xbfc08574923b869f; valaddr_reg:x3;
val_offset:51*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
fcsr_val:32*/
TEST_FPID_OP(fcvt.wu.d, x31, f31, dyn, 32, 0, x3, 51*FLEN/8, x6, x1, x2,FLREG)
inst_77:// fs1 == 1 and fe1 == 0x3fc and fm1 == 0x08574923b869f and fcsr == 0x40 and rm_val == 7
/* opcode: fcvt.wu.d ; op1:f31; dest:x31; op1val:0xbfc08574923b869f; valaddr_reg:x3;
val_offset:52*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
fcsr_val:64*/
TEST_FPID_OP(fcvt.wu.d, x31, f31, dyn, 64, 0, x3, 52*FLEN/8, x6, x1, x2,FLREG)
inst_78:// fs1 == 1 and fe1 == 0x3fc and fm1 == 0x08574923b869f and fcsr == 0x60 and rm_val == 7
/* opcode: fcvt.wu.d ; op1:f31; dest:x31; op1val:0xbfc08574923b869f; valaddr_reg:x3;
val_offset:53*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
fcsr_val:96*/
TEST_FPID_OP(fcvt.wu.d, x31, f31, dyn, 96, 0, x3, 53*FLEN/8, x6, x1, x2,FLREG)
inst_79:// fs1 == 1 and fe1 == 0x3fc and fm1 == 0x08574923b869f and fcsr == 0x80 and rm_val == 7
/* opcode: fcvt.wu.d ; op1:f31; dest:x31; op1val:0xbfc08574923b869f; valaddr_reg:x3;
val_offset:54*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
fcsr_val:128*/
TEST_FPID_OP(fcvt.wu.d, x31, f31, dyn, 128, 0, x3, 54*FLEN/8, x6, x1, x2,FLREG)
inst_80:// fs1 == 0 and fe1 == 0x3fc and fm1 == 0x08574923b869b and fcsr == 0x80 and rm_val == 7
/* opcode: fcvt.wu.d ; op1:f31; dest:x31; op1val:0x3fc08574923b869b; valaddr_reg:x3;
val_offset:55*FLEN/8; rmval:dyn; correctval:??; testreg:x2;
fcsr_val:128*/
TEST_FPID_OP(fcvt.wu.d, x31, f31, dyn, 128, 0, x3, 55*FLEN/8, x6, x1, x2,FLREG)
#endif
RVTEST_CODE_END
RVMODEL_HALT
RVTEST_DATA_BEGIN
.align 4
rvtest_data:
.word 0xbabecafe
.word 0xabecafeb
.word 0xbecafeba
.word 0xecafebab
test_dataset_0:
NAN_BOXED(4593818355633981080,64,FLEN)
NAN_BOXED(4593818355633981080,64,FLEN)
NAN_BOXED(4593818355633981080,64,FLEN)
NAN_BOXED(4593818355633981080,64,FLEN)
NAN_BOXED(4593818355633981080,64,FLEN)
NAN_BOXED(4593818355633981081,64,FLEN)
NAN_BOXED(4593818355633981081,64,FLEN)
NAN_BOXED(4593818355633981081,64,FLEN)
NAN_BOXED(4593818355633981081,64,FLEN)
NAN_BOXED(4593818355633981081,64,FLEN)
NAN_BOXED(4593818355633981082,64,FLEN)
NAN_BOXED(4593818355633981082,64,FLEN)
NAN_BOXED(4593818355633981082,64,FLEN)
NAN_BOXED(4593818355633981082,64,FLEN)
NAN_BOXED(4593818355633981082,64,FLEN)
NAN_BOXED(4593818355633981083,64,FLEN)
NAN_BOXED(4593818355633981083,64,FLEN)
NAN_BOXED(4593818355633981083,64,FLEN)
NAN_BOXED(4593818355633981083,64,FLEN)
NAN_BOXED(4593818355633981083,64,FLEN)
NAN_BOXED(4593818355633981084,64,FLEN)
NAN_BOXED(4593818355633981084,64,FLEN)
NAN_BOXED(4593818355633981084,64,FLEN)
NAN_BOXED(4593818355633981084,64,FLEN)
NAN_BOXED(4593818355633981084,64,FLEN)
test_dataset_1:
NAN_BOXED(4593818355633981085,64,FLEN)
NAN_BOXED(4593818355633981085,64,FLEN)
NAN_BOXED(4593818355633981085,64,FLEN)
NAN_BOXED(4593818355633981085,64,FLEN)
NAN_BOXED(4593818355633981085,64,FLEN)
NAN_BOXED(4593818355633981086,64,FLEN)
NAN_BOXED(4593818355633981086,64,FLEN)
NAN_BOXED(4593818355633981086,64,FLEN)
NAN_BOXED(4593818355633981086,64,FLEN)
NAN_BOXED(4593818355633981086,64,FLEN)
NAN_BOXED(4593818355633981087,64,FLEN)
NAN_BOXED(4593818355633981087,64,FLEN)
NAN_BOXED(4593818355633981087,64,FLEN)
NAN_BOXED(4593818355633981087,64,FLEN)
NAN_BOXED(4593818355633981087,64,FLEN)
NAN_BOXED(13817190392488756888,64,FLEN)
NAN_BOXED(13817190392488756888,64,FLEN)
NAN_BOXED(13817190392488756888,64,FLEN)
NAN_BOXED(13817190392488756888,64,FLEN)
NAN_BOXED(13817190392488756888,64,FLEN)
NAN_BOXED(13817190392488756889,64,FLEN)
NAN_BOXED(13817190392488756889,64,FLEN)
NAN_BOXED(13817190392488756889,64,FLEN)
NAN_BOXED(13817190392488756889,64,FLEN)
NAN_BOXED(13817190392488756889,64,FLEN)
NAN_BOXED(13817190392488756890,64,FLEN)
NAN_BOXED(13817190392488756890,64,FLEN)
NAN_BOXED(13817190392488756890,64,FLEN)
NAN_BOXED(13817190392488756890,64,FLEN)
NAN_BOXED(13817190392488756890,64,FLEN)
NAN_BOXED(13817190392488756891,64,FLEN)
NAN_BOXED(13817190392488756891,64,FLEN)
NAN_BOXED(13817190392488756891,64,FLEN)
NAN_BOXED(13817190392488756891,64,FLEN)
NAN_BOXED(13817190392488756891,64,FLEN)
NAN_BOXED(13817190392488756892,64,FLEN)
NAN_BOXED(13817190392488756892,64,FLEN)
NAN_BOXED(13817190392488756892,64,FLEN)
NAN_BOXED(13817190392488756892,64,FLEN)
NAN_BOXED(13817190392488756892,64,FLEN)
NAN_BOXED(13817190392488756893,64,FLEN)
NAN_BOXED(13817190392488756893,64,FLEN)
NAN_BOXED(13817190392488756893,64,FLEN)
NAN_BOXED(13817190392488756893,64,FLEN)
NAN_BOXED(13817190392488756893,64,FLEN)
NAN_BOXED(13817190392488756894,64,FLEN)
NAN_BOXED(13817190392488756894,64,FLEN)
NAN_BOXED(13817190392488756894,64,FLEN)
NAN_BOXED(13817190392488756894,64,FLEN)
NAN_BOXED(13817190392488756894,64,FLEN)
NAN_BOXED(13817190392488756895,64,FLEN)
NAN_BOXED(13817190392488756895,64,FLEN)
NAN_BOXED(13817190392488756895,64,FLEN)
NAN_BOXED(13817190392488756895,64,FLEN)
NAN_BOXED(13817190392488756895,64,FLEN)
NAN_BOXED(4593818355633981083,64,FLEN)
RVTEST_DATA_END
RVMODEL_DATA_BEGIN
rvtest_sig_begin:
sig_begin_canary:
CANARY;
signature_x4_0:
.fill 0*((SIGALIGN)/4),4,0xdeadbeef
signature_x4_1:
.fill 56*((SIGALIGN)/4),4,0xdeadbeef
signature_x1_0:
.fill 106*((SIGALIGN)/4),4,0xdeadbeef
#ifdef rvtest_mtrap_routine
tsig_begin_canary:
CANARY;
tsig_begin_canary:
CANARY;
mtrap_sigptr:
.fill 64*(XLEN/32),4,0xdeadbeef
tsig_end_canary:
CANARY;
tsig_end_canary:
CANARY;
#endif
#ifdef rvtest_gpr_save
gpr_save:
.fill 32*XLEN/32,4,0xdeadbeef
#endif
sig_end_canary:
CANARY;
rvtest_sig_end:
RVMODEL_DATA_END

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// -----------
// This file was generated by riscv_ctg (https://github.com/riscv-software-src/riscv-ctg)
// version : 0.7.1
// timestamp : Mon Aug 8 15:50:32 2022 GMT
// usage : riscv_ctg \
// -- cgf // --cgf /home/sharder/git/riscv/riscv-ctg/sample_cgfs/dataset.cgf \
// --cgf /home/sharder/git/riscv/riscv-ctg/sample_cgfs/sample_cgfs_fext/RV32F/flw-align.cgf \
// --cgf /home/sharder/git/riscv/riscv-ctg/sample_cgfs/sample_cgfs_fext/RV32F/fsw-align.cgf \
// --cgf /home/sharder/git/riscv/riscv-ctg/sample_cgfs/sample_cgfs_fext/RV32D/fsd-align.cgf \
// --cgf /home/sharder/git/riscv/riscv-ctg/sample_cgfs/sample_cgfs_fext/RV32D/fld-align.cgf \
\
// -- xlen 32 \
// --randomize \
// -----------
//
// -----------
// Copyright (c) 2020. RISC-V International. All rights reserved.
// SPDX-License-Identifier: BSD-3-Clause
// -----------
//
// This assembly file tests the fld instruction of the RISC-V RV32FD_Zicsr,RV64FD_Zicsr extension for the fld-align covergroup.
//
#include "model_test.h"
#include "arch_test.h"
RVTEST_ISA("RV32IFD_Zicsr,RV64IFD_Zicsr")
.section .text.init
.org 0x80
.globl rvtest_entry_point
rvtest_entry_point:
RVMODEL_BOOT
RVTEST_CODE_BEGIN
#ifdef TEST_CASE_1
RVTEST_CASE(0,"//check ISA:=regex(.*D.*);def TEST_CASE_1=True;",fld-align)
RVTEST_FP_ENABLE()
RVTEST_VALBASEUPD(x7,test_dataset_0)
RVTEST_SIGBASE(x16,signature_x16_1)
inst_0:// rs1==x28, rd==f27,ea_align == 0 and (imm_val % 8) == 0 and fcsr == 0, imm_val < 0 and fcsr == 0
// opcode:fld op1:x28; dest:f27; immval:-0x400; align:0; flagreg:$flag_reg
TEST_LOAD_F(x16,x18,0,x28,f27,-0x400,fld,0,x21)
inst_1:// rs1==x9, rd==f12,ea_align == 0 and (imm_val % 8) == 1 and fcsr == 0, imm_val > 0 and fcsr == 0
// opcode:fld op1:x9; dest:f12; immval:0x1; align:0; flagreg:$flag_reg
TEST_LOAD_F(x16,x18,0,x9,f12,0x1,fld,0,x21)
inst_2:// rs1==x13, rd==f15,ea_align == 0 and (imm_val % 8) == 2 and fcsr == 0,
// opcode:fld op1:x13; dest:f15; immval:-0x6; align:0; flagreg:$flag_reg
TEST_LOAD_F(x16,x18,0,x13,f15,-0x6,fld,0,x21)
inst_3:// rs1==x17, rd==f4,ea_align == 0 and (imm_val % 8) == 3 and fcsr == 0,
// opcode:fld op1:x17; dest:f4; immval:-0x5; align:0; flagreg:$flag_reg
TEST_LOAD_F(x16,x18,0,x17,f4,-0x5,fld,0,x21)
inst_4:// rs1==x31, rd==f14,ea_align == 0 and (imm_val % 8) == 4 and fcsr == 0,
// opcode:fld op1:x31; dest:f14; immval:0x4; align:0; flagreg:$flag_reg
TEST_LOAD_F(x16,x18,0,x31,f14,0x4,fld,0,x21)
inst_5:// rs1==x14, rd==f6,imm_val == 0 and fcsr == 0,
// opcode:fld op1:x14; dest:f6; immval:0x0; align:0; flagreg:$flag_reg
TEST_LOAD_F(x16,x18,0,x14,f6,0x0,fld,0,x21)
inst_6:// rs1==x11, rd==f0,ea_align == 0 and (imm_val % 8) == 5 and fcsr == 0,
// opcode:fld op1:x11; dest:f0; immval:-0x3; align:0; flagreg:$flag_reg
TEST_LOAD_F(x16,x18,0,x11,f0,-0x3,fld,0,x21)
inst_7:// rs1==x3, rd==f28,ea_align == 0 and (imm_val % 8) == 6 and fcsr == 0,
// opcode:fld op1:x3; dest:f28; immval:-0x2; align:0; flagreg:$flag_reg
TEST_LOAD_F(x16,x18,0,x3,f28,-0x2,fld,0,x21)
inst_8:// rs1==x5, rd==f29,ea_align == 0 and (imm_val % 8) == 7 and fcsr == 0,
// opcode:fld op1:x5; dest:f29; immval:-0x81; align:0; flagreg:$flag_reg
TEST_LOAD_F(x16,x18,0,x5,f29,-0x81,fld,0,x21)
inst_9:// rs1==x4, rd==f19,
// opcode:fld op1:x4; dest:f19; immval:-0x800; align:0; flagreg:$flag_reg
TEST_LOAD_F(x16,x18,0,x4,f19,-0x800,fld,0,x21)
inst_10:// rs1==x22, rd==f5,
// opcode:fld op1:x22; dest:f5; immval:-0x800; align:0; flagreg:$flag_reg
TEST_LOAD_F(x16,x18,0,x22,f5,-0x800,fld,0,x21)
inst_11:// rs1==x2, rd==f10,
// opcode:fld op1:x2; dest:f10; immval:-0x800; align:0; flagreg:$flag_reg
TEST_LOAD_F(x16,x18,0,x2,f10,-0x800,fld,0,x21)
inst_12:// rs1==x10, rd==f16,
// opcode:fld op1:x10; dest:f16; immval:-0x800; align:0; flagreg:$flag_reg
TEST_LOAD_F(x16,x18,0,x10,f16,-0x800,fld,0,x21)
inst_13:// rs1==x23, rd==f13,
// opcode:fld op1:x23; dest:f13; immval:-0x800; align:0; flagreg:$flag_reg
TEST_LOAD_F(x16,x18,0,x23,f13,-0x800,fld,0,x21)
inst_14:// rs1==x29, rd==f22,
// opcode:fld op1:x29; dest:f22; immval:-0x800; align:0; flagreg:$flag_reg
TEST_LOAD_F(x16,x18,0,x29,f22,-0x800,fld,0,x21)
inst_15:// rs1==x12, rd==f1,
// opcode:fld op1:x12; dest:f1; immval:-0x800; align:0; flagreg:$flag_reg
TEST_LOAD_F(x16,x18,0,x12,f1,-0x800,fld,0,x21)
inst_16:// rs1==x26, rd==f2,
// opcode:fld op1:x26; dest:f2; immval:-0x800; align:0; flagreg:$flag_reg
TEST_LOAD_F(x16,x18,0,x26,f2,-0x800,fld,0,x21)
inst_17:// rs1==x20, rd==f24,
// opcode:fld op1:x20; dest:f24; immval:-0x800; align:0; flagreg:$flag_reg
TEST_LOAD_F(x16,x18,0,x20,f24,-0x800,fld,0,x21)
inst_18:// rs1==x6, rd==f26,
// opcode:fld op1:x6; dest:f26; immval:-0x800; align:0; flagreg:$flag_reg
TEST_LOAD_F(x16,x18,0,x6,f26,-0x800,fld,0,x21)
inst_19:// rs1==x15, rd==f17,
// opcode:fld op1:x15; dest:f17; immval:-0x800; align:0; flagreg:$flag_reg
TEST_LOAD_F(x16,x18,0,x15,f17,-0x800,fld,0,x21)
inst_20:// rs1==x25, rd==f7,
// opcode:fld op1:x25; dest:f7; immval:-0x800; align:0; flagreg:$flag_reg
TEST_LOAD_F(x16,x18,0,x25,f7,-0x800,fld,0,x21)
inst_21:// rs1==x8, rd==f30,
// opcode:fld op1:x8; dest:f30; immval:-0x800; align:0; flagreg:$flag_reg
TEST_LOAD_F(x16,x18,0,x8,f30,-0x800,fld,0,x21)
inst_22:// rs1==x19, rd==f31,
// opcode:fld op1:x19; dest:f31; immval:-0x800; align:0; flagreg:$flag_reg
TEST_LOAD_F(x16,x18,0,x19,f31,-0x800,fld,0,x21)
inst_23:// rs1==x1, rd==f11,
// opcode:fld op1:x1; dest:f11; immval:-0x800; align:0; flagreg:$flag_reg
TEST_LOAD_F(x16,x18,0,x1,f11,-0x800,fld,0,x21)
RVTEST_VALBASEUPD(x4,test_dataset_1)
inst_24:// rs1==x7, rd==f3,
// opcode:fld op1:x7; dest:f3; immval:-0x800; align:0; flagreg:$flag_reg
TEST_LOAD_F(x16,x18,0,x7,f3,-0x800,fld,0,x5)
inst_25:// rs1==x30, rd==f18,
// opcode:fld op1:x30; dest:f18; immval:-0x800; align:0; flagreg:$flag_reg
TEST_LOAD_F(x16,x18,0,x30,f18,-0x800,fld,0,x5)
inst_26:// rs1==x27, rd==f20,
// opcode:fld op1:x27; dest:f20; immval:-0x800; align:0; flagreg:$flag_reg
TEST_LOAD_F(x16,x3,0,x27,f20,-0x800,fld,0,x5)
RVTEST_SIGBASE(x2,signature_x2_0)
inst_27:// rs1==x21, rd==f8,
// opcode:fld op1:x21; dest:f8; immval:-0x800; align:0; flagreg:$flag_reg
TEST_LOAD_F(x2,x3,0,x21,f8,-0x800,fld,0,x5)
inst_28:// rs1==x18, rd==f21,
// opcode:fld op1:x18; dest:f21; immval:-0x800; align:0; flagreg:$flag_reg
TEST_LOAD_F(x2,x3,0,x18,f21,-0x800,fld,0,x5)
inst_29:// rs1==x24, rd==f23,
// opcode:fld op1:x24; dest:f23; immval:-0x800; align:0; flagreg:$flag_reg
TEST_LOAD_F(x2,x3,0,x24,f23,-0x800,fld,0,x5)
inst_30:// rs1==x16, rd==f9,
// opcode:fld op1:x16; dest:f9; immval:-0x800; align:0; flagreg:$flag_reg
TEST_LOAD_F(x2,x3,0,x16,f9,-0x800,fld,0,x5)
inst_31:// rd==f25,
// opcode:fld op1:x1; dest:f25; immval:-0x800; align:0; flagreg:$flag_reg
TEST_LOAD_F(x2,x3,0,x1,f25,-0x800,fld,0,x5)
#endif
RVTEST_CODE_END
RVMODEL_HALT
RVTEST_DATA_BEGIN
.align 4
rvtest_data:
.word 0xbabecafe
.word 0xabecafeb
.word 0xbecafeba
.word 0xecafebab
test_dataset_0:
test_dataset_1:
RVTEST_DATA_END
RVMODEL_DATA_BEGIN
rvtest_sig_begin:
sig_begin_canary:
CANARY;
signature_x16_0:
.fill 0*((SIGALIGN)/4),4,0xdeadbeef
signature_x16_1:
.fill 54*((SIGALIGN)/4),4,0xdeadbeef
signature_x2_0:
.fill 10*((SIGALIGN)/4),4,0xdeadbeef
#ifdef rvtest_mtrap_routine
tsig_begin_canary:
CANARY;
tsig_begin_canary:
CANARY;
mtrap_sigptr:
.fill 64*(XLEN/32),4,0xdeadbeef
tsig_end_canary:
CANARY;
tsig_end_canary:
CANARY;
#endif
#ifdef rvtest_gpr_save
gpr_save:
.fill 32*XLEN/32,4,0xdeadbeef
#endif
sig_end_canary:
CANARY;
rvtest_sig_end:
RVMODEL_DATA_END

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