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[rtl] Fix counter reset value on FPGA

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If the counter width is >= 49, we do not use a DSP on the FPGA.
Then, we should use an asynchronous reset to initialize the counter.

This bug was detected when enabling the lockstep for the CW340. A
lockstep mismatch happend as the mcycle counters of the main and
shadow core did not match due to this bug.

Signed-off-by: Pascal Nasahl <nasahlpa@lowrisc.org>
This commit is contained in:
Pascal Nasahl 2024-11-27 15:28:06 +01:00 • committed by Pirmin Vogel
parent d2d55ed348
commit 54985d21b0
1 changed files with 12 additions and 9 deletions
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21
rtl/ibex_counter.sv
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@ -51,12 +51,17 @@ module ibex_counter #(
end
`ifdef FPGA_XILINX
// Set DSP pragma for supported xilinx FPGAs
localparam int DspPragma = CounterWidth < 49 ? "yes" : "no";
(* use_dsp = DspPragma *) logic [CounterWidth-1:0] counter_q;
// DSP output register requires synchronous reset.
`define COUNTER_FLOP_RST posedge clk_i
// On Xilinx FPGAs, 48-bit DSPs are available that can be used for the
// counter.
if (CounterWidth < 49) begin : g_dsp_counter
// Set DSP pragma for supported xilinx FPGAs
(* use_dsp = "yes" *) logic [CounterWidth-1:0] counter_q;
// DSP output register requires synchronous reset.
`define COUNTER_FLOP_RST posedge clk_i
end else begin : g_no_dsp_counter
(* use_dsp = "no" *) logic [CounterWidth-1:0] counter_q;
`define COUNTER_FLOP_RST posedge clk_i or negedge rst_ni
end
`else
logic [CounterWidth-1:0] counter_q;
@ -65,6 +70,7 @@ module ibex_counter #(
// Counter flop
always_ff @(`COUNTER_FLOP_RST) begin
`undef COUNTER_FLOP_RST
if (!rst_ni) begin
counter_q <= '0;
end else begin
@ -98,6 +104,3 @@ module ibex_counter #(
assign counter_val_o = counter;
endmodule
// Keep helper defines file-local.
`undef COUNTER_FLOP_RST