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[dv] Add known failure detection to riscv_debug_ebreakmu_test
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1 changed files with 40 additions and 12 deletions
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@ -1055,19 +1055,47 @@ class core_ibex_debug_ebreakmu_test extends core_ibex_directed_test;
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`uvm_component_utils(core_ibex_debug_ebreakmu_test)
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`uvm_component_new
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bit seen_ebreak;
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virtual task send_stimulus();
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seen_ebreak = 0;
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fork
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begin : detect_ebreak
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wait (dut_vif.dut_cb.ebreak === 1'b1);
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seen_ebreak = 1;
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end
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begin : run_stimulus
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core_ibex_directed_test::send_stimulus();
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end
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join
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endtask
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virtual task check_stimulus();
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// send a single debug request after core initialization to configure dcsr
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vseq.start_debug_single_seq();
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check_next_core_status(IN_DEBUG_MODE,
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"Core did not enter debug mode after debug_req stimulus", 2000);
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check_priv_mode(PRIV_LVL_M);
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// Read dcsr and verify the appropriate ebreak(m/s/u) bit has been set based on the prv field,
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// as well as the cause field
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wait_for_csr_write(CSR_DCSR, 500);
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check_dcsr_prv(init_operating_mode);
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check_dcsr_ebreak();
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check_dcsr_cause(DBG_CAUSE_HALTREQ);
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wait_ret("dret", 5000);
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fork begin
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fork
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begin : dbg_setup
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// send a single debug request after core initialization to configure dcsr
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vseq.start_debug_single_seq();
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check_next_core_status(IN_DEBUG_MODE,
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"Core did not enter debug mode after debug_req stimulus", 2000);
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check_priv_mode(PRIV_LVL_M);
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// Read dcsr and verify the appropriate ebreak(m/s/u) bit has been set based on the prv field,
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// as well as the cause field
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wait_for_csr_write(CSR_DCSR, 500);
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check_dcsr_prv(init_operating_mode);
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check_dcsr_ebreak();
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check_dcsr_cause(DBG_CAUSE_HALTREQ);
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wait_ret("dret", 5000);
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end
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begin : detect_ebreak
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wait (seen_ebreak == 1);
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`uvm_fatal(`gfn, {"EBreak seen whilst doing initial debug initialization, KNOWN FAILURE ",
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"SEE https://github.com/lowRISC/ibex/issues/1313"})
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end
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join_any
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disable fork;
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end join
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forever begin
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wait (dut_vif.dut_cb.ebreak === 1'b1);
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check_next_core_status(IN_DEBUG_MODE,
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