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https://github.com/lowRISC/ibex.git
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fixed tracer
This commit is contained in:
Pasquale Davide Schiavone
parent
fe8f4fdf8e
commit
57ee554246
3 changed files with 18 additions and 334 deletions
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@ -368,7 +368,7 @@ module zeroriscy_id_stage
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end
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assign alu_operand_b = operand_b;
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assign operand_b_fw_id = operand_b;
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assign operand_b_fw_id = regfile_data_rb_id;
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/////////////////////////////////////////////////////////
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// ____ _____ ____ ___ ____ _____ _____ ____ ____ //
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@ -688,14 +688,15 @@ module zeroriscy_core
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.compressed ( id_stage_i.is_compressed_i ),
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.id_valid ( id_stage_i.id_valid_o ),
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.is_decoding ( id_stage_i.is_decoding_o ),
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.is_branch ( id_stage_i.branch_in_id ),
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.branch_taken ( id_stage_i.branch_set ),
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.pipe_flush ( id_stage_i.controller_i.pipe_flush_i ),
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.rs1_value ( id_stage_i.operand_a_fw_id ),
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.rs2_value ( id_stage_i.operand_b_fw_id ),
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.rs3_value ( data_wdata_ex ),
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.rs2_value_vec ( id_stage_i.alu_operand_b ),
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.ex_valid ( ),
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.lsu_value ( data_wdata_ex ),
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.ex_reg_addr ( id_stage_i.regfile_waddr_mux ),
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.ex_reg_we ( id_stage_i.regfile_we_mux ),
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.ex_reg_wdata ( id_stage_i.regfile_wdata_mux ),
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@ -704,15 +705,10 @@ module zeroriscy_core
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.ex_data_req ( data_req_o ),
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.ex_data_gnt ( data_gnt_i ),
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.ex_data_we ( data_we_o ),
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// use id_stage_i.regfile_wdata_mux
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.ex_data_wdata ( data_wdata_o ),
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.wb_bypass ( branch_in_ex_o ),
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.wb_valid ( ),
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.wb_reg_addr ( ),
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.wb_reg_we ( ),
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.wb_reg_wdata ( regfile_wdata_lsu ),
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.lsu_reg_wdata ( regfile_wdata_lsu ),
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.imm_u_type ( id_stage_i.imm_u_type ),
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.imm_uj_type ( id_stage_i.imm_uj_type ),
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@ -720,12 +716,7 @@ module zeroriscy_core
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.imm_iz_type ( id_stage_i.imm_iz_type[11:0] ),
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.imm_z_type ( id_stage_i.imm_z_type ),
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.imm_s_type ( id_stage_i.imm_s_type ),
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.imm_sb_type ( id_stage_i.imm_sb_type ),
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.imm_s2_type ( id_stage_i.imm_s2_type ),
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.imm_s3_type ( id_stage_i.imm_s3_type ),
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.imm_vs_type ( id_stage_i.imm_vs_type ),
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.imm_vu_type ( id_stage_i.imm_vu_type ),
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.imm_clip_type ( id_stage_i.instr_rdata_i[11:7] )
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.imm_sb_type ( id_stage_i.imm_sb_type )
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);
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`endif
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@ -53,14 +53,14 @@ module zeroriscy_tracer
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input logic compressed,
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input logic id_valid,
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input logic is_decoding,
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input logic is_branch,
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input logic branch_taken,
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input logic pipe_flush,
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input logic [31:0] rs1_value,
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input logic [31:0] rs2_value,
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input logic [31:0] rs3_value,
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input logic [31:0] rs2_value_vec,
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input logic [31:0] lsu_value,
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input logic ex_valid,
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input logic [(REG_ADDR_WIDTH-1):0] ex_reg_addr,
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input logic ex_reg_we,
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input logic [31:0] ex_reg_wdata,
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@ -71,12 +71,7 @@ module zeroriscy_tracer
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input logic [31:0] ex_data_addr,
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input logic [31:0] ex_data_wdata,
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input logic wb_bypass,
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input logic wb_valid,
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input logic [(REG_ADDR_WIDTH-1):0] wb_reg_addr,
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input logic wb_reg_we,
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input logic [31:0] wb_reg_wdata,
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input logic [31:0] lsu_reg_wdata,
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input logic [31:0] imm_u_type,
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input logic [31:0] imm_uj_type,
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@ -84,12 +79,7 @@ module zeroriscy_tracer
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input logic [11:0] imm_iz_type,
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input logic [31:0] imm_z_type,
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input logic [31:0] imm_s_type,
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input logic [31:0] imm_sb_type,
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input logic [31:0] imm_s2_type,
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input logic [31:0] imm_s3_type,
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input logic [31:0] imm_vs_type,
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input logic [31:0] imm_vu_type,
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input logic [ 4:0] imm_clip_type
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input logic [31:0] imm_sb_type
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);
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integer f;
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@ -180,41 +170,6 @@ module zeroriscy_tracer
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end
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endfunction // printRInstr
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function void printAddNInstr(input string mnemonic);
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begin
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regs_read.push_back('{rs1, rs1_value});
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regs_read.push_back('{rs2, rs2_value});
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regs_write.push_back('{rd, 'x});
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str = $sformatf("%-16s x%0d, x%0d, x%0d, 0x%0d", mnemonic, rd, rs1, rs2, $unsigned(imm_s3_type[4:0]));
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end
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endfunction // printAddNInstr
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function void printR1Instr(input string mnemonic);
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begin
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regs_read.push_back('{rs1, rs1_value});
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regs_write.push_back('{rd, 'x});
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str = $sformatf("%-16s x%0d, x%0d", mnemonic, rd, rs1);
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end
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endfunction // printR1Instr
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function void printR3Instr(input string mnemonic);
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begin
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regs_read.push_back('{rd, rs3_value});
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regs_read.push_back('{rs1, rs1_value});
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regs_read.push_back('{rs2, rs2_value});
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regs_write.push_back('{rd, 'x});
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str = $sformatf("%-16s x%0d, x%0d, x%0d", mnemonic, rd, rs1, rs2);
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end
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endfunction // printR3Instr
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function void printClipInstr(input string mnemonic);
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begin
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regs_read.push_back('{rs1, rs1_value});
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regs_write.push_back('{rd, 'x});
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str = $sformatf("%-16s x%0d, x%0d, %0d", mnemonic, rd, rs1, $unsigned(imm_clip_type));
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end
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endfunction // printRInstr
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function void printIInstr(input string mnemonic);
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begin
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regs_read.push_back('{rs1, rs1_value});
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@ -253,13 +208,6 @@ module zeroriscy_tracer
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end
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endfunction // printSBInstr
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function void printSBallInstr(input string mnemonic);
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begin
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regs_read.push_back('{rs1, rs1_value});
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str = $sformatf("%-16s x%0d, %0d", mnemonic, rs1, $signed(imm_sb_type));
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end
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endfunction // printSBInstr
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function void printCSRInstr(input string mnemonic);
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logic [11:0] csr;
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begin
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@ -276,23 +224,6 @@ module zeroriscy_tracer
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end
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endfunction // printCSRInstr
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function void printBit1Instr(input string mnemonic);
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begin
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regs_read.push_back('{rs1, rs1_value});
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regs_write.push_back('{rd, 'x});
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str = $sformatf("%-16s x%0d, x%0d, %0d, %0d", mnemonic, rd, rs1, imm_s3_type, imm_s2_type);
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end
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endfunction
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function void printBit2Instr(input string mnemonic);
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begin
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regs_read.push_back('{rd, rs3_value});
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regs_read.push_back('{rs1, rs1_value});
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regs_write.push_back('{rd, 'x});
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str = $sformatf("%-16s x%0d, x%0d, %0d, %0d", mnemonic, rd, rs1, imm_s3_type, imm_s2_type);
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end
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endfunction
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function void printLoadInstr();
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string mnemonic;
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logic [2:0] size;
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@ -320,26 +251,10 @@ module zeroriscy_tracer
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if (instr[14:12] != 3'b111) begin
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// regular load
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if (instr[6:0] != OPCODE_LOAD_POST) begin
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regs_read.push_back('{rs1, rs1_value});
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str = $sformatf("%-16s x%0d, %0d(x%0d)", mnemonic, rd, $signed(imm_i_type), rs1);
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end else begin
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regs_read.push_back('{rs1, rs1_value});
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regs_write.push_back('{rs1, 'x});
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str = $sformatf("p.%-14s x%0d, %0d(x%0d!)", mnemonic, rd, $signed(imm_i_type), rs1);
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end
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end else begin
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// reg-reg load
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if (instr[6:0] != OPCODE_LOAD_POST) begin
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regs_read.push_back('{rs2, rs2_value});
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regs_read.push_back('{rs1, rs1_value});
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str = $sformatf("%-16s x%0d, x%0d(x%0d)", mnemonic, rd, rs2, rs1);
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end else begin
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regs_read.push_back('{rs2, rs2_value});
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regs_read.push_back('{rs1, rs1_value});
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regs_write.push_back('{rs1, 'x});
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str = $sformatf("p.%-14s x%0d, x%0d(x%0d!)", mnemonic, rd, rs2, rs1);
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end
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printMnemonic("INVALID");
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end
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end
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endfunction
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@ -360,204 +275,15 @@ module zeroriscy_tracer
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if (instr[14] == 1'b0) begin
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// regular store
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if (instr[6:0] != OPCODE_STORE_POST) begin
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regs_read.push_back('{rs2, rs2_value});
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regs_read.push_back('{rs1, rs1_value});
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str = $sformatf("%-16s x%0d, %0d(x%0d)", mnemonic, rs2, $signed(imm_s_type), rs1);
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end else begin
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regs_read.push_back('{rs2, rs2_value});
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regs_read.push_back('{rs1, rs1_value});
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regs_write.push_back('{rs1, 'x});
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str = $sformatf("p.%-14s x%0d, %0d(x%0d!)", mnemonic, rs2, $signed(imm_s_type), rs1);
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end
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end else begin
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// reg-reg store
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if (instr[6:0] != OPCODE_STORE_POST) begin
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regs_read.push_back('{rs2, rs2_value});
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regs_read.push_back('{rs3, rs3_value});
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regs_read.push_back('{rs1, rs1_value});
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str = $sformatf("p.%-14s x%0d, x%0d(x%0d)", mnemonic, rs2, rs3, rs1);
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end else begin
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regs_read.push_back('{rs2, rs2_value});
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regs_read.push_back('{rs3, rs3_value});
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regs_read.push_back('{rs1, rs1_value});
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regs_write.push_back('{rs1, 'x});
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str = $sformatf("p.%-14s x%0d, x%0d(x%0d!)", mnemonic, rs2, rs3, rs1);
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end
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printMnemonic("INVALID");
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end
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end
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endfunction // printSInstr
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function void printHwloopInstr();
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string mnemonic;
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begin
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// set mnemonic
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case (instr[14:12])
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3'b000: mnemonic = "lp.starti";
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3'b001: mnemonic = "lp.endi";
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3'b010: mnemonic = "lp.count";
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3'b011: mnemonic = "lp.counti";
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3'b100: mnemonic = "lp.setup";
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3'b101: mnemonic = "lp.setupi";
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3'b111: begin
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printMnemonic("INVALID");
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return;
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end
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endcase
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// decode and print instruction
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case (instr[14:12])
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// lp.starti and lp.endi
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3'b000,
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3'b001: str = $sformatf("%-16s 0x%0d, 0x%0h", mnemonic, rd, imm_iz_type);
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// lp.count
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3'b010: begin
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regs_read.push_back('{rs1, rs1_value});
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str = $sformatf("%-16s 0x%0d, x%0d", mnemonic, rd, rs1);
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end
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// lp.counti
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3'b011: str = $sformatf("%-16s x%0d, 0x%0h", mnemonic, rd, imm_iz_type);
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// lp.setup
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3'b100: begin
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regs_read.push_back('{rs1, rs1_value});
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str = $sformatf("%-16s 0x%0d, x%0d, 0x%0h", mnemonic, rd, rs1, imm_iz_type);
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end
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// lp.setupi
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3'b101: begin
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str = $sformatf("%-16s 0x%0d, 0x%0h, 0x%0h", mnemonic, rd, imm_iz_type, rs1);
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end
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endcase
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end
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endfunction
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function void printMulInstr();
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string mnemonic;
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string str_suf;
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string str_imm;
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string str_asm;
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begin
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// always read rs1 and rs2 and write rd
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regs_read.push_back('{rs1, rs1_value});
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regs_read.push_back('{rs2, rs2_value});
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regs_write.push_back('{rd, 'x});
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if (instr[12])
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regs_read.push_back('{rd, rs3_value});
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case ({instr[31:30], instr[14]})
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3'b000: str_suf = "u";
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3'b001: str_suf = "uR";
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3'b010: str_suf = "hhu";
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3'b011: str_suf = "hhuR";
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3'b100: str_suf = "s";
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3'b101: str_suf = "sR";
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3'b110: str_suf = "hhs";
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3'b111: str_suf = "hhsR";
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endcase
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if (instr[12])
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mnemonic = "p.mac";
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else
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mnemonic = "p.mul";
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if (imm_s3_type[4:0] != 5'b00000)
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str_asm = $sformatf("%s%sN", mnemonic, str_suf);
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else
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str_asm = $sformatf("%s%s", mnemonic, str_suf);
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if (instr[29:25] != 5'b00000)
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str = $sformatf("%-16s x%0d, x%0d, x%0d, %0d", str_asm, rd, rs1, rs2, $unsigned(imm_s3_type[4:0]));
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else
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str = $sformatf("%-16s x%0d, x%0d, x%0d", str_asm, rd, rs1, rs2);
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end
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endfunction
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function void printVecInstr();
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string mnemonic;
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string str_asm;
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string str_args;
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string str_hb;
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string str_sci;
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string str_imm;
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begin
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// always read rs1 and write rd
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regs_read.push_back('{rs1, rs1_value});
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regs_write.push_back('{rd, 'x});
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case (instr[14:13])
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2'b00: str_sci = "";
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2'b10: str_sci = ".sc";
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2'b11: str_sci = ".sci";
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endcase
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if (instr[12])
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str_hb = ".b";
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else
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str_hb = ".h";
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// set mnemonic
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case (instr[31:26])
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6'b000000: begin mnemonic = "pv.add"; str_imm = $sformatf("0x%0d", imm_vs_type); end
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6'b000010: begin mnemonic = "pv.sub"; str_imm = $sformatf("0x%0d", imm_vs_type); end
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6'b000100: begin mnemonic = "pv.avg"; str_imm = $sformatf("0x%0d", imm_vs_type); end
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6'b000110: begin mnemonic = "pv.avgu"; str_imm = $sformatf("0x%0d", imm_vu_type); end
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6'b001000: begin mnemonic = "pv.min"; str_imm = $sformatf("0x%0d", imm_vs_type); end
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6'b001010: begin mnemonic = "pv.minu"; str_imm = $sformatf("0x%0d", imm_vu_type); end
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6'b001100: begin mnemonic = "pv.max"; str_imm = $sformatf("0x%0d", imm_vs_type); end
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6'b001110: begin mnemonic = "pv.maxu"; str_imm = $sformatf("0x%0d", imm_vu_type); end
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6'b010000: begin mnemonic = "pv.srl"; str_imm = $sformatf("0x%0d", imm_vs_type); end
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6'b010010: begin mnemonic = "pv.sra"; str_imm = $sformatf("0x%0d", imm_vs_type); end
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6'b010100: begin mnemonic = "pv.sll"; str_imm = $sformatf("0x%0d", imm_vs_type); end
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6'b010110: begin mnemonic = "pv.or"; str_imm = $sformatf("0x%0d", imm_vs_type); end
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6'b011000: begin mnemonic = "pv.xor"; str_imm = $sformatf("0x%0d", imm_vs_type); end
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6'b011010: begin mnemonic = "pv.and"; str_imm = $sformatf("0x%0d", imm_vs_type); end
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6'b011100: begin mnemonic = "pv.abs"; str_imm = $sformatf("0x%0d", imm_vs_type); end
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6'b011110: begin mnemonic = "pv.extract"; str_imm = $sformatf("0x%0d", imm_vs_type); str_sci = ""; end
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6'b100000: begin mnemonic = "pv.extractu"; str_imm = $sformatf("0x%0d", imm_vu_type); str_sci = ""; end
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6'b100010: begin mnemonic = "pv.insert"; str_imm = $sformatf("0x%0d", imm_vs_type); end
|
||||
|
||||
// shuffle/pack
|
||||
6'b110000: begin mnemonic = "pv.shuffle"; str_imm = $sformatf("N/A"); end
|
||||
6'b110010: begin mnemonic = "pv.shuffle2"; end
|
||||
6'b110100: begin mnemonic = "pv.pack"; end
|
||||
6'b110110: begin mnemonic = "pv.packhi"; end
|
||||
6'b111000: begin mnemonic = "pv.packlo"; end
|
||||
|
||||
// comparisons
|
||||
6'b000001: begin mnemonic = "pv.cmpeq"; str_imm = $sformatf("0x%0d", imm_vs_type); end
|
||||
6'b000011: begin mnemonic = "pv.cmpne"; str_imm = $sformatf("0x%0d", imm_vs_type); end
|
||||
6'b000101: begin mnemonic = "pv.cmpgt"; str_imm = $sformatf("0x%0d", imm_vs_type); end
|
||||
6'b000111: begin mnemonic = "pv.cmpge"; str_imm = $sformatf("0x%0d", imm_vs_type); end
|
||||
6'b001001: begin mnemonic = "pv.cmplt"; str_imm = $sformatf("0x%0d", imm_vs_type); end
|
||||
6'b001011: begin mnemonic = "pv.cmple"; str_imm = $sformatf("0x%0d", imm_vs_type); end
|
||||
6'b001101: begin mnemonic = "pv.cmpgtu"; str_imm = $sformatf("0x%0d", imm_vu_type); end
|
||||
6'b001111: begin mnemonic = "pv.cmpgeu"; str_imm = $sformatf("0x%0d", imm_vu_type); end
|
||||
6'b010001: begin mnemonic = "pv.cmpltu"; str_imm = $sformatf("0x%0d", imm_vu_type); end
|
||||
6'b010011: begin mnemonic = "pv.cmpleu"; str_imm = $sformatf("0x%0d", imm_vu_type); end
|
||||
|
||||
default: begin
|
||||
printMnemonic("INVALID");
|
||||
return;
|
||||
end
|
||||
endcase
|
||||
|
||||
if (str_sci == "") begin
|
||||
regs_read.push_back('{rs2, rs2_value});
|
||||
str_args = $sformatf("x%0d, x%0d, x%0d", rd, rs1, rs2);
|
||||
end else if (str_sci == ".sc") begin
|
||||
regs_read.push_back('{rs2, rs2_value_vec});
|
||||
str_args = $sformatf("x%0d, x%0d, x%0d", rd, rs1, rs2);
|
||||
end else if (str_sci == ".sci") begin
|
||||
str_args = $sformatf("x%0d, x%0d, %s", rd, rs1, str_imm);
|
||||
end
|
||||
|
||||
str_asm = $sformatf("%s%s%s", mnemonic, str_sci, str_hb);
|
||||
|
||||
str = $sformatf("%-16s %s", str_asm, str_args);
|
||||
end
|
||||
endfunction
|
||||
endclass
|
||||
|
||||
mailbox #(instr_trace_t) instr_ex = new ();
|
||||
|
|
@ -600,7 +326,7 @@ module zeroriscy_tracer
|
|||
instr_trace_t trace;
|
||||
mem_acc_t mem_acc;
|
||||
// special case for WFI because we don't wait for unstalling there
|
||||
if ((id_valid && is_decoding ) || pipe_flush || (ex_data_req && is_decoding))
|
||||
if ((id_valid && is_decoding) || pipe_flush || (ex_data_req && is_decoding))
|
||||
begin
|
||||
trace = new ();
|
||||
|
||||
|
|
@ -650,33 +376,6 @@ module zeroriscy_tracer
|
|||
INSTR_EXTHZ: trace.printRInstr("p.exthz");
|
||||
INSTR_EXTBS: trace.printRInstr("p.extbs");
|
||||
INSTR_EXTBZ: trace.printRInstr("p.extbz");
|
||||
INSTR_PAVG: trace.printRInstr("p.avg");
|
||||
INSTR_PAVGU: trace.printRInstr("p.avgu");
|
||||
INSTR_PADDN: trace.printAddNInstr("p.addN");
|
||||
INSTR_PADDUN: trace.printAddNInstr("p.adduN");
|
||||
INSTR_PADDRN: trace.printAddNInstr("p.addRN");
|
||||
INSTR_PADDURN: trace.printAddNInstr("p.adduRN");
|
||||
INSTR_PSUBN: trace.printAddNInstr("p.subN");
|
||||
INSTR_PSUBUN: trace.printAddNInstr("p.subuN");
|
||||
INSTR_PSUBRN: trace.printAddNInstr("p.subRN");
|
||||
INSTR_PSUBURN: trace.printAddNInstr("p.subuRN");
|
||||
INSTR_PSLET: trace.printRInstr("p.slet");
|
||||
INSTR_PSLETU: trace.printRInstr("p.sletu");
|
||||
INSTR_PMIN: trace.printRInstr("p.min");
|
||||
INSTR_PMINU: trace.printRInstr("p.minu");
|
||||
INSTR_PMAX: trace.printRInstr("p.max");
|
||||
INSTR_PMAXU: trace.printRInstr("p.maxu");
|
||||
INSTR_PABS: trace.printR1Instr("p.abs");
|
||||
INSTR_PCLIP: trace.printClipInstr("p.clip");
|
||||
INSTR_PCLIPU: trace.printClipInstr("p.clipu");
|
||||
INSTR_PBEXT: trace.printBit1Instr("p.extract");
|
||||
INSTR_PBEXTU: trace.printBit1Instr("p.extractu");
|
||||
INSTR_PBINS: trace.printBit2Instr("p.insert");
|
||||
INSTR_PBCLR: trace.printBit1Instr("p.bclr");
|
||||
INSTR_PBSET: trace.printBit1Instr("p.bset");
|
||||
// FENCE
|
||||
INSTR_FENCE: trace.printMnemonic("fence");
|
||||
INSTR_FENCEI: trace.printMnemonic("fencei");
|
||||
// SYSTEM (CSR manipulation)
|
||||
INSTR_CSRRW: trace.printCSRInstr("csrrw");
|
||||
INSTR_CSRRS: trace.printCSRInstr("csrrs");
|
||||
|
|
@ -690,20 +389,14 @@ module zeroriscy_tracer
|
|||
INSTR_ERET: trace.printMnemonic("mret");
|
||||
INSTR_WFI: trace.printMnemonic("wfi");
|
||||
// PULP MULTIPLIER
|
||||
INSTR_PMUL: trace.printRInstr("p.mul");
|
||||
INSTR_PMAC: trace.printR3Instr("p.mac");
|
||||
INSTR_PMUL: trace.printRInstr("mul");
|
||||
INSTR_DIV: trace.printRInstr("div");
|
||||
INSTR_DIVU: trace.printRInstr("divu");
|
||||
INSTR_REM: trace.printRInstr("rem");
|
||||
INSTR_REMU: trace.printRInstr("remu");
|
||||
// opcodes with custom decoding
|
||||
{25'b?, OPCODE_LOAD}: trace.printLoadInstr();
|
||||
{25'b?, OPCODE_LOAD_POST}: trace.printLoadInstr();
|
||||
{25'b?, OPCODE_STORE}: trace.printStoreInstr();
|
||||
{25'b?, OPCODE_STORE_POST}: trace.printStoreInstr();
|
||||
{25'b?, OPCODE_HWLOOP}: trace.printHwloopInstr();
|
||||
{25'b?, OPCODE_VECOP}: trace.printVecInstr();
|
||||
INSTR_PMULRN: trace.printMulInstr();
|
||||
default: trace.printMnemonic("INVALID");
|
||||
endcase // unique case (instr)
|
||||
|
||||
|
|
@ -735,7 +428,7 @@ module zeroriscy_tracer
|
|||
if (~mem_acc.we)
|
||||
//load operations
|
||||
foreach(trace.regs_write[i])
|
||||
trace.regs_write[i].value = wb_reg_wdata;
|
||||
trace.regs_write[i].value = lsu_reg_wdata;
|
||||
trace.mem_access.push_back(mem_acc);
|
||||
end
|
||||
trace.printInstrTrace();
|
||||
|
|
|
|||
Loading…
Add table
Add a link
Reference in a new issue