mirror of
https://github.com/lowRISC/ibex.git
synced 2025-04-22 04:47:25 -04:00
Works, but bug in compressed decoder for sll
This commit is contained in:
Andreas Traber
parent
d324cfc01f
commit
5b3ba2d1d6
2 changed files with 141 additions and 158 deletions
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@ -1126,11 +1126,13 @@ module controller
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if (jump_in_ex_i == `BRANCH_COND && ~branch_decision_i) begin
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// not taken
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pc_mux_sel_o = `PC_INCR;
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ctrl_fsm_ns = DECODE;
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if (~stall_id_o)
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ctrl_fsm_ns = DECODE;
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end else begin
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// branch taken or jump
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pc_mux_sel_o = `PC_JUMP;
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ctrl_fsm_ns = BRANCH_DELAY;
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if (~stall_id_o)
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ctrl_fsm_ns = BRANCH_DELAY;
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end
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end
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@ -1247,7 +1249,7 @@ module controller
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// we unstall the if_stage if the debug unit wants to set a new
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// pc, so that the new value gets written into current_pc_if and is
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// used by the instr_core_interface
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stall_if_o = instr_ack_stall | load_stall | jr_stall | lsu_stall | misalign_stall | dbg_halt | dbg_stall_i | (~pc_valid_i);
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stall_if_o = instr_ack_stall | load_stall | jr_stall | lsu_stall | misalign_stall | dbg_halt | dbg_stall_i | (~pc_valid_i) | (jump_in_id_o != `BRANCH_NONE);
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stall_id_o = instr_ack_stall | load_stall | jr_stall | lsu_stall | misalign_stall | dbg_halt | dbg_stall_i;
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stall_ex_o = instr_ack_stall | lsu_stall | dbg_stall_i;
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stall_wb_o = lsu_stall | dbg_stall_i;
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291
if_stage.sv
291
if_stage.sv
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@ -81,17 +81,18 @@ module if_stage
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);
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// offset FSM
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enum logic[3:0] {IDLE, WAIT_ALIGNED, WAIT_UNALIGNED, VALID_ALIGNED, VALID_UNALIGNED,
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HANDLE_BRANCH, FETCH_UNALIGNED} offset_fsm_cs, offset_fsm_ns, offset_fsm_stored;
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enum logic[3:0] {WAIT_ALIGNED, VALID_ALIGNED,
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UNALIGNED_16,
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WAIT_UNALIGNED_32, VALID_UNALIGNED_32,
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WAIT_JUMPED_ALIGNED, VALID_JUMPED_ALIGNED,
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WAIT_JUMPED_UNALIGNED, VALID_JUMPED_UNALIGNED,
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IDLE } offset_fsm_cs, offset_fsm_ns, offset_fsm_stored;
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logic [1:0] is_compressed;
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logic crossword_n, crossword_Q;
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logic unaligned, unaligned_Q;
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logic crossword;
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logic unaligned;
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logic unaligned_jump;
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logic handle_branch;
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logic force_nop_int;
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// instr_core_interface
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logic fetch_req;
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logic [31:0] fetch_rdata;
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@ -115,7 +116,7 @@ module if_stage
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current_pc_if_o = {fetch_addr[31:2], 2'b00};
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if (unaligned) begin
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if (crossword_Q) begin
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if (crossword) begin
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// cross-word access, regular instruction
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instr_rdata_int = {fetch_rdata[15:0], data_arr};
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current_pc_if_o = {fetch_addr_Q[31:2], 2'b10};
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@ -127,10 +128,6 @@ module if_stage
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current_pc_if_o = {fetch_addr[31:2], 2'b10};
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end
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end
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// insert NOPs for branches
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if (force_nop_int)
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instr_rdata_int = {25'b0, `OPCODE_OPIMM};
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end
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@ -199,14 +196,8 @@ module if_stage
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begin
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if (rst_n == 1'b0) begin
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offset_fsm_cs <= IDLE;
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offset_fsm_stored <= IDLE;
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end else begin
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if (handle_branch) begin
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offset_fsm_cs <= HANDLE_BRANCH;
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offset_fsm_stored <= offset_fsm_ns;
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end
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else
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offset_fsm_cs <= offset_fsm_ns;
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offset_fsm_cs <= offset_fsm_ns;
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end
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end
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@ -215,171 +206,151 @@ module if_stage
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begin
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offset_fsm_ns = offset_fsm_cs;
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handle_branch = 1'b0;
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fetch_req = 1'b0;
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valid_o = 1'b0;
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unaligned = unaligned_Q;
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crossword_n = crossword_Q;
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force_nop_int = 1'b0;
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unaligned = 1'b0;
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crossword = 1'b0;
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unique case (offset_fsm_cs)
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// no valid instruction data for ID stage
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// assume aligned
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IDLE: begin
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if (req_i) begin
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fetch_req = 1'b1;
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offset_fsm_ns = WAIT_JUMPED_ALIGNED;
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end
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end
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// aligned 32 bit or 16 bit instruction, we don't know yet
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WAIT_ALIGNED,
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VALID_ALIGNED: begin
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if (fetch_valid || offset_fsm_cs == VALID_ALIGNED) begin
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valid_o = 1'b1; // an instruction is ready for ID stage
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offset_fsm_ns = VALID_ALIGNED;
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if (req_i && ~stall_if_i) begin
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if (~is_compressed[0]) begin
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// 32 bit aligned instruction found
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fetch_req = 1'b1;
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offset_fsm_ns = WAIT_ALIGNED;
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end else begin
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// 16 bit aligned instruction found
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if (is_compressed[1]) begin
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// next is 16 bit unaligned instruction
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// we already have that data, no need to fetch anything
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offset_fsm_ns = UNALIGNED_16;
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end else begin
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// next is 32 bit unaligned instruction
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// the upper half of this instruction is missing, start
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// fetching it
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fetch_req = 1'b1;
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offset_fsm_ns = WAIT_UNALIGNED_32;
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end
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end
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end
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end
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end
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// unaligned 16 bit instruction
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UNALIGNED_16: begin
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unaligned = 1'b1;
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// we don't need to wait for a fetch_valid as we already have the data
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valid_o = 1'b1;
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if (req_i && ~stall_if_i) begin
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// next instruction will be aligned
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fetch_req = 1'b1;
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offset_fsm_ns = WAIT_ALIGNED;
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end
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end
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// We are currently in an ALIGNED state, serving PC[1] == 1'b0
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VALID_ALIGNED,
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WAIT_ALIGNED: begin
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unaligned = 1'b0;
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// unaligned 32 bit instruction
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WAIT_UNALIGNED_32,
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VALID_UNALIGNED_32: begin
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unaligned = 1'b1;
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crossword = 1'b1;
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if (fetch_valid || offset_fsm_cs == VALID_ALIGNED) begin
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if (fetch_valid || offset_fsm_cs == VALID_UNALIGNED_32) begin
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valid_o = 1'b1;
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offset_fsm_ns = VALID_ALIGNED;
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offset_fsm_ns = VALID_UNALIGNED_32;
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if (req_i && ~stall_if_i) begin
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crossword_n = 1'b0;
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// ----------------------------------------------------------------------
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// no branch in ID, do regular fetch
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// ----------------------------------------------------------------------
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if (is_compressed[0]) begin
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// compressed instruction
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if (is_compressed[1]) begin
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// upper half contains compressed instruction and is available
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// from register, don't start fetch now
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offset_fsm_ns = VALID_UNALIGNED;
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end else begin
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// cross-word access, upper half is beginning of 32 bit instruction
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crossword_n = 1'b1;
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fetch_req = 1'b1;
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offset_fsm_ns = WAIT_UNALIGNED;
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end
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if (is_compressed[1]) begin
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// next is 16 bit unaligned instruction
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// we already have that data, no need to fetch anything
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offset_fsm_ns = UNALIGNED_16;
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end else begin
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// regular instruction
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fetch_req = 1'b1;
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offset_fsm_ns = WAIT_ALIGNED;
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end
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if (jump_in_id_i != `BRANCH_NONE) begin
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// ----------------------------------------------------------------------
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// need to handle branch
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// ----------------------------------------------------------------------
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handle_branch = 1'b1;
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// next is 32 bit unaligned instruction
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// the upper half of this instruction is missing, start
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// fetching it
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fetch_req = 1'b1;
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offset_fsm_ns = WAIT_UNALIGNED_32;
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end
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end
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end
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end
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// We are currently in an unaligned state, serving PC[1] == 1'b1
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WAIT_UNALIGNED,
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VALID_UNALIGNED: begin
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unaligned = 1'b1;
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// we did an aligned jump
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WAIT_JUMPED_ALIGNED,
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VALID_JUMPED_ALIGNED: begin
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if (fetch_valid || offset_fsm_cs == VALID_UNALIGNED) begin
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if (fetch_valid || offset_fsm_cs == VALID_JUMPED_ALIGNED) begin
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valid_o = 1'b1;
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offset_fsm_ns = VALID_UNALIGNED;
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offset_fsm_ns = VALID_JUMPED_ALIGNED;
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if (req_i && ~stall_if_i) begin
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crossword_n = 1'b0;
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// ----------------------------------------------------------------------
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// no branch in ID, do regular fetch
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// ----------------------------------------------------------------------
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if (crossword_Q) begin
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// last instruction was 32 bit crossword, unaligned
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if (is_compressed[0]) begin
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// this instruction is 16 bit
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if (is_compressed[1]) begin
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// compressed instruction, next instruction will be
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// unaligned
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offset_fsm_ns = VALID_UNALIGNED;
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// next instruction is also 16 bit
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offset_fsm_ns = UNALIGNED_16;
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end else begin
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// regular instruction, fetch following instruction
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fetch_req = 1'b1;
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crossword_n = 1'b1;
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offset_fsm_ns = WAIT_UNALIGNED;
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// next is 32 bit unaligned instruction
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// the upper half of this instruction is missing, start
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// fetching it
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fetch_req = 1'b1;
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offset_fsm_ns = WAIT_UNALIGNED_32;
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end
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end else begin
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// compressed instruction because no cross-word access done,
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// next instruction will be aligned
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// this instruction is 32 bit, so next one will be aligned
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fetch_req = 1'b1;
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offset_fsm_ns = WAIT_ALIGNED;
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assert(is_compressed[1]) else $error("Not compressed, but compressed expected");
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end
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if (jump_in_id_i != `BRANCH_NONE) begin
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handle_branch = 1'b1;
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end
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end
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end
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end
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HANDLE_BRANCH: begin
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// assume jump/branch instruction is in EX stage
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if (jump_in_ex_i == `BRANCH_COND && ~branch_decision_i) begin
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// branch not taken
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// let's go to one instruction after the one we already put into the
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// pipeline
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if (unaligned_Q) begin
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// last state was unaligned, go back
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if (crossword_Q) begin
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fetch_req = 1'b1;
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offset_fsm_ns = WAIT_UNALIGNED;
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end else begin
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fetch_req = 1'b1;
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offset_fsm_ns = WAIT_ALIGNED;
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end
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end else begin
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crossword_n = 1'b0;
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if (is_compressed[0]) begin
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offset_fsm_ns = VALID_UNALIGNED;
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end else begin
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offset_fsm_ns = VALID_ALIGNED;
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end
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end
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end else begin
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// branch taken or jump
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fetch_req = 1'b1;
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crossword_n = 1'b0;
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if (unaligned_jump) begin
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// if the target address is unaligned, we need to fetch the lower
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// word first
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offset_fsm_ns = FETCH_UNALIGNED;
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end else begin
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offset_fsm_ns = WAIT_ALIGNED;
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end
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end
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end
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// can be cross-word or compressed
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FETCH_UNALIGNED: begin
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// we did an unaligned jump
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WAIT_JUMPED_UNALIGNED,
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VALID_JUMPED_UNALIGNED: begin
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unaligned = 1'b1;
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if (fetch_valid) begin
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if (fetch_valid || offset_fsm_cs == VALID_JUMPED_UNALIGNED) begin
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// here we might not yet have the data, if the instruction is 32 bit
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// unaligned
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offset_fsm_ns = VALID_JUMPED_UNALIGNED;
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if (is_compressed[1]) begin
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// no cross-word access
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crossword_n = 1'b0;
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valid_o = 1'b1;
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if (req_i && ~stall_if_i) begin
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fetch_req = 1'b1;
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offset_fsm_ns = WAIT_ALIGNED;
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end else begin
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offset_fsm_ns = VALID_UNALIGNED;
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end
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// Puh, lucky, we got a 16 bit instruction
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valid_o = 1'b1;
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// next instruction will be aligned
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fetch_req = 1'b1;
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offset_fsm_ns = WAIT_ALIGNED;
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end else begin
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// cross-word access, fetch next word
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fetch_req = 1'b1;
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crossword_n = 1'b1;
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offset_fsm_ns = WAIT_UNALIGNED;
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// a 32 bit unaligned instruction, let's fetch the upper half
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// we don't wait for stalls here as we still need data to get
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// unstalled
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fetch_req = 1'b1;
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offset_fsm_ns = WAIT_UNALIGNED_32;
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end
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end
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end
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@ -388,6 +359,31 @@ module if_stage
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offset_fsm_ns = IDLE;
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end
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endcase
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// take care of jumps and branches
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if(~stall_id_i) begin
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if (jump_in_ex_i != `BRANCH_NONE) begin
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if ((jump_in_ex_i == `BRANCH_COND && branch_decision_i) ||
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jump_in_ex_i == `BRANCH_JAL || jump_in_ex_i == `BRANCH_JALR) begin
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// branch taken
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fetch_req = 1'b1;
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if (unaligned_jump)
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offset_fsm_ns = WAIT_JUMPED_UNALIGNED;
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else
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offset_fsm_ns = WAIT_JUMPED_ALIGNED;
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end else begin
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// branch not taken
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// we don't need to do anything?
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end
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end else if (jump_in_id_i != `BRANCH_NONE) begin
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// new branch in ID, just wait
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//fetch_req = 1'b0;
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end
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end
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end
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@ -410,7 +406,7 @@ module if_stage
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data_arr <= 16'b0;
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fetch_addr_Q <= 32'b0;
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end else begin
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if (~stall_if_i) begin
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if (fetch_req) begin
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data_arr <= fetch_rdata[31:16];
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fetch_addr_Q <= fetch_addr;
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end
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@ -418,21 +414,6 @@ module if_stage
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end
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// IF PC register
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always_ff @(posedge clk, negedge rst_n)
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begin : IF_PIPELINE
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if (rst_n == 1'b0)
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begin
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crossword_Q <= 1'b0;
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unaligned_Q <= 1'b0;
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end
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else
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begin
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crossword_Q <= crossword_n;
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unaligned_Q <= unaligned;
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end
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end
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// IF-ID pipeline registers, frozen when the ID stage is stalled
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always_ff @(posedge clk, negedge rst_n)
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begin : IF_ID_PIPE_REGISTERS
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