Synthesis problems... take #2

This commit is contained in:
Andreas Traber 2015-08-28 13:55:50 +02:00
parent 6cf4b2f229
commit 5ea5e01990

View file

@ -278,9 +278,9 @@ module cs_registers
if (is_pccr == 1'b1) begin
unique case (csr_op_i)
`CSR_OP_NONE: ;
`CSR_OP_WRITE: PCCR_n[i] <= csr_wdata_i;
`CSR_OP_SET: PCCR_n[i] <= csr_wdata_i | PCCR_q[i];
`CSR_OP_CLEAR: PCCR_n[i] <= csr_wdata_i & ~(PCCR_q[i]);
`CSR_OP_WRITE: PCCR_n[0] <= csr_wdata_i;
`CSR_OP_SET: PCCR_n[0] <= csr_wdata_i | PCCR_q[0];
`CSR_OP_CLEAR: PCCR_n[0] <= csr_wdata_i & ~(PCCR_q[0]);
endcase
end
end