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Update lowrisc_ip to lowRISC/opentitan@6cc5c164b

Browse source 
NOTE this commit includes various changes to align the Ibex repo with
changes upstream in OT!

Update code from upstream repository
https://github.com/lowRISC/opentitan to revision
6cc5c164ba96d339f06cbcede0d17d2c96ce3c05

* [dv] Add SV_FCOV_SVA back (Srikrishna Iyer)
* [DV][FCOV] Minor updates to lowRISC/opentitan#5414 (Srikrishna Iyer)
* [dvsim] Fix --cov + --build|run-only bugs (Srikrishna Iyer)
* [lint] Waivers for rv_core_ibex lint (Greg Chadwick)
* [lint] Allow one branch in unique case (Greg Chadwick)
* [dv/macros] Add fcov macros from Ibex (Tom Roberts)
* [dvsim/verilator] Fix pre-build cmd failure when hw/foundry is
  absent (Michael Schaffner)
* [verilator/otp] Enable OTP preloading in verilator (Michael
  Schaffner)
* [dvsim] Use builtins wherever possible (Srikrishna Iyer)
* [prim] Avoid an apparent combinatorial loop in prim_secded_*_dec.sv
  (Rupert Swarbrick)
* [dv/shadow_reg] Fix aes shadow reg error (Cindy Chen)
* [lint] Remove comportable waivers from non-comportable IPs (Michael
  Schaffner)
* [dv] Fix VPD dumping (Srikrishna Iyer)
* [prim] Waive Verilator lint warning in prim_lfsr.sv (Pirmin Vogel)
* [dv] Hard code various dv connections until full hook-up (Timothy
  Chen)
* [tlul] Add payload checker and generator on device side only.
  (Timothy Chen)
* [prim_packer] Silence verilator width warnings (Rupert Swarbrick)
* [dvsim] lint fixes to FlowCfg (Srikrishna Iyer)
* [dvsim] Minor improvement to FlowCfg (Srikrishna Iyer)
* [dvsim] lint fixes to Scheduler (Srikrishna Iyer)
* [dvsim] Very small update to Timer. (Srikrishna Iyer)
* [lint] Update Verible lint parser to detect Verible syntax errors
  (Michael Schaffner)
* [lint] Spot errors in the lint flow that we weren't expecting
  (Rupert Swarbrick)
* [lint] Remove Fusesoc-related message waivers (Michael Schaffner)
* [top / rst] Adjust the way rst_ni is used in design (Timothy Chen)
* [dvsim/syn] Update parsing script and area reporting (Michael
  Schaffner)
* [dv/regwen] update REGWEN conventions (Cindy Chen)
* [dv/tools] Bug fix to common.tcl tb_top section. (Eitan Shapira)
* [dv] Fix stress_all with reset (Weicai Yang)
* [prim] Add a new slow to fast clock synchronizer (Tom Roberts)
* [prim] Minor lint fix (Tom Roberts)
* [tlul] Add instruction type to tlul (Timothy Chen)
* [top] Ast updates (Timothy Chen)
* [lint] Increase threshold for max number of bits in an array
  (Michael Schaffner)
* [dv] add dv_base_reg_pkg to env_pkg template (Udi Jonnalagadda)
* [dv/verilator] Ignore foundry dir (Srikrishna Iyer)
* [dv] Provide license diagnostic info for VCS (Srikrishna Iyer)
* [prim/otp_ctrl] Fix ECC correctable bug in generic OTP wrapper
  (Michael Schaffner)
* [prim_ram_1p_scr] Make parity and diffusion layer settings more
  flexible (Michael Schaffner)
* [prim] fix flash sram adapter use for configuration space (Timothy
  Chen)
* [dv] Make CSR fields randomizable by default. (Srikrishna Iyer)
* [dv/prim] minor updates (Udi Jonnalagadda)
* [top] Minor lint fixes (Timothy Chen)
* [prim_flash] Flash port alignments (Michael Schaffner)
* [prim_util_pkg] Fix DC warning in _clog2() (Philipp Wagner)
* Add missing full_o output signal of prim_fifo_sync (Philipp Wagner)
* [dv] Gracefully kill simulation (Srikrishna Iyer)
* [dv] Minor updates to prim tbs (Srikrishna Iyer)
* [flash / top] Minor edits based on reviews (Timothy Chen)
* [flash_ctrl / top] Various functional updates to flash (Timothy
  Chen)
* [dv/otp_ctrl] regwen sequence (Cindy Chen)
* [prim] Wire up full_o sync fifo output port in prim_sram_arbiter
  (Rupert Swarbrick)
* [dvsim] Generate FUSESOC_IGNORE at top of scratch root (Rupert
  Swarbrick)
* Revert "[lint] Remove Fusesoc-related message waivers" (Michael
  Schaffner)
* Revert "[lint] Rename tool warnings to flow warnings and reduce
  their severity" (Michael Schaffner)
* Revert "[lint] Provision syntax error filter for Verible lint"
  (Michael Schaffner)
* [prim] Update fifo behavior during reset (Timothy Chen)
* [dv] Move cip related macros to cip_macros (Weicai Yang)
* [dv/dvsim] Fix when next_item does not have dependency (Cindy Chen)
* [prim_packer_fifo/rtl] reset to disable output controls (Mark
  Branstad)
* [lint] Provision syntax error filter for Verible lint (Michael
  Schaffner)
* [lint] Rename tool warnings to flow warnings and reduce their
  severity (Michael Schaffner)
* [lint] Remove Fusesoc-related message waivers (Michael Schaffner)
* [dv/dvsim] collect coverage in scheduler (Cindy Chen)
* [dvsim] Fix Syn class (Michael Schaffner)
* [dv/shadow_reg] move get_shadow_regs function to dv_base_ral_block
  (Cindy Chen)
* [lc_ctrl] Switch ECC to standard Hamming code (Michael Schaffner)
* [prim_ram_*p_adv/prim_otp] Add option to use standard Hamming ECC
  (Michael Schaffner)
* [secded_gen] Fix template bug that results in lint error (Michael
  Schaffner)
* [prim/fifo_async] Disallow non-power-of-two depths (Tom Roberts)
* [dv/alert] update shadow_reg alert naming in DV (Cindy Chen)
* [dv] Align csr::reset_asserted to actual reset pin (Weicai Yang)
* [prim_secded*_fpv] Generate FPV testbenches (Michael Schaffner)
* [prim_secded*] Regenerate all SECDED primitives (Michael Schaffner)
* [secded_gen] Add ability to generate FPV TB's and correct Hamming
  code (Michael Schaffner)
* [dvsim] Run cov_merge / cov_report as part of the main set of jobs
  (Rupert Swarbrick)
* [dvsim] Get rid of Deploy's static dispatch_counter (Rupert
  Swarbrick)
* [dvsim] Make the scheduling logic per-target (Rupert Swarbrick)
* [dvsim] Remove "status" from Deploy items (Rupert Swarbrick)
* [dvsim] Create jobs with dependencies instead of sub-jobs (Rupert
  Swarbrick)
* [dvsim] Simplify SimCfg._gen_results (Rupert Swarbrick)
* [dvsim] Factor deploy method out of Deploy object (Rupert Swarbrick)
* [dvsim] Move time tracking into its own class in Deploy.py (Rupert
  Swarbrick)
* [dvsim] Fix printing of Deploy objects (Rupert Swarbrick)
* [dv] make dv_macros.svh more UVM_agnostic (Srikrishna Iyer)
* [dv/prim] reduce smoke test iterations (Udi Jonnalagadda)
* [dv/hmac] reduce runtime for sha_vector test in smoke regression
  (Cindy Chen)
* [DV] Enable cov comp creation iff cov is enabled (Srikrishna Iyer)
* [prim_alert] Fix xcelium compile error (Cindy Chen)
* [alert_rxtx/fpv] Update alert sender FPV testbenches (Michael
  Schaffner)
* [alert_rxtx] Add option to latch fatal alert in alert sender
  (Michael Schaffner)
* [kmac/dv] KMAC smoke test (Udi Jonnalagadda)
* [dv/str_utils_pkg] add byte_to_str function (Udi Jonnalagadda)
* [prim] - Add new prim_lc_dec (Jacob Levy)
* [util] Move design-related helper scripts to util/design (Michael
  Schaffner)
* [prim-flash] Add missing deps (Srikrishna Iyer)
* [dv] Define SIMULATION during DV sims (Michael Schaffner)
* [dv] Fix a typo in tb.sv.tpl (Weicai Yang)
* Cleanup: Remove executable bits from source files (Philipp Wagner)
* [dv] Use separate clock for EDN (Weicai Yang)
* [dv] Add macro DV_EDN_IF_CONNECT to simplify EDN connect in TB
  (Weicai Yang)
* [dv] Fix typo in clk_rst_if (Weicai Yang)

Signed-off-by: Tom Roberts <tomroberts@lowrisc.org>
This commit is contained in:
Tom Roberts 2021-03-03 10:48:44 +00:00 • committed by Tom Roberts
parent 6e617c4097
commit 5ef18f0b78
191 changed files with 3769 additions and 2923 deletions
Download patch file Download diff file Expand all files Collapse all files

48
dv/fcov/dv_fcov_macros.svh
View file

@ -1,48 +0,0 @@
// Copyright lowRISC contributors.
// Licensed under the Apache License, Version 2.0, see LICENSE for details.
// SPDX-License-Identifier: Apache-2.0
// Coverage support is not available in Verilator but it's useful to include extra fcov signals for
// linting purposes. They need to be marked as unused to avoid warnings.
// Include FCOV RTL by default. Exclude it for synthesis and where explicitly requested (by defining
// EXCLUDE_FCOV).
`ifdef SYNTHESIS
`define EXCLUDE_FCOV
`elsif YOSYS
`define EXCLUDE_FCOV
`endif
`ifdef VERILATOR
`define FCOV_MARK_UNUSED(__var_type, __var_name) \
__var_type unused_fcov_``__var_name; \
assign unused_fcov_``__var_name = fcov_``__var_name;
`else
`define FCOV_MARK_UNUSED(__var_type, __var_name)
`endif
`ifndef FCOV_SIGNAL
`define FCOV_SIGNAL(__var_type, __var_name, __var_definition) \
`ifndef EXCLUDE_FCOV \
__var_type fcov_``__var_name; \
\
assign fcov_``__var_name = __var_definition; \
\
`FCOV_MARK_UNUSED(__var_type, __var_name) \
`endif
`endif
`ifndef FCOV_SIGNAL_GEN_IF
`define FCOV_SIGNAL_GEN_IF(__var_type, __var_name, __var_definition, __generate_test, __default_val = '0) \
`ifndef EXCLUDE_FCOV \
__var_type fcov_``__var_name; \
\
if (__generate_test) begin : g_fcov_``__var_name \
assign fcov_``__var_name = __var_definition; \
end else begin : g_no_fcov_``__var_name \
assign fcov_``__var_name = __default_val; \
end \
\
`FCOV_MARK_UNUSED(__var_type, __var_name) \
`endif
`endif

14
dv/uvm/core_ibex/fcov/core_ibex_fcov_if.sv
View file

@ -10,7 +10,7 @@ interface core_ibex_fcov_if import ibex_pkg::*; (
input priv_lvl_e priv_mode_if,
input priv_lvl_e priv_mode_lsu
);
`include "dv_macros.svh"
`include "dv_fcov_macros.svh"
import uvm_pkg::*;
typedef enum {
@ -96,7 +96,7 @@ interface core_ibex_fcov_if import ibex_pkg::*; (
covergroup uarch_cg @(posedge clk_i);
type_option.strobe = 1;
`DV_FCOV_EXPR_SEEN(cp_insn_unstalled, instruction_unstalled.triggered)
`DV_FCOV_EXPR_SEEN(insn_unstalled, instruction_unstalled.triggered)
cp_insn_category_id: coverpoint id_instr_category;
@ -116,10 +116,10 @@ interface core_ibex_fcov_if import ibex_pkg::*; (
cp_priv_mode_if: coverpoint priv_mode_if;
cp_prov_mode_lsu: coverpoint priv_mode_lsu;
`DV_FCOV_EXPR_SEEN(cp_interrupt_taken, id_stage_i.controller_i.fcov_interrupt_taken)
`DV_FCOV_EXPR_SEEN(cp_debug_entry_if, id_stage_i.controller_i.fcov_debug_entry_if)
`DV_FCOV_EXPR_SEEN(cp_debug_entry_id, id_stage_i.controller_i.fcov_debug_entry_id)
`DV_FCOV_EXPR_SEEN(cp_pipe_flush, id_stage_i.controller_i.fcov_pipe_flush)
`DV_FCOV_EXPR_SEEN(interrupt_taken, id_stage_i.controller_i.fcov_interrupt_taken)
`DV_FCOV_EXPR_SEEN(debug_entry_if, id_stage_i.controller_i.fcov_debug_entry_if)
`DV_FCOV_EXPR_SEEN(debug_entry_id, id_stage_i.controller_i.fcov_debug_entry_id)
`DV_FCOV_EXPR_SEEN(pipe_flush, id_stage_i.controller_i.fcov_pipe_flush)
wb_reg_hz_instr_cross: cross cp_insn_category_id, cp_wb_reg_hz;
stall_cross: cross cp_insn_category_id, cp_stall_type_id;
@ -137,5 +137,5 @@ interface core_ibex_fcov_if import ibex_pkg::*; (
void'($value$plusargs("enable_uarch_cov=%d", en_uarch_cov));
end
`DV_INSTANTIATE_CG(uarch_cg, en_uarch_cov)
`DV_FCOV_INSTANTIATE_CG(uarch_cg, en_uarch_cov)
endinterface

1
dv/uvm/core_ibex/ibex_dv.f
View file

@ -70,7 +70,6 @@ ${PRJ_DIR}/vendor/google_riscv-dv/src/riscv_signature_pkg.sv
+incdir+${PRJ_DIR}/dv/uvm/core_ibex/tests
+incdir+${PRJ_DIR}/dv/uvm/core_ibex/common/ibex_mem_intf_agent
+incdir+${PRJ_DIR}/dv/uvm/core_ibex/common/irq_agent
+incdir+${PRJ_DIR}/dv/fcov
+incdir+${PRJ_DIR}/vendor/lowrisc_ip/dv/sv/mem_model
+incdir+${PRJ_DIR}/vendor/lowrisc_ip/dv/sv/dv_utils
+incdir+${PRJ_DIR}/vendor/lowrisc_ip/dv/sv/str_utils

3
dv/uvm/icache/dv/env/ibex_icache_env_cfg.sv vendored
View file

@ -35,6 +35,9 @@ class ibex_icache_env_cfg extends dv_base_env_cfg;
virtual function void initialize(bit [BUS_AW-1:0] csr_base_addr = '1);
core_agent_cfg = ibex_icache_core_agent_cfg::type_id::create("core_agent_cfg");
mem_agent_cfg = ibex_icache_mem_agent_cfg::type_id::create ("mem_agent_cfg");
// Note this is a hack - super.initialize() cannot be called without triggering a lot of
// issues due to missing RAL bits
is_initialized = 1;
endfunction
// Create tag and data ECC agents for each way. If ECC is disabled, this should still be called,

2
ibex_core.core
View file

@ -13,7 +13,7 @@ filesets:
- lowrisc:prim:lfsr
- lowrisc:ibex:ibex_pkg
- lowrisc:ibex:ibex_icache
- lowrisc:dv:dv_fcov
- lowrisc:dv:dv_fcov_macros
files:
- rtl/ibex_alu.sv
- rtl/ibex_branch_predict.sv

13
rtl/ibex_controller.sv
View file

@ -822,12 +822,13 @@ module ibex_controller #(
//////////
// FCOV //
//////////
`FCOV_SIGNAL(logic, interrupt_taken, (ctrl_fsm_cs != IRQ_TAKEN) & (ctrl_fsm_ns == IRQ_TAKEN));
`FCOV_SIGNAL(logic, debug_entry_if,
(ctrl_fsm_cs != DBG_TAKEN_IF) & (ctrl_fsm_ns == DBG_TAKEN_IF));
`FCOV_SIGNAL(logic, debug_entry_id,
(ctrl_fsm_cs != DBG_TAKEN_ID) & (ctrl_fsm_ns == DBG_TAKEN_ID));
`FCOV_SIGNAL(logic, pipe_flush, (ctrl_fsm_cs != FLUSH) & (ctrl_fsm_ns == FLUSH));
`DV_FCOV_SIGNAL(logic, interrupt_taken, (ctrl_fsm_cs != IRQ_TAKEN) & (ctrl_fsm_ns == IRQ_TAKEN))
`DV_FCOV_SIGNAL(logic, debug_entry_if,
(ctrl_fsm_cs != DBG_TAKEN_IF) & (ctrl_fsm_ns == DBG_TAKEN_IF))
`DV_FCOV_SIGNAL(logic, debug_entry_id,
(ctrl_fsm_cs != DBG_TAKEN_ID) & (ctrl_fsm_ns == DBG_TAKEN_ID))
`DV_FCOV_SIGNAL(logic, pipe_flush, (ctrl_fsm_cs != FLUSH) & (ctrl_fsm_ns == FLUSH))
////////////////
// Assertions //

10
rtl/ibex_id_stage.sv
View file

@ -1039,12 +1039,12 @@ module ibex_id_stage #(
// FCOV //
//////////
`FCOV_SIGNAL_GEN_IF(logic, rf_rd_wb_hz,
`DV_FCOV_SIGNAL_GEN_IF(logic, rf_rd_wb_hz,
(gen_stall_mem.rf_rd_a_hz | gen_stall_mem.rf_rd_b_hz) & instr_valid_i, WritebackStage)
`FCOV_SIGNAL(logic, branch_taken,
instr_executing & (id_fsm_q == FIRST_CYCLE) & branch_decision_i);
`FCOV_SIGNAL(logic, branch_not_taken,
instr_executing & (id_fsm_q == FIRST_CYCLE) & ~branch_decision_i);
`DV_FCOV_SIGNAL(logic, branch_taken,
instr_executing & (id_fsm_q == FIRST_CYCLE) & branch_decision_i)
`DV_FCOV_SIGNAL(logic, branch_not_taken,
instr_executing & (id_fsm_q == FIRST_CYCLE) & ~branch_decision_i)
////////////////
// Assertions //

5
rtl/ibex_load_store_unit.sv
View file

@ -498,8 +498,9 @@ module ibex_load_store_unit
//////////
// FCOV //
//////////
`FCOV_SIGNAL(logic, ls_error_exception, (load_err_o | store_err_o) & ~pmp_err_q);
`FCOV_SIGNAL(logic, ls_pmp_exception, (load_err_o | store_err_o) & pmp_err_q);
`DV_FCOV_SIGNAL(logic, ls_error_exception, (load_err_o | store_err_o) & ~pmp_err_q)
`DV_FCOV_SIGNAL(logic, ls_pmp_exception, (load_err_o | store_err_o) & pmp_err_q)
////////////////
// Assertions //

2
rtl/ibex_wb_stage.sv
View file

@ -173,7 +173,7 @@ module ibex_wb_stage #(
assign rf_wdata_wb_o = rf_wdata_wb_mux_we[0] ? rf_wdata_wb_mux[0] : rf_wdata_wb_mux[1];
assign rf_we_wb_o = |rf_wdata_wb_mux_we;
`FCOV_SIGNAL_GEN_IF(logic, wb_valid, g_writeback_stage.wb_valid_q, WritebackStage)
`DV_FCOV_SIGNAL_GEN_IF(logic, wb_valid, g_writeback_stage.wb_valid_q, WritebackStage)
`ASSERT(RFWriteFromOneSourceOnly, $onehot0(rf_wdata_wb_mux_we))
endmodule

2
vendor/lowrisc_ip.lock.hjson vendored
View file

@ -9,6 +9,6 @@
upstream:
{
url: https://github.com/lowRISC/opentitan
rev: 7aa5c2b890fa5d4e3d0b43e0f5e561cb7743a01d
rev: 6cc5c164ba96d339f06cbcede0d17d2c96ce3c05
}
}

4
vendor/lowrisc_ip/dv/sv/common_ifs/clk_rst_if.sv vendored
View file

@ -97,8 +97,8 @@ interface clk_rst_if #(
end
endfunction
// set the clk period in ns
function automatic void set_period_ns(int period_ps);
// set the clk period in ps
function automatic void set_period_ps(int period_ps);
clk_period_ps = period_ps;
clk_freq_mhz = 1000_000 / clk_period_ps;
recompute = 1'b1;

2
vendor/lowrisc_ip/dv/sv/common_ifs/index.md vendored
View file

@ -30,7 +30,7 @@ the frequency and duty cycle of the generated clock, use the following
functions:
* `set_freq_mhz` / `set_freq_khz`: set the clock frequency in MHz / KHz. This
is 50MHz by default.
* `set_period_ns`: set the clock period in nanoseconds. This is 20ns by default
* `set_period_ps`: set the clock period in picoseconds. This is 20_000ps by default
(giving a clock period of 50MHz).
* `set_duty_cycle`: set the duty cycle (as a percentage: 1 - 99). This is 50 by
default.

2
vendor/lowrisc_ip/dv/sv/csr_utils/csr_utils_pkg.sv vendored
View file

@ -343,7 +343,7 @@ package csr_utils_pkg;
end
// poke always updates predict value, if predict == 0, revert back to old mirrored value
if (!predict || kind == BkdrRegPathRtlShadow) begin
void'(csr.predict(.value(old_mirrored_val), .kind(UVM_PREDICT_DIRECT)));
void'(csr.predict(.value(old_mirrored_val), .kind(UVM_PREDICT_DIRECT), .path(UVM_BACKDOOR)));
end
endtask

76
vendor/lowrisc_ip/dv/sv/dv_base_reg/dv_base_reg.sv vendored
View file

@ -14,6 +14,10 @@ class dv_base_reg extends uvm_reg;
local bit shadow_wr_staged; // stage the first shadow reg write
local bit shadow_update_err;
local bit en_shadow_wr = 1;
// In certain shadow reg (e.g. in AES), fatal error can lock write access
local bit shadow_fatal_lock;
local string update_err_alert_name;
local string storage_err_alert_name;
// atomic_shadow_wr: semaphore to guarantee atomicity of the two writes for shadowed registers.
// In case a parallel thread writing a different value to the same reg causing an update_err
@ -60,6 +64,11 @@ class dv_base_reg extends uvm_reg;
locked_regs.push_back(locked_reg);
endfunction
function bit is_inside_locked_regs(dv_base_reg csr);
if (csr inside {locked_regs}) return 1;
else return 0;
endfunction
function bit is_enable_reg();
return (locked_regs.size() > 0);
endfunction
@ -136,7 +145,7 @@ class dv_base_reg extends uvm_reg;
// no need to update shadow value or access type if access is not OK, as access is aborted
if (rw.status != UVM_IS_OK) return;
if (is_shadowed) begin
if (is_shadowed && !shadow_fatal_lock) begin
// first write
if (!shadow_wr_staged) begin
shadow_wr_staged = 1;
@ -158,7 +167,8 @@ class dv_base_reg extends uvm_reg;
field_access = fields[0].get_access();
case (field_access)
// rw.value is a dynamic array
"W1C": if (rw.value[0][0] == 1'b1) set_locked_regs_access("RO");
// discussed in issue #1922: enable register is standarized to W0C or RO (if HW has write
// access).
"W0C": if (rw.value[0][0] == 1'b0) set_locked_regs_access("RO");
"RO": ; // if RO, it's updated by design, need to predict in scb
default:`uvm_fatal(`gfn, $sformatf("enable register invalid access %s", field_access))
@ -198,15 +208,20 @@ class dv_base_reg extends uvm_reg;
if (is_shadowed) atomic_shadow_wr.put(1);
endtask
// override do_predict function to support shadow_reg:
// skip predict if it is shadow_reg's first write, or second write with an update_err
// Override do_predict function to support shadow_reg.
// Skip predict in one of the following conditions:
// 1). It is shadow_reg's first write.
// 2). It is shadow_reg's second write with an update_err.
// 2). The shadow_reg is locked due to fatal storage error and it is not a backdoor write.
virtual function void do_predict (uvm_reg_item rw,
uvm_predict_e kind = UVM_PREDICT_DIRECT,
uvm_reg_byte_en_t be = -1);
if (is_shadowed && (shadow_wr_staged || shadow_update_err) && kind != UVM_PREDICT_READ) begin
`uvm_info(`gfn,
$sformatf("skip predict csr %s: due to shadow_reg_first_wr=%0b or update_err=%0b",
get_name(), shadow_wr_staged, shadow_update_err), UVM_HIGH)
if (is_shadowed && kind != UVM_PREDICT_READ && (shadow_wr_staged || shadow_update_err ||
(shadow_fatal_lock && rw.path != UVM_BACKDOOR))) begin
`uvm_info(`gfn, $sformatf(
"skip predict %s: due to shadow_reg_first_wr=%0b, update_err=%0b, shadow_fatal_lock=%0b",
get_name(), shadow_wr_staged, shadow_update_err, shadow_fatal_lock), UVM_HIGH)
return;
end
super.do_predict(rw, kind, be);
@ -221,12 +236,15 @@ class dv_base_reg extends uvm_reg;
input int lineno = 0);
if (kind == "BkdrRegPathRtlShadow") shadowed_val = value;
else if (kind == "BkdrRegPathRtlCommitted") committed_val = value;
super.poke(status, value, kind, parent, extension, fname, lineno);
endtask
// callback function to update shadowed values according to specific design
// should only be called after post-write
// Callback function to update shadowed values according to specific design.
// Should only be called after post-write.
// If a shadow reg is locked due to fatal error, this function will return without updates
virtual function void update_shadowed_val(uvm_reg_data_t val, bit do_predict = 1);
if (shadow_fatal_lock) return;
if (shadow_wr_staged) begin
// update value after first write
staged_shadow_val = val;
@ -248,6 +266,7 @@ class dv_base_reg extends uvm_reg;
if (is_shadowed) begin
shadow_update_err = 0;
shadow_wr_staged = 0;
shadow_fatal_lock = 0;
committed_val = get_mirrored_value();
shadowed_val = ~committed_val;
// in case reset is issued during shadowed writes
@ -257,4 +276,41 @@ class dv_base_reg extends uvm_reg;
atomic_en_shadow_wr.put(1);
end
endfunction
function void add_update_err_alert(string name);
if (update_err_alert_name == "") update_err_alert_name = name;
endfunction
function void add_storage_err_alert(string name);
if (storage_err_alert_name == "") storage_err_alert_name = name;
endfunction
function string get_update_err_alert_name();
string parent_name = this.get_parent().get_name();
// block level alert name is input alert name from hjson
if (parent_name == "ral") return update_err_alert_name;
// top-level alert name is ${block_name} + alert name from hjson
return ($sformatf("%0s_%0s", parent_name, update_err_alert_name));
endfunction
function void lock_shadow_reg();
shadow_fatal_lock = 1;
endfunction
function bit shadow_reg_is_locked();
return shadow_fatal_lock;
endfunction
function string get_storage_err_alert_name();
string parent_name = this.get_parent().get_name();
// block level alert name is input alert name from hjson
if (parent_name == "ral") return storage_err_alert_name;
// top-level alert name is ${block_name} + alert name from hjson
return ($sformatf("%0s_%0s", parent_name, storage_err_alert_name));
endfunction
endclass

24
vendor/lowrisc_ip/dv/sv/dv_base_reg/dv_base_reg_block.sv vendored
View file

@ -34,6 +34,7 @@ class dv_base_reg_block extends uvm_reg_block;
function void get_dv_base_regs(ref dv_base_reg dv_regs[$]);
uvm_reg ral_regs[$];
// if the ral has hier, this function will recursively includes the registers in the sub-blocks
this.get_registers(ral_regs);
foreach (ral_regs[i]) `downcast(dv_regs[i], ral_regs[i])
endfunction
@ -48,17 +49,18 @@ class dv_base_reg_block extends uvm_reg_block;
endfunction
function void get_enable_regs(ref dv_base_reg enable_regs[$]);
dv_base_reg_block blks[$];
get_dv_base_reg_blocks(blks);
if (blks.size() == 0) begin
dv_base_reg all_regs[$];
this.get_dv_base_regs(all_regs);
foreach (all_regs[i]) begin
if (all_regs[i].is_enable_reg()) enable_regs.push_back(all_regs[i]);
end
return;
end else begin
foreach (blks[i]) blks[i].get_enable_regs(enable_regs);
dv_base_reg all_regs[$];
this.get_dv_base_regs(all_regs);
foreach (all_regs[i]) begin
if (all_regs[i].is_enable_reg()) enable_regs.push_back(all_regs[i]);
end
endfunction
function void get_shadowed_regs(ref dv_base_reg shadowed_regs[$]);
dv_base_reg all_regs[$];
this.get_dv_base_regs(all_regs);
foreach (all_regs[i]) begin
if (all_regs[i].get_is_shadowed()) shadowed_regs.push_back(all_regs[i]);
end
endfunction

23
vendor/lowrisc_ip/dv/sv/dv_base_reg/dv_base_reg_field.sv vendored
View file

@ -9,6 +9,29 @@ class dv_base_reg_field extends uvm_reg_field;
`uvm_object_utils(dv_base_reg_field)
`uvm_object_new
// Issue #5105: UVM forces the value member to be non-randomizable for certain access policies.
// We restore it in this extended class.
virtual function void configure(uvm_reg parent,
int unsigned size,
int unsigned lsb_pos,
string access,
bit volatile,
uvm_reg_data_t reset,
bit has_reset,
bit is_rand,
bit individually_accessible);
super.configure(.parent (parent),
.size (size),
.lsb_pos (lsb_pos),
.access (access),
.volatile (volatile),
.reset (reset),
.has_reset(has_reset),
.is_rand (is_rand),
.individually_accessible(individually_accessible));
value.rand_mode(is_rand);
endfunction
// when use UVM_PREDICT_WRITE and the CSR access is WO, this function will return the default
// val of the register, rather than the written value
virtual function uvm_reg_data_t XpredictX(uvm_reg_data_t cur_val,

17
vendor/lowrisc_ip/dv/sv/dv_lib/dv_base_env_cfg.sv vendored
View file

@ -8,9 +8,16 @@ class dv_base_env_cfg #(type RAL_T = dv_base_reg_block) extends uvm_object;
bit en_scb = 1; // can be changed at run-time
bit en_scb_tl_err_chk = 1;
bit en_scb_mem_chk = 1;
bit en_cov = 1;
bit en_cov = 0; // Enable via plusarg, only if coverage collection is turned on.
bit has_ral = 1;
bit under_reset = 0;
bit is_initialized; // Indicates that the initialize() method has been called.
// The scope and runtime of a existing test can be reduced by setting this variable. This is
// useful to keep the runtime down especially in time-sensitive runs such as CI, which is meant
// to check the code health and not find design bugs. It is set via plusarg and retrieved in
// `dv_base_test`.
bit smoke_test = 0;
// bit to configure all uvcs with zero delays to create high bw test
rand bit zero_delays;
@ -40,8 +47,12 @@ class dv_base_env_cfg #(type RAL_T = dv_base_reg_block) extends uvm_object;
`uvm_object_new
function void pre_randomize();
`DV_CHECK_FATAL(is_initialized, "Please invoke initialize() before randomizing this object.")
endfunction
virtual function void initialize(bit [bus_params_pkg::BUS_AW-1:0] csr_base_addr = '1);
import bus_params_pkg::*;
is_initialized = 1'b1;
// build the ral model
if (has_ral) begin
@ -63,7 +74,7 @@ class dv_base_env_cfg #(type RAL_T = dv_base_reg_block) extends uvm_object;
// correctly handle the case where a bus address is narrower than a uvm_reg_addr_t).
base_addr = (&csr_base_addr ?
{`UVM_REG_ADDR_WIDTH{1'b1}} :
{{(`UVM_REG_ADDR_WIDTH - BUS_AW){1'b0}}, csr_base_addr});
{{(`UVM_REG_ADDR_WIDTH - bus_params_pkg::BUS_AW){1'b0}}, csr_base_addr});
ral.set_base_addr(base_addr);
// Get list of valid csr addresses (useful in seq to randomize addr as well as in scb checks)

7
vendor/lowrisc_ip/dv/sv/dv_lib/dv_base_scoreboard.sv vendored
View file

@ -33,9 +33,12 @@ class dv_base_scoreboard #(type RAL_T = dv_base_reg_block,
if (!cfg.clk_rst_vif.rst_n) begin
`uvm_info(`gfn, "reset occurred", UVM_HIGH)
cfg.reset_asserted();
csr_utils_pkg::reset_asserted();
@(posedge cfg.clk_rst_vif.rst_n);
reset();
cfg.reset_deasserted();
csr_utils_pkg::clear_outstanding_access();
csr_utils_pkg::reset_deasserted();
`uvm_info(`gfn, "out of reset", UVM_HIGH)
end
else begin
@ -47,7 +50,9 @@ class dv_base_scoreboard #(type RAL_T = dv_base_reg_block,
virtual function void reset(string kind = "HARD");
// reset the ral model
if (cfg.has_ral) ral.reset(kind);
if (cfg.has_ral) begin
foreach (cfg.ral_models[i]) cfg.ral_models[i].reset(kind);
end
endfunction
virtual function void pre_abort();

25
vendor/lowrisc_ip/dv/sv/dv_lib/dv_base_test.sv vendored
View file

@ -14,6 +14,8 @@ class dv_base_test #(type CFG_T = dv_base_env_cfg,
uint max_quit_count = 1;
uint64 test_timeout_ns = 200_000_000; // 200ms
uint drain_time_ns = 2_000; // 2us
bit poll_for_stop = 1'b1;
uint poll_for_stop_interval_ns = 1000;
`uvm_component_new
@ -25,17 +27,23 @@ class dv_base_test #(type CFG_T = dv_base_env_cfg,
env = ENV_T::type_id::create("env", this);
cfg = CFG_T::type_id::create("cfg", this);
// don't add args for initialize. Use default value instead
cfg.initialize();
`DV_CHECK_RANDOMIZE_FATAL(cfg)
uvm_config_db#(CFG_T)::set(this, "env", "cfg", cfg);
// knob to en/dis scb (enabled by default)
// Enable scoreboard (and sub-scoreboard checks) via plusarg.
void'($value$plusargs("en_scb=%0b", cfg.en_scb));
void'($value$plusargs("en_scb_tl_err_chk=%0b", cfg.en_scb_tl_err_chk));
void'($value$plusargs("en_scb_mem_chk=%0b", cfg.en_scb_mem_chk));
// knob to cfg all agents with zero delays
// Enable fastest design performance by configuring zero delays in all agents.
void'($value$plusargs("zero_delays=%0b", cfg.zero_delays));
// Enable coverage collection.
void'($value$plusargs("en_cov=%0b", cfg.en_cov));
// Enable reduced runtime test.
void'($value$plusargs("smoke_test=%0b", cfg.smoke_test));
endfunction : build_phase
virtual function void end_of_elaboration_phase(uvm_phase phase);
@ -49,17 +57,22 @@ class dv_base_test #(type CFG_T = dv_base_env_cfg,
virtual task run_phase(uvm_phase phase);
void'($value$plusargs("drain_time_ns=%0d", drain_time_ns));
phase.phase_done.set_drain_time(this, (drain_time_ns * 1ns));
void'($value$plusargs("poll_for_stop=%0b", poll_for_stop));
void'($value$plusargs("poll_for_stop_interval_ns=%0d", poll_for_stop_interval_ns));
if (poll_for_stop) dv_utils_pkg::poll_for_stop(.interval_ns(poll_for_stop_interval_ns));
void'($value$plusargs("UVM_TEST_SEQ=%0s", test_seq_s));
if (run_test_seq) begin
run_seq(test_seq_s, phase);
end
// TODO: add hook for end of test checking
// TODO: add hook for end of test checking.
endtask : run_phase
virtual task run_seq(string test_seq_s, uvm_phase phase);
uvm_sequence test_seq = create_seq_by_name(test_seq_s);
// provide virtual_sequencer earlier, so we may use the p_sequencer in constraint
// Setting the sequencer before the sequence is randomized is mandatory. We do this so that the
// sequence has access to the UVM environment's cfg handle via the p_sequencer handle within the
// randomization constraints.
test_seq.set_sequencer(env.virtual_sequencer);
`DV_CHECK_RANDOMIZE_FATAL(test_seq)
@ -70,7 +83,7 @@ class dv_base_test #(type CFG_T = dv_base_env_cfg,
`uvm_info(`gfn, {"Finished test sequence ", test_seq_s}, UVM_MEDIUM)
endtask
// TODO: add default report_phase implementation
// TODO: Add default report_phase implementation.
endclass : dv_base_test

8
vendor/lowrisc_ip/dv/sv/dv_lib/dv_base_vseq.sv vendored
View file

@ -25,7 +25,7 @@ class dv_base_vseq #(type RAL_T = dv_base_reg_block,
// knobs to enable pre_start routines
bit do_dut_init = 1'b1;
bit do_apply_reset = 1'b1;
bit do_wait_for_reset = 1'b1;
bit do_wait_for_reset = 1'b0;
// knobs to enable post_start routines
bit do_dut_shutdown = 1'b1;
@ -86,13 +86,7 @@ class dv_base_vseq #(type RAL_T = dv_base_reg_block,
virtual task apply_reset(string kind = "HARD");
if (kind == "HARD") begin
csr_utils_pkg::reset_asserted();
cfg.clk_rst_vif.apply_reset();
csr_utils_pkg::clear_outstanding_access();
csr_utils_pkg::reset_deasserted();
end
if (cfg.has_ral) begin
foreach (cfg.ral_models[i]) cfg.ral_models[i].reset(kind);
end
endtask

4
dv/fcov/dv_fcov.core → vendor/lowrisc_ip/dv/sv/dv_utils/dv_fcov_macros.core vendored
View file

@ -2,8 +2,8 @@ CAPI=2:
# Copyright lowRISC contributors.
# Licensed under the Apache License, Version 2.0, see LICENSE for details.
# SPDX-License-Identifier: Apache-2.0
name: "lowrisc:dv:dv_fcov"
description: "DV FCOV utilities"
name: "lowrisc:dv:dv_fcov_macros"
description: "DV FCOV macros"
filesets:
files_fcov:

112
vendor/lowrisc_ip/dv/sv/dv_utils/dv_fcov_macros.svh vendored Normal file
View file

@ -0,0 +1,112 @@
// Copyright lowRISC contributors.
// Licensed under the Apache License, Version 2.0, see LICENSE for details.
// SPDX-License-Identifier: Apache-2.0
// Include FCOV RTL by default. Disable it for synthesis and where explicitly requested (by defining
// DV_FCOV_DISABLE).
`ifdef SYNTHESIS
`define DV_FCOV_DISABLE
`elsif YOSYS
`define DV_FCOV_DISABLE
`endif
// Disable instantiations of FCOV coverpoints or covergroups.
`ifdef VERILATOR
`define DV_FCOV_DISABLE_CP
`elsif DV_FCOV_DISABLE
`define DV_FCOV_DISABLE_CP
`endif
// Instantiates a covergroup in an interface or module.
//
// This macro assumes that a covergroup of the same name as the NAME_ arg is defined in the
// interface or module. It just adds some extra signals and logic to control the creation of the
// covergroup instance with ~bit en_<cg_name>~. This defaults to 0. It is ORed with the external
// COND_ signal. The testbench can modify it at t = 0 based on the test being run.
// NOTE: This is not meant to be invoked inside a class.
//
// NAME_ : Name of the covergroup.
// COND_ : External condition / expr that controls the creation of the covergroup.
// ARGS_ : Arguments to covergroup instance, if any. Args MUST BE wrapped in (..).
`ifndef DV_FCOV_INSTANTIATE_CG
`ifdef DV_FCOV_DISABLE_CP
`define DV_FCOV_INSTANTIATE_CG(NAME_, COND_ = 1'b1, ARGS_ = ())
`else
`define DV_FCOV_INSTANTIATE_CG(NAME_, COND_ = 1'b1, ARGS_ = ()) \
bit en_``NAME_ = 1'b0; \
NAME_ NAME_``_inst; \
initial begin \
/* The #1 delay below allows any part of the tb to control the conditions first at t = 0. */ \
#1; \
if ((en_``NAME_) || (COND_)) begin \
$display("%0t: (%0s:%0d) [%m] %0s", $time, `__FILE__, `__LINE__, \
{"Creating covergroup ", `"NAME_`"}); \
NAME_``_inst = new``ARGS_; \
end \
end
`endif
`endif
// Creates a coverpoint for an expression where only the expression true case is of interest for
// coverage (e.g. where the expression indicates an event has occured).
`ifndef DV_FCOV_EXPR_SEEN
`ifdef DV_FCOV_DISABLE_CP
`define DV_FCOV_EXPR_SEEN(NAME_, EXPR_)
`else
`define DV_FCOV_EXPR_SEEN(NAME_, EXPR_) cp_``NAME_: coverpoint EXPR_ { bins seen = {1}; }
`endif
`endif
// Creates a SVA cover that can be used in a covergroup.
//
// This macro creates an unnamed SVA cover from the property (or an expression) `PROP_` and an event
// with the name `EV_NAME_`. When the SVA cover is hit, the event is triggered. A coverpoint can
// cover the `triggered` property of the event.
`ifndef DV_FCOV_SVA
`ifdef DV_FCOV_DISABLE
`define DV_FCOV_SVA(EV_NAME_, PROP_, CLK_ = clk_i, RST_ = rst_ni)
`else
`define DV_FCOV_SVA(EV_NAME_, PROP_, CLK_ = clk_i, RST_ = rst_ni) \
event EV_NAME_; \
cover property (@(posedge CLK_) disable iff (RST_ == 0) (PROP_)) begin \
-> EV_NAME_; \
end
`endif
`endif
// Coverage support is not always available but it's useful to include extra fcov signals for
// linting purposes. They need to be marked as unused to avoid warnings.
`ifndef DV_FCOV_MARK_UNUSED
`define DV_FCOV_MARK_UNUSED(TYPE_, NAME_) \
TYPE_ unused_fcov_``NAME_; \
assign unused_fcov_``NAME_ = fcov_``NAME_;
`endif
// Define a signal and expression in the design for capture in functional coverage
`ifndef DV_FCOV_SIGNAL
`ifdef DV_FCOV_DISABLE
`define DV_FCOV_SIGNAL(TYPE_, NAME_, EXPR_)
`else
`define DV_FCOV_SIGNAL(TYPE_, NAME_, EXPR_) \
TYPE_ fcov_``NAME_; \
assign fcov_``NAME_ = EXPR_; \
`DV_FCOV_MARK_UNUSED(TYPE_, NAME_)
`endif
`endif
// Define a signal and expression in the design for capture in functional coverage depending on
// design configuration. The input GEN_COND_ must be a constant or parameter.
`ifndef DV_FCOV_SIGNAL_GEN_IF
`ifdef DV_FCOV_DISABLE
`define DV_FCOV_SIGNAL_GEN_IF(TYPE_, NAME_, EXPR_, GEN_COND_, DEFAULT_ = '0)
`else
`define DV_FCOV_SIGNAL_GEN_IF(TYPE_, NAME_, EXPR_, GEN_COND_, DEFAULT_ = '0) \
TYPE_ fcov_``NAME_; \
if (GEN_COND_) begin : g_fcov_``NAME_ \
assign fcov_``NAME_ = EXPR_; \
end else begin : g_no_fcov_``NAME_ \
assign fcov_``NAME_ = DEFAULT_; \
end \
`DV_FCOV_MARK_UNUSED(TYPE_, NAME_)
`endif
`endif

73
vendor/lowrisc_ip/dv/sv/dv_utils/dv_macros.svh vendored
View file

@ -2,9 +2,6 @@
// Licensed under the Apache License, Version 2.0, see LICENSE for details.
// SPDX-License-Identifier: Apache-2.0
`ifndef __DV_MACROS_SVH__
`define __DV_MACROS_SVH__
`ifdef UVM
`include "uvm_macros.svh"
`endif
@ -270,7 +267,7 @@
// print static/dynamic 1d array or queue
`ifndef DV_PRINT_ARR_CONTENTS
`define DV_PRINT_ARR_CONTENTS(ARR_, V_=UVM_MEDIUM, ID_=`gfn) \
`define DV_PRINT_ARR_CONTENTS(ARR_, V_=uvm_pkg::UVM_MEDIUM, ID_=`gfn) \
begin \
foreach (ARR_[i]) begin \
`dv_info($sformatf("%s[%0d] = 0x%0d[0x%0h]", `"ARR_`", i, ARR_[i], ARR_[i]), V_, ID_) \
@ -364,7 +361,7 @@
begin \
EXIT_ \
if (MSG_ != "") begin \
`dv_info(MSG_, UVM_HIGH, ID_) \
`dv_info(MSG_, uvm_pkg::UVM_HIGH, ID_) \
end \
end \
join_any \
@ -438,7 +435,7 @@
`ifdef UVM
`ifndef dv_info
// verilog_lint: waive macro-name-style
`define dv_info(MSG_, VERBOSITY_ = UVM_LOW, ID_ = $sformatf("%m")) \
`define dv_info(MSG_, VERBOSITY_ = uvm_pkg::UVM_LOW, ID_ = $sformatf("%m")) \
if (uvm_pkg::uvm_report_enabled(VERBOSITY_, uvm_pkg::UVM_INFO, ID_)) begin \
uvm_pkg::uvm_report_info(ID_, MSG_, VERBOSITY_, `uvm_file, `uvm_line, "", 1); \
end
@ -495,67 +492,3 @@
`endif
`endif // UVM
// Declare array of alert interface, using parameter NUM_ALERTS and LIST_OF_ALERTS, and connect to
// arrays of wires (alert_tx and alert_rx). User need to manually connect these wires to DUT
// Also set each alert_if to uvm_config_db to use in env
`ifndef DV_ALERT_IF_CONNECT
`define DV_ALERT_IF_CONNECT \
alert_esc_if alert_if[NUM_ALERTS](.clk(clk), .rst_n(rst_n)); \
prim_alert_pkg::alert_rx_t [NUM_ALERTS-1:0] alert_rx; \
prim_alert_pkg::alert_tx_t [NUM_ALERTS-1:0] alert_tx; \
for (genvar k = 0; k < NUM_ALERTS; k++) begin : connect_alerts_pins \
assign alert_rx[k] = alert_if[k].alert_rx; \
assign alert_if[k].alert_tx = alert_tx[k]; \
initial begin \
uvm_config_db#(virtual alert_esc_if)::set(null, $sformatf("*.env.m_alert_agent_%0s", \
LIST_OF_ALERTS[k]), "vif", alert_if[k]); \
end \
end
`endif
// Instantiates a covergroup in an interface or module.
//
// This macro assumes that a covergroup of the same name as the __CG_NAME arg is defined in the
// interface or module. It just adds some extra signals and logic to control the creation of the
// covergroup instance with ~bit en_<cg_name>~. This defaults to 0. It is ORed with the external
// __COND signal. The testbench can modify it at t = 0 based on the test being run.
// NOTE: This is not meant to be invoked inside a class.
//
// __CG_NAME : Name of the covergroup.
// __COND : External condition / expr that controls the creation of the covergroup.
// __CG_ARGS : Arguments to covergroup instance, if any. Args MUST BE wrapped in (..).
`ifndef DV_INSTANTIATE_CG
`define DV_INSTANTIATE_CG(__CG_NAME, __COND = 1'b1, __CG_ARGS = ()) \
bit en_``__CG_NAME = 1'b0; \
__CG_NAME __CG_NAME``_inst; \
initial begin \
/* The #1 delay below allows any part of the tb to control the conditions first at t = 0. */ \
#1; \
if ((en_``__CG_NAME) || (__COND)) begin \
`dv_info({"Creating covergroup ", `"__CG_NAME`"}, UVM_MEDIUM) \
__CG_NAME``_inst = new``__CG_ARGS; \
end \
end
`endif
// Creates a SVA cover that can be used in a covergroup.
//
// This macro creates an unnamed SVA cover from the expression `__sva` and an event with the name
// `__ev_name`. When the SVA cover is hit, the event is triggered. A coverpoint can cover the
// `triggered` property of the event.
`ifndef DV_FCOV_SVA
`define DV_FCOV_SVA(__ev_name, __sva, __clk = clk_i, __rst = rst_ni) \
event __ev_name; \
cover property (@(posedge __clk) disable iff (__rst == 0) (__sva)) begin \
-> __ev_name; \
end
`endif
// Creates a coverpoint for an expression where only the expression true case is of interest for
// coverage (e.g. where the expression indicates an event has occured).
`ifndef DV_FCOV_EXPR_SEEN
`define DV_FCOV_EXPR_SEEN(__cp_name, __expr) __cp_name: coverpoint __expr { bins seen = {1}; }
`endif
`endif // __DV_MACROS_SVH__

1
vendor/lowrisc_ip/dv/sv/dv_utils/dv_utils.core vendored
View file

@ -9,6 +9,7 @@ filesets:
files_dv:
depend:
- lowrisc:dv:dv_macros
- lowrisc:dv:dv_fcov_macros
- lowrisc:dv:common_ifs
- lowrisc:prim:assert:0.1
- lowrisc:ibex:bus_params_pkg

25
vendor/lowrisc_ip/dv/sv/dv_utils/dv_utils_pkg.sv vendored
View file

@ -92,11 +92,20 @@ package dv_utils_pkg;
return val >= 0 ? val : -val;
endfunction
// endian swap
// endian swaps a 32-bit data word
function automatic logic [31:0] endian_swap(logic [31:0] data);
return {<<8{data}};
endfunction
// endian swaps bytes at a word granularity, while preserving overall word ordering.
//
// e.g. if `arr[] = '{'h0, 'h1, 'h2, 'h3, 'h4, 'h5, 'h6, 'h7}`, this function will produce:
// `'{'h3, 'h2, 'h1, 'h0, 'h7, 'h6, 'h5, 'h4}`
function automatic void endian_swap_byte_arr(ref bit [7:0] arr[]);
arr = {<< byte {arr}};
arr = {<< 32 {arr}};
endfunction
`ifdef UVM
// Simple function to set max errors before quitting sim
function automatic void set_max_quit_count(int n);
@ -171,6 +180,20 @@ package dv_utils_pkg;
return (hier.substr(0, idx - 1));
endfunction
// Periodically check for the existence of a magic file (dv.stop). Exit if it exists. This
// provides a mechanism to gracefully kill a simulation without direct access to the process.
task automatic poll_for_stop(uint interval_ns = 1000, string filename = "dv.stop");
fork
while (1) begin
#(interval_ns * 1ns);
if (!$system($sformatf("test -f %0s", filename))) begin
$system($sformatf("rm %0s", filename));
`dv_fatal($sformatf("Found %0s file. Exiting!", filename), "poll_for_stop")
end
end
join_none
endtask : poll_for_stop
// sources
`ifdef UVM
`include "dv_report_server.sv"

9
vendor/lowrisc_ip/dv/sv/str_utils/str_utils_pkg.sv vendored
View file

@ -119,6 +119,15 @@ package str_utils_pkg;
end
endfunction : str_to_bytes
// Converts an array of bytes to a string.
function automatic string bytes_to_str(byte bytes[]);
string s;
foreach (bytes[i]) begin
s = {s, string'(bytes[i])};
end
return s;
endfunction
/************************/
/* File path functions. */
/************************/

3
vendor/lowrisc_ip/dv/tools/common.tcl vendored
View file

@ -17,8 +17,9 @@ if {[info exists ::env(WAVES)]} {
}
set tb_top "tb"
if {[info exists ::(TB_TOP)]} {
if {[info exists ::env(TB_TOP)]} {
set tb_top "$::env(TB_TOP)"
} else {
puts "WARNING: TB_TOP environment variable not set - using \"tb\" as the
top level testbench hierarchy."
}

3
vendor/lowrisc_ip/dv/tools/dvsim/common_modes.hjson vendored
View file

@ -16,6 +16,9 @@
name: cov
is_sim_mode: 1
en_build_modes: ["{tool}_cov"]
// This plusarg is retrieved in `hw/dv/sv/dv_lib/dv_base_test.sv`. If not set, the coverage
// collection components are not created.
run_opts: ["+en_cov=1"]
}
{
name: profile

5
vendor/lowrisc_ip/dv/tools/dvsim/common_sim_cfg.hjson vendored
View file

@ -62,7 +62,8 @@
"+define+UVM_REGEX_NO_DPI",
"+define+UVM_REG_ADDR_WIDTH={tl_aw}",
"+define+UVM_REG_DATA_WIDTH={tl_dw}",
"+define+UVM_REG_BYTENABLE_WIDTH={tl_dbw}"]
"+define+UVM_REG_BYTENABLE_WIDTH={tl_dbw}",
"+define+SIMULATION"]
run_opts: ["+UVM_NO_RELNOTES",
"+UVM_VERBOSITY={expand_uvm_verbosity_{verbosity}}"]
@ -110,6 +111,8 @@
name: smoke
tests: []
reseed: 1
// Knob used to configure an existing test / vseq to have a shorter runtime.
run_opts: ["+smoke_test=1"]
}
{

1
vendor/lowrisc_ip/dv/tools/dvsim/vcs.hjson vendored
View file

@ -192,6 +192,7 @@
// Vars that need to exported to the env.
exports: [
{ FLEXLM_DIAGNOSTICS: 4 },
{ VCS_ARCH_OVERRIDE: "linux" },
{ VCS_LIC_EXPIRE_WARNING: 1 }
]

5
vendor/lowrisc_ip/dv/tools/dvsim/verilator.hjson vendored
View file

@ -43,6 +43,11 @@
]
// -- END --
// Remove {proj_root}/hw/foundry from FuseSoC cores search if it exists.
pre_build_cmds: ['''if [ -d {proj_root}/hw/foundry ]; then \
touch {proj_root}/hw/foundry/FUSESOC_IGNORE; \
fi''']
build_cmd: "fusesoc {fusesoc_cores_root_dirs} run"
ex_name: "{eval_cmd} echo \"{fusesoc_core}\" | cut -d: -f3"
run_cmd: "{build_dir}/sim-verilator/V{ex_name}"

10
vendor/lowrisc_ip/dv/tools/waves.tcl vendored
View file

@ -19,6 +19,7 @@ global tb_top
set wavedump_db "waves.$waves"
# TODO: convert this to a proc?
set fid ""
switch $waves {
"none" {
puts "INFO: Dumping waves is not enabled."
@ -39,7 +40,7 @@ switch $waves {
"vpd" {
checkEq simulator "vcs"
dump -file $wavedump_db -type VPD
set fid [dump -file $wavedump_db -type VPD]
}
"vcd" {
@ -76,13 +77,14 @@ if {$waves ne "none"} {
# simulation. It is useful in that case to only dump the relevant scopes of interest during debug.
#
# scope : Design / testbench hierarchy to dump waves. Defaults to $tb_top.
# fid : File ID returned by the dump command in the first step above.
# depth : Levels in the hierarchy to dump waves. Defaults to 0 (dump all levels).
# fsdb_flags : Additional string flags passed to fsdbDumpVars. Defaults to "+all".
# probe_flags : Additional string flags passed to probe command (Xcelium). Defaults to "-all".
# dump_flags : Additional string flags passed to dump command (VCS). Defaults to "-aggregates".
#
# Depending on the need, more such technlogy specific flags can be added in future.
proc wavedumpScope {scope {depth 0} {fsdb_flags "+all"} {probe_flags "-all"}
proc wavedumpScope {scope fid {depth 0} {fsdb_flags "+all"} {probe_flags "-all"}
{dump_flags "-aggregates"}} {
global simulator
global waves
@ -114,7 +116,7 @@ proc wavedumpScope {scope {depth 0} {fsdb_flags "+all"} {probe_flags "-all"}
"vpd" {
# The dump command switch -aggregates enables dumping of structs &
# arrays.
dump -add "$scope" -depth $depth $dump_flags
dump -add "$scope" -fid $fid -depth $depth $dump_flags
}
"vcd" {
@ -154,5 +156,5 @@ setDefault dump_tb_top 1
# By default, add the full test bench scope for wavedump.
if {$dump_tb_top == 1} {
wavedumpScope $tb_top
wavedumpScope $tb_top $fid
}

5
vendor/lowrisc_ip/dv/verilator/cpp/verilator_memutil.cc vendored
View file

@ -98,6 +98,7 @@ bool VerilatorMemUtil::ParseCLIArguments(int argc, char **argv,
{"rominit", required_argument, nullptr, 'r'},
{"raminit", required_argument, nullptr, 'm'},
{"flashinit", required_argument, nullptr, 'f'},
{"otpinit", required_argument, nullptr, 'o'},
{"meminit", required_argument, nullptr, 'l'},
{"verbose-mem-load", no_argument, nullptr, 'V'},
{"load-elf", required_argument, nullptr, 'E'},
@ -134,6 +135,10 @@ bool VerilatorMemUtil::ParseCLIArguments(int argc, char **argv,
load_args.push_back(
{.name = "flash", .filepath = optarg, .type = kMemImageUnknown});
break;
case 'o':
load_args.push_back(
{.name = "otp", .filepath = optarg, .type = kMemImageUnknown});
break;
case 'l':
if (strcasecmp(optarg, "list") == 0) {
mem_util_->PrintMemRegions();

10
vendor/lowrisc_ip/ip/prim/doc/prim_flash.md vendored
View file

@ -29,7 +29,7 @@ TestModeWidth | int | The number of test modes for a bank of flash
Name | In/Out | Description
------------------------|--------|---------------------------------
clk_i | input | Clock input
rst_n_i | input | Reset input
rst_ni | input | Reset input
flash_req_i | input | Inputs from flash protocol and physical controllers
flash_rsp_o | output | Outputs to flash protocol and physical controllers
prog_type_avail_o | output | Available program types in this flash wrapper: Currently there are only two types, program normal and program repair
@ -41,14 +41,14 @@ tdo_o | output | jtag tdo
bist_enable_i | input | lc_ctrl_pkg :: On for bist_enable input
scanmode_i | input | dft scanmode input
scan_en_i | input | dft scan shift input
scan_rst_n_i | input | dft scanmode reset
scan_rst_ni | input | dft scanmode reset
flash_power_ready_h_i | input | flash power is ready (high voltage connection)
flash_power_down_h_i | input | flash wrapper is powering down (high voltage connection)
flash_test_mode_a_i | input | flash test mode values (analog connection)
flash_test_voltage_h_i | input | flash test mode voltage (high voltage connection)
flash_err_o | output | flash level error interrupt indication, cleared on write 1 to status register
flash_alert_po | output | flash positive detector alert
flash_alert_no | output | flash negative detector alert
flash_alert_po | output | flash positive detector alert
flash_alert_no | output | flash negative detector alert
flash_alert_ack | input | single pulse ack
flash_alert_trig | input | alert force trig by SW
tl_i | input | TL_UL interface for rd/wr registers access
@ -148,7 +148,7 @@ A program type not supported by the wrapper, indicated through `prog_type_avail`
## Erase Suspend
Since erase operations can take a significant amount of time, sometimes it is necessary for software or other components to suspend the operation.
The suspend operation input request starts with `erase_suspend_req` assertion. Flash wrapper circuit acks when wrapper starts suspend.
The suspend operation input request starts with `erase_suspend_req` assertion. Flash wrapper circuit acks when wrapper starts suspend.
When the erase suspend completes, the flash wrapper circuitry also asserts `done` for the ongoing erase transaction to ensure all hardware gracefully completes.
The following is an example diagram

1
vendor/lowrisc_ip/ip/prim/dv/prim_lfsr/prim_lfsr_sim.core vendored
View file

@ -13,6 +13,7 @@ filesets:
files_dv:
depend:
- lowrisc:dv:dv_utils
- lowrisc:dv:dv_test_status
- lowrisc:dv:common_ifs
files:
- tb/prim_lfsr_tb.sv

23
vendor/lowrisc_ip/ip/prim/dv/prim_lfsr/tb/prim_lfsr_tb.sv vendored
View file

@ -166,7 +166,7 @@ module prim_lfsr_tb;
lfsr_en = '0;
err = '0;
main_clk.set_period_ns(ClkPeriod);
main_clk.set_period_ps(ClkPeriod);
main_clk.set_active();
main_clk.apply_reset();
@ -209,19 +209,18 @@ module prim_lfsr_tb;
end
end
if (!err) begin
$display("All LFSRs from %0d bit to %0d have maximum length!",
MinLfsrDw, MaxLfsrDw);
// signature for makefile
$display("TEST PASSED CHECKS");
end else begin
$display("One or more checks have failed!");
// signature for makefile
$display("TEST FAILED CHECKS");
end
if (!err) $display("All LFSRs from %0d bit to %0d have maximum length!", MinLfsrDw, MaxLfsrDw);
dv_test_status_pkg::dv_test_status(.passed(!err));
$finish();
end
// TODO: perhaps wrap this in a macro?
initial begin
bit poll_for_stop = 1'b1;
int unsigned poll_for_stop_interval_ns = 1000;
void'($value$plusargs("poll_for_stop=%0b", poll_for_stop));
void'($value$plusargs("poll_for_stop_interval_ns=%0d", poll_for_stop_interval_ns));
if (poll_for_stop) dv_utils_pkg::poll_for_stop(.interval_ns(poll_for_stop_interval_ns));
end
endmodule : prim_lfsr_tb

17
vendor/lowrisc_ip/ip/prim/dv/prim_present/data/prim_present_testplan.hjson vendored
View file

@ -1,17 +0,0 @@
// Copyright lowRISC contributors.
// Licensed under the Apache License, Version 2.0, see LICENSE for details.
// SPDX-License-Identifier: Apache-2.0
{
name: "prim_present"
import_testplans: []
entries: [
{
name: smoke
desc: '''Simple PRESENT test - feed golden and random testvectors into
both the encryption and decryption algorithms and verify that all
outputs match those from the reference model.'''
milestone: V2
tests: ["prim_present_smoke"]
}
]
}

3
vendor/lowrisc_ip/ip/prim/dv/prim_present/prim_present_sim.core vendored
View file

@ -12,6 +12,9 @@ filesets:
files_dv:
depend:
- lowrisc:dv:dv_utils
- lowrisc:dv:dv_macros
- lowrisc:dv:dv_test_status
- lowrisc:dv:crypto_dpi_present:0.1
files:
- tb/prim_present_tb.sv

7
vendor/lowrisc_ip/ip/prim/dv/prim_present/prim_present_sim_cfg.hjson vendored
View file

@ -17,9 +17,6 @@
// Fusesoc core file used for building the file list.
fusesoc_core: lowrisc:dv:prim_present_sim:0.1
// Testplan hjson file.
testplan: "{proj_root}/hw/ip/prim/dv/prim_present/data/prim_present_testplan.hjson"
// Import additional common sim cfg files.
import_cfgs: ["{proj_root}/hw/dv/tools/dvsim/common_sim_cfg.hjson"]
@ -36,7 +33,7 @@
// List of test specifications.
tests: [
{
name: prim_present_smoke
name: prim_present_test
}
]
@ -44,7 +41,7 @@
regressions: [
{
name: smoke
tests: ["prim_present_smoke"]
tests: ["prim_present_test"]
}
]
}

35
vendor/lowrisc_ip/ip/prim/dv/prim_present/tb/prim_present_tb.sv vendored
View file

@ -11,6 +11,7 @@
// widths remain untested.
module prim_present_tb;
`include "dv_macros.svh"
//////////////////////////////////////////////////////
// config
@ -42,6 +43,10 @@ module prim_present_tb;
// this parameter is required for the DPI model.
localparam bit KeySize80 = (KeyWidth == 80);
// This bit can be set from the command line to indicate that we are running a smoke regression,
// and to run just a single iteration of the test.
// This helps drastically reduce runtimes in the CI flows.
bit smoke_test;
//////////////////////////////////////////////////////
// DUTs for both encryption and decryption
@ -94,16 +99,13 @@ module prim_present_tb;
crypto_dpi_present_pkg::sv_dpi_present_get_key_schedule(key, KeySize80, key_schedule);
$display("Starting encryption pass with data[0x%0x] and key[0x%0x]!", plaintext, key);
check_encryption(plaintext, key, key_schedule, encrypted_text);
$display("Starting decryption pass!");
check_decryption(encrypted_text, key, key_out[Encrypt]);
endtask
// Helper task to drive plaintext and key into each encryption instance.
// Calls a subroutine to perform checks on the outputs (once they are available).
task automatic check_encryption(input bit [DataWidth-1:0] plaintext,
@ -194,7 +196,7 @@ module prim_present_tb;
break;
end
end
if (error) $fatal("TEST FAILED CHECKS");
if (error) dv_test_status_pkg::dv_test_status(.passed(1'b0));
endtask
@ -203,6 +205,8 @@ module prim_present_tb;
//////////////////////////////////////////////////////
initial begin : p_stimuli
int num_trans;
string msg_id = $sformatf("%m");
// The key and plaintext/ciphertext to be fed into PRESENT instances.
bit [KeyWidth-1:0] key;
@ -231,22 +235,27 @@ module prim_present_tb;
test_present(plaintext, key);
// Test random vectors
for (int i = 0; i < 5000; i++) begin
if (!std::randomize(plaintext)) begin
$fatal("Randomization of plaintext failed!");
end
if (!std::randomize(key)) begin
$fatal("Randomization of key failed!");
end
void'($value$plusargs("smoke_test=%0b", smoke_test));
num_trans = smoke_test ? 1 : $urandom_range(5000, 25000);
for (int i = 0; i < num_trans; i++) begin
`DV_CHECK_STD_RANDOMIZE_FATAL(plaintext, "", msg_id)
`DV_CHECK_STD_RANDOMIZE_FATAL(key, "", msg_id)
test_present(plaintext, key);
end
// Final error checking and print out the test signature (expected by simulation flow).
$display("All encryption and decryption passes were successful!");
$display("TEST PASSED CHECKS");
dv_test_status_pkg::dv_test_status(.passed(1'b1));
$finish();
end
// TODO: perhaps wrap this in a macro?
initial begin
bit poll_for_stop = 1'b1;
int unsigned poll_for_stop_interval_ns = 1000;
void'($value$plusargs("poll_for_stop=%0b", poll_for_stop));
void'($value$plusargs("poll_for_stop_interval_ns=%0d", poll_for_stop_interval_ns));
if (poll_for_stop) dv_utils_pkg::poll_for_stop(.interval_ns(poll_for_stop_interval_ns));
end
endmodule : prim_present_tb

4
vendor/lowrisc_ip/ip/prim/dv/prim_prince/prim_prince_sim.core vendored
View file

@ -12,9 +12,11 @@ filesets:
files_dv:
depend:
- lowrisc:dv:crypto_dpi_prince:0.1
- lowrisc:dv:dv_utils
- lowrisc:dv:dv_macros
- lowrisc:dv:common_ifs
- lowrisc:dv:dv_test_status
- lowrisc:dv:crypto_dpi_prince
files:
- tb/prim_prince_tb.sv
file_type: systemVerilogSource

55
vendor/lowrisc_ip/ip/prim/dv/prim_prince/tb/prim_prince_tb.sv vendored
View file

@ -11,6 +11,7 @@
// widths remain untested.
module prim_prince_tb;
`include "dv_macros.svh"
//////////////////////////////////////////////////////
// config
@ -44,6 +45,11 @@ module prim_prince_tb;
localparam time ClkPeriod = 10000;
// This bit can be set from the command line to indicate that we are running a smoke regression,
// and to run just a single iteration of the test.
// This helps drastically reduce runtimes in the CI flows.
bit smoke_test;
//////////////////////////////////////////////////////
// Clock interface
//////////////////////////////////////////////////////
@ -100,15 +106,14 @@ module prim_prince_tb;
bit [KeyWidth-1:0] key);
bit [1:0][1:0][NumRoundsHalf-1:0][DataWidth-1:0] encrypted_text;
$display("Starting encryption with data[0x%0x] and key[0x%0x]!", plaintext, key);
check_encryption(plaintext, key, encrypted_text);
$display("Starting decryption pass!");
check_decryption(encrypted_text, key);
endtask
// Helper task to drive plaintext and key into each encryption instance.
// Calls a subroutine to perform checks on the outputs (once they are available).
task automatic check_encryption(
@ -209,35 +214,36 @@ module prim_prince_tb;
err_msg = {$sformatf("%s mismatch in %s design with %0d rounds and old key schedule!\n",
msg, reg_msg, i+1),
$sformatf("Expected[0x%0x] - Actual[0x%0x]\n", expected_text_old_sched[i][j],
actual_text_old_sched[i][j]),
"TEST FAILED CHECKS"};
$fatal(err_msg);
actual_text_old_sched[i][j])};
$error(err_msg);
dv_test_status_pkg::dv_test_status(.passed(1'b0));
end
// compare outputs generated using new key schedule.
if (expected_text_new_sched[i][j] != actual_text_new_sched[i][j]) begin
err_msg = {$sformatf("%s mismatch in %s design with %0d rounds and old key schedule!\n",
msg, reg_msg, i+1),
$sformatf("Expected[0x%0x] - Actual[0x%0x]\n", expected_text_new_sched[i][j],
actual_text_new_sched[i][j]),
"TEST FAILED CHECKS"};
$fatal(err_msg);
actual_text_new_sched[i][j])};
$error(err_msg);
dv_test_status_pkg::dv_test_status(.passed(1'b0));
end
end
end
endtask
//////////////////////////////////////////////////////
// main testbench body
//////////////////////////////////////////////////////
initial begin : p_stimuli
int num_trans;
string msg_id = $sformatf("%m");
// The key and plaintext/ciphertext to be fed into PRINCE instances.
bit [KeyWidth/2-1:0] k0, k1;
bit [DataWidth-1:0] plaintext;
clk_if.set_period_ns(ClkPeriod);
clk_if.set_period_ps(ClkPeriod);
clk_if.set_active();
clk_if.apply_reset();
$timeformat(-12, 0, " ps", 12);
@ -273,25 +279,28 @@ module prim_prince_tb;
test_prince(plaintext, {k1, k0});
// Test random vectors
for (int i = 0; i < 25000; i++) begin
if (!std::randomize(plaintext)) begin
$fatal("Randomization of plaintext failed!");
end
if (!std::randomize(k0)) begin
$fatal("Randomization of k0 failed!");
end
if (!std::randomize(k1)) begin
$fatal("Randomization of k1 failed!");
end
void'($value$plusargs("smoke_test=%0b", smoke_test));
num_trans = smoke_test ? 1 : $urandom_range(5000, 25000);
for (int i = 0; i < num_trans; i++) begin
`DV_CHECK_STD_RANDOMIZE_FATAL(plaintext, "", msg_id)
`DV_CHECK_STD_RANDOMIZE_FATAL(k0, "", msg_id)
`DV_CHECK_STD_RANDOMIZE_FATAL(k1, "", msg_id)
test_prince(plaintext, {k1, k0});
end
// Final error checking and print out the test signature (expected by simulation flow).
$display("All encryption and decryption passes were successful!");
$display("TEST PASSED CHECKS");
dv_test_status_pkg::dv_test_status(.passed(1'b1));
$finish();
end
// TODO: perhaps wrap this in a macro?
initial begin
bit poll_for_stop = 1'b1;
int unsigned poll_for_stop_interval_ns = 1000;
void'($value$plusargs("poll_for_stop=%0b", poll_for_stop));
void'($value$plusargs("poll_for_stop_interval_ns=%0d", poll_for_stop_interval_ns));
if (poll_for_stop) dv_utils_pkg::poll_for_stop(.interval_ns(poll_for_stop_interval_ns));
end
endmodule : prim_prince_tb

31
vendor/lowrisc_ip/ip/prim/fpv/prim_alert_rxtx_async_fatal_fpv.core vendored Normal file
View file

@ -0,0 +1,31 @@
CAPI=2:
# Copyright lowRISC contributors.
# Licensed under the Apache License, Version 2.0, see LICENSE for details.
# SPDX-License-Identifier: Apache-2.0
name: "lowrisc:fpv:prim_alert_rxtx_async_fatal_fpv:0.1"
description: "ALERT_HANDLER rxtx async fatal FPV target"
filesets:
files_formal:
depend:
- lowrisc:prim:all
files:
- vip/prim_alert_rxtx_async_assert_fpv.sv
- tb/prim_alert_rxtx_async_fatal_fpv.sv
- tb/prim_alert_rxtx_async_fatal_bind_fpv.sv
file_type: systemVerilogSource
targets:
default: &default_target
# note, this setting is just used
# to generate a file list for jg
default_tool: icarus
filesets:
- files_formal
toplevel:
- prim_alert_rxtx_async_fatal_fpv
formal:
<<: *default_target
lint:
<<: *default_target

31
vendor/lowrisc_ip/ip/prim/fpv/prim_alert_rxtx_fatal_fpv.core vendored Normal file
View file

@ -0,0 +1,31 @@
CAPI=2:
# Copyright lowRISC contributors.
# Licensed under the Apache License, Version 2.0, see LICENSE for details.
# SPDX-License-Identifier: Apache-2.0
name: "lowrisc:fpv:prim_alert_rxtx_fatal_fpv:0.1"
description: "ALERT_HANDLER FPV target"
filesets:
files_formal:
depend:
- lowrisc:prim:all
files:
- vip/prim_alert_rxtx_assert_fpv.sv
- tb/prim_alert_rxtx_fatal_fpv.sv
- tb/prim_alert_rxtx_fatal_bind_fpv.sv
file_type: systemVerilogSource
targets:
default: &default_target
# note, this setting is just used
# to generate a file list for jg
default_tool: icarus
filesets:
- files_formal
toplevel:
- prim_alert_rxtx_fatal_fpv
formal:
<<: *default_target
lint:
<<: *default_target

33
vendor/lowrisc_ip/ip/prim/fpv/prim_secded_22_16_fpv.core vendored Normal file
View file

@ -0,0 +1,33 @@
CAPI=2:
# Copyright lowRISC contributors.
# Licensed under the Apache License, Version 2.0, see LICENSE for details.
# SPDX-License-Identifier: Apache-2.0
name: "lowrisc:fpv:prim_secded_22_16_fpv:0.1"
description: "SECDED FPV target"
filesets:
files_formal:
depend:
- lowrisc:prim:all
- lowrisc:prim:secded
files:
- vip/prim_secded_22_16_assert_fpv.sv
- tb/prim_secded_22_16_fpv.sv
- tb/prim_secded_22_16_bind_fpv.sv
file_type: systemVerilogSource
targets:
default: &default_target
# note, this setting is just used
# to generate a file list for jg
default_tool: icarus
filesets:
- files_formal
toplevel:
- prim_secded_22_16_fpv
formal:
<<: *default_target
lint:
<<: *default_target

33
vendor/lowrisc_ip/ip/prim/fpv/prim_secded_28_22_fpv.core vendored Normal file
View file

@ -0,0 +1,33 @@
CAPI=2:
# Copyright lowRISC contributors.
# Licensed under the Apache License, Version 2.0, see LICENSE for details.
# SPDX-License-Identifier: Apache-2.0
name: "lowrisc:fpv:prim_secded_28_22_fpv:0.1"
description: "SECDED FPV target"
filesets:
files_formal:
depend:
- lowrisc:prim:all
- lowrisc:prim:secded
files:
- vip/prim_secded_28_22_assert_fpv.sv
- tb/prim_secded_28_22_fpv.sv
- tb/prim_secded_28_22_bind_fpv.sv
file_type: systemVerilogSource
targets:
default: &default_target
# note, this setting is just used
# to generate a file list for jg
default_tool: icarus
filesets:
- files_formal
toplevel:
- prim_secded_28_22_fpv
formal:
<<: *default_target
lint:
<<: *default_target

33
vendor/lowrisc_ip/ip/prim/fpv/prim_secded_39_32_fpv.core vendored Normal file
View file

@ -0,0 +1,33 @@
CAPI=2:
# Copyright lowRISC contributors.
# Licensed under the Apache License, Version 2.0, see LICENSE for details.
# SPDX-License-Identifier: Apache-2.0
name: "lowrisc:fpv:prim_secded_39_32_fpv:0.1"
description: "SECDED FPV target"
filesets:
files_formal:
depend:
- lowrisc:prim:all
- lowrisc:prim:secded
files:
- vip/prim_secded_39_32_assert_fpv.sv
- tb/prim_secded_39_32_fpv.sv
- tb/prim_secded_39_32_bind_fpv.sv
file_type: systemVerilogSource
targets:
default: &default_target
# note, this setting is just used
# to generate a file list for jg
default_tool: icarus
filesets:
- files_formal
toplevel:
- prim_secded_39_32_fpv
formal:
<<: *default_target
lint:
<<: *default_target

33
vendor/lowrisc_ip/ip/prim/fpv/prim_secded_64_57_fpv.core vendored Normal file
View file

@ -0,0 +1,33 @@
CAPI=2:
# Copyright lowRISC contributors.
# Licensed under the Apache License, Version 2.0, see LICENSE for details.
# SPDX-License-Identifier: Apache-2.0
name: "lowrisc:fpv:prim_secded_64_57_fpv:0.1"
description: "SECDED FPV target"
filesets:
files_formal:
depend:
- lowrisc:prim:all
- lowrisc:prim:secded
files:
- vip/prim_secded_64_57_assert_fpv.sv
- tb/prim_secded_64_57_fpv.sv
- tb/prim_secded_64_57_bind_fpv.sv
file_type: systemVerilogSource
targets:
default: &default_target
# note, this setting is just used
# to generate a file list for jg
default_tool: icarus
filesets:
- files_formal
toplevel:
- prim_secded_64_57_fpv
formal:
<<: *default_target
lint:
<<: *default_target

33
vendor/lowrisc_ip/ip/prim/fpv/prim_secded_72_64_fpv.core vendored Normal file
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@ -0,0 +1,33 @@
CAPI=2:
# Copyright lowRISC contributors.
# Licensed under the Apache License, Version 2.0, see LICENSE for details.
# SPDX-License-Identifier: Apache-2.0
name: "lowrisc:fpv:prim_secded_72_64_fpv:0.1"
description: "SECDED FPV target"
filesets:
files_formal:
depend:
- lowrisc:prim:all
- lowrisc:prim:secded
files:
- vip/prim_secded_72_64_assert_fpv.sv
- tb/prim_secded_72_64_fpv.sv
- tb/prim_secded_72_64_bind_fpv.sv
file_type: systemVerilogSource
targets:
default: &default_target
# note, this setting is just used
# to generate a file list for jg
default_tool: icarus
filesets:
- files_formal
toplevel:
- prim_secded_72_64_fpv
formal:
<<: *default_target
lint:
<<: *default_target

33
vendor/lowrisc_ip/ip/prim/fpv/prim_secded_hamming_22_16_fpv.core vendored Normal file
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@ -0,0 +1,33 @@
CAPI=2:
# Copyright lowRISC contributors.
# Licensed under the Apache License, Version 2.0, see LICENSE for details.
# SPDX-License-Identifier: Apache-2.0
name: "lowrisc:fpv:prim_secded_hamming_22_16_fpv:0.1"
description: "SECDED FPV target"
filesets:
files_formal:
depend:
- lowrisc:prim:all
- lowrisc:prim:secded
files:
- vip/prim_secded_hamming_22_16_assert_fpv.sv
- tb/prim_secded_hamming_22_16_fpv.sv
- tb/prim_secded_hamming_22_16_bind_fpv.sv
file_type: systemVerilogSource
targets:
default: &default_target
# note, this setting is just used
# to generate a file list for jg
default_tool: icarus
filesets:
- files_formal
toplevel:
- prim_secded_hamming_22_16_fpv
formal:
<<: *default_target
lint:
<<: *default_target

33
vendor/lowrisc_ip/ip/prim/fpv/prim_secded_hamming_39_32_fpv.core vendored Normal file
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@ -0,0 +1,33 @@
CAPI=2:
# Copyright lowRISC contributors.
# Licensed under the Apache License, Version 2.0, see LICENSE for details.
# SPDX-License-Identifier: Apache-2.0
name: "lowrisc:fpv:prim_secded_hamming_39_32_fpv:0.1"
description: "SECDED FPV target"
filesets:
files_formal:
depend:
- lowrisc:prim:all
- lowrisc:prim:secded
files:
- vip/prim_secded_hamming_39_32_assert_fpv.sv
- tb/prim_secded_hamming_39_32_fpv.sv
- tb/prim_secded_hamming_39_32_bind_fpv.sv
file_type: systemVerilogSource
targets:
default: &default_target
# note, this setting is just used
# to generate a file list for jg
default_tool: icarus
filesets:
- files_formal
toplevel:
- prim_secded_hamming_39_32_fpv
formal:
<<: *default_target
lint:
<<: *default_target

33
vendor/lowrisc_ip/ip/prim/fpv/prim_secded_hamming_72_64_fpv.core vendored Normal file
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@ -0,0 +1,33 @@
CAPI=2:
# Copyright lowRISC contributors.
# Licensed under the Apache License, Version 2.0, see LICENSE for details.
# SPDX-License-Identifier: Apache-2.0
name: "lowrisc:fpv:prim_secded_hamming_72_64_fpv:0.1"
description: "SECDED FPV target"
filesets:
files_formal:
depend:
- lowrisc:prim:all
- lowrisc:prim:secded
files:
- vip/prim_secded_hamming_72_64_assert_fpv.sv
- tb/prim_secded_hamming_72_64_fpv.sv
- tb/prim_secded_hamming_72_64_bind_fpv.sv
file_type: systemVerilogSource
targets:
default: &default_target
# note, this setting is just used
# to generate a file list for jg
default_tool: icarus
filesets:
- files_formal
toplevel:
- prim_secded_hamming_72_64_fpv
formal:
<<: *default_target
lint:
<<: *default_target

2
vendor/lowrisc_ip/ip/prim/fpv/tb/prim_alert_rxtx_async_bind_fpv.sv vendored
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@ -18,8 +18,10 @@ module prim_alert_rxtx_async_bind_fpv;
.alert_err_pi,
.alert_err_ni,
.alert_skew_i,
.alert_test_i,
.alert_req_i,
.alert_ack_o,
.alert_state_o,
.ping_req_i,
.ping_ok_o,
.integ_fail_o,

31
vendor/lowrisc_ip/ip/prim/fpv/tb/prim_alert_rxtx_async_fatal_bind_fpv.sv vendored Normal file
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@ -0,0 +1,31 @@
// Copyright lowRISC contributors.
// Licensed under the Apache License, Version 2.0, see LICENSE for details.
// SPDX-License-Identifier: Apache-2.0
//
module prim_alert_rxtx_async_fatal_bind_fpv;
bind prim_alert_rxtx_async_fpv
prim_alert_rxtx_async_assert_fpv prim_alert_rxtx_async_assert_fpv (
.clk_i,
.rst_ni,
.ping_err_pi,
.ping_err_ni,
.ping_skew_i,
.ack_err_pi,
.ack_err_ni,
.ack_skew_i,
.alert_err_pi,
.alert_err_ni,
.alert_skew_i,
.alert_test_i,
.alert_req_i,
.alert_ack_o,
.alert_state_o,
.ping_req_i,
.ping_ok_o,
.integ_fail_o,
.alert_o
);
endmodule : prim_alert_rxtx_async_fatal_bind_fpv

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@ -0,0 +1,117 @@
// Copyright lowRISC contributors.
// Licensed under the Apache License, Version 2.0, see LICENSE for details.
// SPDX-License-Identifier: Apache-2.0
//
// Testbench module for alert sender/receiver pair. Intended to use with
// a formal tool.
module prim_alert_rxtx_async_fatal_fpv
import prim_alert_pkg::*;
import prim_esc_pkg::*;
(
input clk_i,
input rst_ni,
// for sigint error and skew injection only
input ping_err_pi,
input ping_err_ni,
input [1:0] ping_skew_i,
input ack_err_pi,
input ack_err_ni,
input [1:0] ack_skew_i,
input alert_err_pi,
input alert_err_ni,
input [1:0] alert_skew_i,
// normal I/Os
input alert_test_i,
input alert_req_i,
input ping_req_i,
output logic alert_ack_o,
output logic alert_state_o,
output logic ping_ok_o,
output logic integ_fail_o,
output logic alert_o
);
// asynchronous case
localparam bit AsyncOn = 1'b1;
localparam bit IsFatal = 1'b1;
logic ping_pd;
logic ping_nd;
logic ack_pd;
logic ack_nd;
logic alert_pd;
logic alert_nd;
alert_rx_t alert_rx_out, alert_rx_in;
alert_tx_t alert_tx_out, alert_tx_in;
// for the purposes of FPV, we currently emulate the asynchronous transition
// only in terms of the skew it may introduce (which is limited to +- 1 cycle)
logic [1:0] ping_pq;
logic [1:0] ping_nq;
logic [1:0] ack_pq;
logic [1:0] ack_nq;
logic [1:0] alert_pq;
logic [1:0] alert_nq;
assign ping_pd = alert_rx_out.ping_p;
assign ping_nd = alert_rx_out.ping_n;
assign ack_pd = alert_rx_out.ack_p;
assign ack_nd = alert_rx_out.ack_n;
assign alert_rx_in.ping_p = ping_pq[ping_skew_i[0]] ^ ping_err_pi;
assign alert_rx_in.ping_n = ping_nq[ping_skew_i[1]] ^ ping_err_ni;
assign alert_rx_in.ack_p = ack_pq[ack_skew_i[0]] ^ ack_err_pi;
assign alert_rx_in.ack_n = ack_nq[ack_skew_i[1]] ^ ack_err_ni;
assign alert_pd = alert_tx_out.alert_p;
assign alert_nd = alert_tx_out.alert_n;
assign alert_tx_in.alert_p = alert_pq[alert_skew_i[0]] ^ alert_err_pi;
assign alert_tx_in.alert_n = alert_nq[alert_skew_i[1]] ^ alert_err_ni;
prim_alert_sender #(
.AsyncOn ( AsyncOn ),
.IsFatal ( IsFatal )
) i_prim_alert_sender (
.clk_i ,
.rst_ni ,
.alert_test_i,
.alert_req_i,
.alert_ack_o,
.alert_state_o,
.alert_rx_i ( alert_rx_in ),
.alert_tx_o ( alert_tx_out )
);
prim_alert_receiver #(
.AsyncOn ( AsyncOn )
) i_prim_alert_receiver (
.clk_i ,
.rst_ni ,
.ping_req_i ,
.ping_ok_o ,
.integ_fail_o ,
.alert_o ,
.alert_rx_o ( alert_rx_out ),
.alert_tx_i ( alert_tx_in )
);
always_ff @(posedge clk_i or negedge rst_ni) begin : p_skew_delay
if (!rst_ni) begin
ping_pq <= '0;
ping_nq <= '1;
ack_pq <= '0;
ack_nq <= '1;
alert_pq <= '0;
alert_nq <= '1;
end else begin
ping_pq <= {ping_pq [$high(ping_pq )-1:0], ping_pd};
ping_nq <= {ping_nq [$high(ping_nq )-1:0], ping_nd};
ack_pq <= {ack_pq [$high(ack_pq )-1:0], ack_pd};
ack_nq <= {ack_nq [$high(ack_nq )-1:0], ack_nd};
alert_pq <= {alert_pq[$high(alert_pq)-1:0], alert_pd};
alert_nq <= {alert_nq[$high(alert_nq)-1:0], alert_nd};
end
end
endmodule : prim_alert_rxtx_async_fatal_fpv

4
vendor/lowrisc_ip/ip/prim/fpv/tb/prim_alert_rxtx_async_fpv.sv vendored
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@ -22,9 +22,11 @@ module prim_alert_rxtx_async_fpv
input alert_err_ni,
input [1:0] alert_skew_i,
// normal I/Os
input alert_test_i,
input alert_req_i,
input ping_req_i,
output logic alert_ack_o,
output logic alert_state_o,
output logic ping_ok_o,
output logic integ_fail_o,
output logic alert_o
@ -71,8 +73,10 @@ module prim_alert_rxtx_async_fpv
) i_prim_alert_sender (
.clk_i ,
.rst_ni ,
.alert_test_i,
.alert_req_i,
.alert_ack_o,
.alert_state_o,
.alert_rx_i ( alert_rx_in ),
.alert_tx_o ( alert_tx_out )
);

2
vendor/lowrisc_ip/ip/prim/fpv/tb/prim_alert_rxtx_bind_fpv.sv vendored
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@ -15,8 +15,10 @@ module prim_alert_rxtx_bind_fpv;
.ack_err_ni,
.alert_err_pi,
.alert_err_ni,
.alert_test_i,
.alert_req_i,
.alert_ack_o,
.alert_state_o,
.ping_req_i,
.ping_ok_o,
.integ_fail_o,

29
vendor/lowrisc_ip/ip/prim/fpv/tb/prim_alert_rxtx_fatal_bind_fpv.sv vendored Normal file
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@ -0,0 +1,29 @@
// Copyright lowRISC contributors.
// Licensed under the Apache License, Version 2.0, see LICENSE for details.
// SPDX-License-Identifier: Apache-2.0
//
module prim_alert_rxtx_fatal_bind_fpv;
// this reuses the synchronous VIP.
bind prim_alert_rxtx_fpv
prim_alert_rxtx_assert_fpv prim_alert_rxtx_assert_fpv (
.clk_i,
.rst_ni,
.ping_err_pi,
.ping_err_ni,
.ack_err_pi,
.ack_err_ni,
.alert_err_pi,
.alert_err_ni,
.alert_test_i,
.alert_req_i,
.alert_ack_o,
.alert_state_o,
.ping_req_i,
.ping_ok_o,
.integ_fail_o,
.alert_o
);
endmodule : prim_alert_rxtx_fatal_bind_fpv

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vendor/lowrisc_ip/ip/prim/fpv/tb/prim_alert_rxtx_fatal_fpv.sv vendored Normal file
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@ -0,0 +1,74 @@
// Copyright lowRISC contributors.
// Licensed under the Apache License, Version 2.0, see LICENSE for details.
// SPDX-License-Identifier: Apache-2.0
//
// Testbench module for alert sender/receiver pair. Intended to use with
// a formal tool.
module prim_alert_rxtx_fatal_fpv
import prim_alert_pkg::*;
import prim_esc_pkg::*;
(
input clk_i,
input rst_ni,
// for sigint error injection only
input ping_err_pi,
input ping_err_ni,
input ack_err_pi,
input ack_err_ni,
input alert_err_pi,
input alert_err_ni,
// normal I/Os
input alert_test_i,
input alert_req_i,
input ping_req_i,
output logic alert_ack_o,
output logic alert_state_o,
output logic ping_ok_o,
output logic integ_fail_o,
output logic alert_o
);
// synchronous case
localparam bit AsyncOn = 1'b0;
localparam bit IsFatal = 1'b1;
alert_rx_t alert_rx_out, alert_rx_in;
alert_tx_t alert_tx_out, alert_tx_in;
assign alert_rx_in.ping_p = alert_rx_out.ping_p ^ ping_err_pi;
assign alert_rx_in.ping_n = alert_rx_out.ping_n ^ ping_err_ni;
assign alert_rx_in.ack_p = alert_rx_out.ack_p ^ ack_err_pi;
assign alert_rx_in.ack_n = alert_rx_out.ack_n ^ ack_err_ni;
assign alert_tx_in.alert_p = alert_tx_out.alert_p ^ alert_err_pi;
assign alert_tx_in.alert_n = alert_tx_out.alert_n ^ alert_err_ni;
prim_alert_sender #(
.AsyncOn ( AsyncOn ),
.IsFatal ( IsFatal )
) i_prim_alert_sender (
.clk_i ,
.rst_ni ,
.alert_test_i,
.alert_req_i,
.alert_ack_o,
.alert_state_o,
.alert_rx_i ( alert_rx_in ),
.alert_tx_o ( alert_tx_out )
);
prim_alert_receiver #(
.AsyncOn ( AsyncOn )
) i_prim_alert_receiver (
.clk_i ,
.rst_ni ,
.ping_req_i ,
.ping_ok_o ,
.integ_fail_o ,
.alert_o ,
.alert_rx_o ( alert_rx_out ),
.alert_tx_i ( alert_tx_in )
);
endmodule : prim_alert_rxtx_fatal_fpv

4
vendor/lowrisc_ip/ip/prim/fpv/tb/prim_alert_rxtx_fpv.sv vendored
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@ -19,9 +19,11 @@ module prim_alert_rxtx_fpv
input alert_err_pi,
input alert_err_ni,
// normal I/Os
input alert_test_i,
input alert_req_i,
input ping_req_i,
output logic alert_ack_o,
output logic alert_state_o,
output logic ping_ok_o,
output logic integ_fail_o,
output logic alert_o
@ -46,8 +48,10 @@ module prim_alert_rxtx_fpv
) i_prim_alert_sender (
.clk_i ,
.rst_ni ,
.alert_test_i,
.alert_req_i,
.alert_ack_o,
.alert_state_o,
.alert_rx_i ( alert_rx_in ),
.alert_tx_o ( alert_tx_out )
);

20
vendor/lowrisc_ip/ip/prim/fpv/tb/prim_secded_22_16_bind_fpv.sv vendored Normal file
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@ -0,0 +1,20 @@
// Copyright lowRISC contributors.
// Licensed under the Apache License, Version 2.0, see LICENSE for details.
// SPDX-License-Identifier: Apache-2.0
//
// SECDED FPV bind file generated by util/design/secded_gen.py
module prim_secded_22_16_bind_fpv;
bind prim_secded_22_16_fpv
prim_secded_22_16_assert_fpv prim_secded_22_16_assert_fpv (
.clk_i,
.rst_ni,
.in,
.d_o,
.syndrome_o,
.err_o,
.error_inject_i
);
endmodule : prim_secded_22_16_bind_fpv

31
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@ -0,0 +1,31 @@
// Copyright lowRISC contributors.
// Licensed under the Apache License, Version 2.0, see LICENSE for details.
// SPDX-License-Identifier: Apache-2.0
//
// SECDED FPV testbench generated by util/design/secded_gen.py
module prim_secded_22_16_fpv (
input clk_i,
input rst_ni,
input [15:0] in,
output logic [15:0] d_o,
output logic [5:0] syndrome_o,
output logic [1:0] err_o,
input [21:0] error_inject_i
);
logic [21:0] data_enc;
prim_secded_22_16_enc prim_secded_22_16_enc (
.in,
.out(data_enc)
);
prim_secded_22_16_dec prim_secded_22_16_dec (
.in(data_enc ^ error_inject_i),
.d_o,
.syndrome_o,
.err_o
);
endmodule : prim_secded_22_16_fpv

20
vendor/lowrisc_ip/ip/prim/fpv/tb/prim_secded_28_22_bind_fpv.sv vendored Normal file
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@ -0,0 +1,20 @@
// Copyright lowRISC contributors.
// Licensed under the Apache License, Version 2.0, see LICENSE for details.
// SPDX-License-Identifier: Apache-2.0
//
// SECDED FPV bind file generated by util/design/secded_gen.py
module prim_secded_28_22_bind_fpv;
bind prim_secded_28_22_fpv
prim_secded_28_22_assert_fpv prim_secded_28_22_assert_fpv (
.clk_i,
.rst_ni,
.in,
.d_o,
.syndrome_o,
.err_o,
.error_inject_i
);
endmodule : prim_secded_28_22_bind_fpv

31
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@ -0,0 +1,31 @@
// Copyright lowRISC contributors.
// Licensed under the Apache License, Version 2.0, see LICENSE for details.
// SPDX-License-Identifier: Apache-2.0
//
// SECDED FPV testbench generated by util/design/secded_gen.py
module prim_secded_28_22_fpv (
input clk_i,
input rst_ni,
input [21:0] in,
output logic [21:0] d_o,
output logic [5:0] syndrome_o,
output logic [1:0] err_o,
input [27:0] error_inject_i
);
logic [27:0] data_enc;
prim_secded_28_22_enc prim_secded_28_22_enc (
.in,
.out(data_enc)
);
prim_secded_28_22_dec prim_secded_28_22_dec (
.in(data_enc ^ error_inject_i),
.d_o,
.syndrome_o,
.err_o
);
endmodule : prim_secded_28_22_fpv

20
vendor/lowrisc_ip/ip/prim/fpv/tb/prim_secded_39_32_bind_fpv.sv vendored Normal file
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@ -0,0 +1,20 @@
// Copyright lowRISC contributors.
// Licensed under the Apache License, Version 2.0, see LICENSE for details.
// SPDX-License-Identifier: Apache-2.0
//
// SECDED FPV bind file generated by util/design/secded_gen.py
module prim_secded_39_32_bind_fpv;
bind prim_secded_39_32_fpv
prim_secded_39_32_assert_fpv prim_secded_39_32_assert_fpv (
.clk_i,
.rst_ni,
.in,
.d_o,
.syndrome_o,
.err_o,
.error_inject_i
);
endmodule : prim_secded_39_32_bind_fpv

31
vendor/lowrisc_ip/ip/prim/fpv/tb/prim_secded_39_32_fpv.sv vendored Normal file
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@ -0,0 +1,31 @@
// Copyright lowRISC contributors.
// Licensed under the Apache License, Version 2.0, see LICENSE for details.
// SPDX-License-Identifier: Apache-2.0
//
// SECDED FPV testbench generated by util/design/secded_gen.py
module prim_secded_39_32_fpv (
input clk_i,
input rst_ni,
input [31:0] in,
output logic [31:0] d_o,
output logic [6:0] syndrome_o,
output logic [1:0] err_o,
input [38:0] error_inject_i
);
logic [38:0] data_enc;
prim_secded_39_32_enc prim_secded_39_32_enc (
.in,
.out(data_enc)
);
prim_secded_39_32_dec prim_secded_39_32_dec (
.in(data_enc ^ error_inject_i),
.d_o,
.syndrome_o,
.err_o
);
endmodule : prim_secded_39_32_fpv

20
vendor/lowrisc_ip/ip/prim/fpv/tb/prim_secded_64_57_bind_fpv.sv vendored Normal file
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@ -0,0 +1,20 @@
// Copyright lowRISC contributors.
// Licensed under the Apache License, Version 2.0, see LICENSE for details.
// SPDX-License-Identifier: Apache-2.0
//
// SECDED FPV bind file generated by util/design/secded_gen.py
module prim_secded_64_57_bind_fpv;
bind prim_secded_64_57_fpv
prim_secded_64_57_assert_fpv prim_secded_64_57_assert_fpv (
.clk_i,
.rst_ni,
.in,
.d_o,
.syndrome_o,
.err_o,
.error_inject_i
);
endmodule : prim_secded_64_57_bind_fpv

31
vendor/lowrisc_ip/ip/prim/fpv/tb/prim_secded_64_57_fpv.sv vendored Normal file
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@ -0,0 +1,31 @@
// Copyright lowRISC contributors.
// Licensed under the Apache License, Version 2.0, see LICENSE for details.
// SPDX-License-Identifier: Apache-2.0
//
// SECDED FPV testbench generated by util/design/secded_gen.py
module prim_secded_64_57_fpv (
input clk_i,
input rst_ni,
input [56:0] in,
output logic [56:0] d_o,
output logic [6:0] syndrome_o,
output logic [1:0] err_o,
input [63:0] error_inject_i
);
logic [63:0] data_enc;
prim_secded_64_57_enc prim_secded_64_57_enc (
.in,
.out(data_enc)
);
prim_secded_64_57_dec prim_secded_64_57_dec (
.in(data_enc ^ error_inject_i),
.d_o,
.syndrome_o,
.err_o
);
endmodule : prim_secded_64_57_fpv

20
vendor/lowrisc_ip/ip/prim/fpv/tb/prim_secded_72_64_bind_fpv.sv vendored Normal file
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@ -0,0 +1,20 @@
// Copyright lowRISC contributors.
// Licensed under the Apache License, Version 2.0, see LICENSE for details.
// SPDX-License-Identifier: Apache-2.0
//
// SECDED FPV bind file generated by util/design/secded_gen.py
module prim_secded_72_64_bind_fpv;
bind prim_secded_72_64_fpv
prim_secded_72_64_assert_fpv prim_secded_72_64_assert_fpv (
.clk_i,
.rst_ni,
.in,
.d_o,
.syndrome_o,
.err_o,
.error_inject_i
);
endmodule : prim_secded_72_64_bind_fpv

31
vendor/lowrisc_ip/ip/prim/fpv/tb/prim_secded_72_64_fpv.sv vendored Normal file
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@ -0,0 +1,31 @@
// Copyright lowRISC contributors.
// Licensed under the Apache License, Version 2.0, see LICENSE for details.
// SPDX-License-Identifier: Apache-2.0
//
// SECDED FPV testbench generated by util/design/secded_gen.py
module prim_secded_72_64_fpv (
input clk_i,
input rst_ni,
input [63:0] in,
output logic [63:0] d_o,
output logic [7:0] syndrome_o,
output logic [1:0] err_o,
input [71:0] error_inject_i
);
logic [71:0] data_enc;
prim_secded_72_64_enc prim_secded_72_64_enc (
.in,
.out(data_enc)
);
prim_secded_72_64_dec prim_secded_72_64_dec (
.in(data_enc ^ error_inject_i),
.d_o,
.syndrome_o,
.err_o
);
endmodule : prim_secded_72_64_fpv

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@ -0,0 +1,20 @@
// Copyright lowRISC contributors.
// Licensed under the Apache License, Version 2.0, see LICENSE for details.
// SPDX-License-Identifier: Apache-2.0
//
// SECDED FPV bind file generated by util/design/secded_gen.py
module prim_secded_hamming_22_16_bind_fpv;
bind prim_secded_hamming_22_16_fpv
prim_secded_hamming_22_16_assert_fpv prim_secded_hamming_22_16_assert_fpv (
.clk_i,
.rst_ni,
.in,
.d_o,
.syndrome_o,
.err_o,
.error_inject_i
);
endmodule : prim_secded_hamming_22_16_bind_fpv

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@ -0,0 +1,31 @@
// Copyright lowRISC contributors.
// Licensed under the Apache License, Version 2.0, see LICENSE for details.
// SPDX-License-Identifier: Apache-2.0
//
// SECDED FPV testbench generated by util/design/secded_gen.py
module prim_secded_hamming_22_16_fpv (
input clk_i,
input rst_ni,
input [15:0] in,
output logic [15:0] d_o,
output logic [5:0] syndrome_o,
output logic [1:0] err_o,
input [21:0] error_inject_i
);
logic [21:0] data_enc;
prim_secded_hamming_22_16_enc prim_secded_hamming_22_16_enc (
.in,
.out(data_enc)
);
prim_secded_hamming_22_16_dec prim_secded_hamming_22_16_dec (
.in(data_enc ^ error_inject_i),
.d_o,
.syndrome_o,
.err_o
);
endmodule : prim_secded_hamming_22_16_fpv

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vendor/lowrisc_ip/ip/prim/fpv/tb/prim_secded_hamming_39_32_bind_fpv.sv vendored Normal file
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@ -0,0 +1,20 @@
// Copyright lowRISC contributors.
// Licensed under the Apache License, Version 2.0, see LICENSE for details.
// SPDX-License-Identifier: Apache-2.0
//
// SECDED FPV bind file generated by util/design/secded_gen.py
module prim_secded_hamming_39_32_bind_fpv;
bind prim_secded_hamming_39_32_fpv
prim_secded_hamming_39_32_assert_fpv prim_secded_hamming_39_32_assert_fpv (
.clk_i,
.rst_ni,
.in,
.d_o,
.syndrome_o,
.err_o,
.error_inject_i
);
endmodule : prim_secded_hamming_39_32_bind_fpv

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@ -0,0 +1,31 @@
// Copyright lowRISC contributors.
// Licensed under the Apache License, Version 2.0, see LICENSE for details.
// SPDX-License-Identifier: Apache-2.0
//
// SECDED FPV testbench generated by util/design/secded_gen.py
module prim_secded_hamming_39_32_fpv (
input clk_i,
input rst_ni,
input [31:0] in,
output logic [31:0] d_o,
output logic [6:0] syndrome_o,
output logic [1:0] err_o,
input [38:0] error_inject_i
);
logic [38:0] data_enc;
prim_secded_hamming_39_32_enc prim_secded_hamming_39_32_enc (
.in,
.out(data_enc)
);
prim_secded_hamming_39_32_dec prim_secded_hamming_39_32_dec (
.in(data_enc ^ error_inject_i),
.d_o,
.syndrome_o,
.err_o
);
endmodule : prim_secded_hamming_39_32_fpv

20
vendor/lowrisc_ip/ip/prim/fpv/tb/prim_secded_hamming_72_64_bind_fpv.sv vendored Normal file
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@ -0,0 +1,20 @@
// Copyright lowRISC contributors.
// Licensed under the Apache License, Version 2.0, see LICENSE for details.
// SPDX-License-Identifier: Apache-2.0
//
// SECDED FPV bind file generated by util/design/secded_gen.py
module prim_secded_hamming_72_64_bind_fpv;
bind prim_secded_hamming_72_64_fpv
prim_secded_hamming_72_64_assert_fpv prim_secded_hamming_72_64_assert_fpv (
.clk_i,
.rst_ni,
.in,
.d_o,
.syndrome_o,
.err_o,
.error_inject_i
);
endmodule : prim_secded_hamming_72_64_bind_fpv

31
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@ -0,0 +1,31 @@
// Copyright lowRISC contributors.
// Licensed under the Apache License, Version 2.0, see LICENSE for details.
// SPDX-License-Identifier: Apache-2.0
//
// SECDED FPV testbench generated by util/design/secded_gen.py
module prim_secded_hamming_72_64_fpv (
input clk_i,
input rst_ni,
input [63:0] in,
output logic [63:0] d_o,
output logic [7:0] syndrome_o,
output logic [1:0] err_o,
input [71:0] error_inject_i
);
logic [71:0] data_enc;
prim_secded_hamming_72_64_enc prim_secded_hamming_72_64_enc (
.in,
.out(data_enc)
);
prim_secded_hamming_72_64_dec prim_secded_hamming_72_64_dec (
.in(data_enc ^ error_inject_i),
.d_o,
.syndrome_o,
.err_o
);
endmodule : prim_secded_hamming_72_64_fpv

23
vendor/lowrisc_ip/ip/prim/fpv/vip/prim_alert_rxtx_assert_fpv.sv vendored
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@ -18,8 +18,10 @@ module prim_alert_rxtx_assert_fpv (
input alert_err_pi,
input alert_err_ni,
// normal I/Os
input alert_test_i,
input alert_req_i,
input alert_ack_o,
input alert_state_o,
input ping_req_i,
input ping_ok_o,
input integ_fail_o,
@ -58,7 +60,7 @@ module prim_alert_rxtx_assert_fpv (
(prim_alert_rxtx_fpv.i_prim_alert_sender.state_q ==
prim_alert_rxtx_fpv.i_prim_alert_sender.Idle) &&
(prim_alert_rxtx_fpv.i_prim_alert_receiver.state_q ==
prim_alert_rxtx_fpv.i_prim_alert_receiver.Idle)|=> FullHandshake_S,
prim_alert_rxtx_fpv.i_prim_alert_receiver.Idle) |=> FullHandshake_S,
clk_i, !rst_ni || error_present)
`ASSERT(AlertHs_A, alert_req_i &&
(prim_alert_rxtx_fpv.i_prim_alert_sender.state_q ==
@ -66,6 +68,19 @@ module prim_alert_rxtx_assert_fpv (
(prim_alert_rxtx_fpv.i_prim_alert_receiver.state_q ==
prim_alert_rxtx_fpv.i_prim_alert_receiver.Idle) |=>
FullHandshake_S |-> alert_ack_o, clk_i, !rst_ni || error_present)
`ASSERT(AlertTestHs_A, alert_test_i &&
(prim_alert_rxtx_fpv.i_prim_alert_sender.state_q ==
prim_alert_rxtx_fpv.i_prim_alert_sender.Idle) &&
(prim_alert_rxtx_fpv.i_prim_alert_receiver.state_q ==
prim_alert_rxtx_fpv.i_prim_alert_receiver.Idle) |=>
FullHandshake_S, clk_i, !rst_ni || error_present)
// Make sure we eventually get an ACK
`ASSERT(AlertReqAck_A, alert_req_i &&
(prim_alert_rxtx_fpv.i_prim_alert_sender.state_q ==
prim_alert_rxtx_fpv.i_prim_alert_sender.Idle) &&
(prim_alert_rxtx_fpv.i_prim_alert_receiver.state_q ==
prim_alert_rxtx_fpv.i_prim_alert_receiver.Idle) |-> strong(##[1:$] alert_ack_o),
clk_i, !rst_ni || error_present)
// transmission of pings
// note: the complete transmission of pings only happen when no ping handshake is in progress
@ -78,15 +93,15 @@ module prim_alert_rxtx_assert_fpv (
prim_alert_rxtx_fpv.i_prim_alert_sender.PingHsPhase2}) && $rose(ping_req_i) |->
ping_ok_o == 0 throughout ping_req_i [->1], clk_i, !rst_ni || error_present)
// transmission of alerts in case of no collision with ping enable
`ASSERT(AlertCheck0_A, !ping_req_i [*3] ##0 $rose(alert_req_i) &&
`ASSERT(AlertCheck0_A, !ping_req_i [*3] ##0 ($rose(alert_req_i) || $rose(alert_test_i)) &&
(prim_alert_rxtx_fpv.i_prim_alert_sender.state_q ==
prim_alert_rxtx_fpv.i_prim_alert_sender.Idle) |=>
alert_o, clk_i, !rst_ni || error_present || ping_req_i)
// transmission of alerts in the general case which can include continous ping collisions
`ASSERT(AlertCheck1_A, alert_req_i |=>
`ASSERT(AlertCheck1_A, alert_req_i || alert_test_i |=>
strong(##[1:$] ((prim_alert_rxtx_fpv.i_prim_alert_sender.state_q ==
prim_alert_rxtx_fpv.i_prim_alert_sender.Idle) && !ping_req_i) ##1 alert_o),
clk_i, !rst_ni || error_present || alert_ack_o)
clk_i, !rst_ni || error_present || prim_alert_rxtx_fpv.i_prim_alert_sender.alert_clr)
// basic liveness of FSMs in case no errors are present
`ASSERT(FsmLivenessSender_A,

27
vendor/lowrisc_ip/ip/prim/fpv/vip/prim_alert_rxtx_async_assert_fpv.sv vendored
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@ -21,8 +21,10 @@ module prim_alert_rxtx_async_assert_fpv (
input alert_err_ni,
input [1:0] alert_skew_i,
// normal I/Os
input alert_test_i,
input alert_req_i,
input alert_ack_o,
input alert_state_o,
input ping_req_i,
input ping_ok_o,
input integ_fail_o,
@ -87,8 +89,20 @@ module prim_alert_rxtx_async_assert_fpv (
(prim_alert_rxtx_async_fpv.i_prim_alert_sender.state_q ==
prim_alert_rxtx_async_fpv.i_prim_alert_sender.Idle) &&
(prim_alert_rxtx_async_fpv.i_prim_alert_receiver.state_q ==
prim_alert_rxtx_async_fpv.i_prim_alert_receiver.Idle) |-> ##[0:5] FullHandshake_S
##[0:5] alert_ack_o,
prim_alert_rxtx_async_fpv.i_prim_alert_receiver.Idle) |-> ##[0:5] FullHandshake_S,
clk_i, !rst_ni || error_setreg_q)
`ASSERT(AlertTestHs_A, alert_test_i &&
(prim_alert_rxtx_async_fpv.i_prim_alert_sender.state_q ==
prim_alert_rxtx_async_fpv.i_prim_alert_sender.Idle) &&
(prim_alert_rxtx_async_fpv.i_prim_alert_receiver.state_q ==
prim_alert_rxtx_async_fpv.i_prim_alert_receiver.Idle) |-> ##[0:5] FullHandshake_S,
clk_i, !rst_ni || error_setreg_q)
// Make sure we eventually get an ACK
`ASSERT(AlertReqAck_A, alert_req_i &&
(prim_alert_rxtx_async_fpv.i_prim_alert_sender.state_q ==
prim_alert_rxtx_async_fpv.i_prim_alert_sender.Idle) &&
(prim_alert_rxtx_async_fpv.i_prim_alert_receiver.state_q ==
prim_alert_rxtx_async_fpv.i_prim_alert_receiver.Idle) |-> strong(##[1:$] alert_ack_o),
clk_i, !rst_ni || error_setreg_q)
// transmission of pings
@ -104,16 +118,17 @@ module prim_alert_rxtx_async_assert_fpv (
prim_alert_rxtx_async_fpv.i_prim_alert_sender.PingHsPhase2}) && $rose(ping_req_i) |->
ping_ok_o == 0 throughout ping_req_i[->1], clk_i, !rst_ni || error_setreg_q)
// transmission of first alert assertion (no ping collision)
`ASSERT(AlertCheck0_A, !ping_req_i [*10] ##1 $rose(alert_req_i) &&
`ASSERT(AlertCheck0_A, !ping_req_i [*10] ##1 ($rose(alert_req_i) || $rose(alert_test_i)) &&
(prim_alert_rxtx_async_fpv.i_prim_alert_sender.state_q ==
prim_alert_rxtx_async_fpv.i_prim_alert_sender.Idle) |->
##[3:5] alert_o, clk_i, !rst_ni || ping_req_i || error_setreg_q)
// eventual transmission of alerts in the general case which can include continous ping
// collisions
`ASSERT(AlertCheck1_A, alert_req_i |->
`ASSERT(AlertCheck1_A, alert_req_i || alert_test_i |->
strong(##[1:$] (prim_alert_rxtx_async_fpv.i_prim_alert_sender.state_q ==
prim_alert_rxtx_async_fpv.i_prim_alert_sender.Idle && !ping_req_i) ##[3:5] alert_o),
clk_i, !rst_ni || error_setreg_q || alert_ack_o)
clk_i, !rst_ni || error_setreg_q ||
prim_alert_rxtx_async_fpv.i_prim_alert_sender.alert_clr)
// basic liveness of FSMs in case no errors are present
`ASSERT(FsmLivenessSender_A, !error_present [*2] ##1 !error_present &&
@ -127,6 +142,4 @@ module prim_alert_rxtx_async_assert_fpv (
strong(##[1:$] (prim_alert_rxtx_async_fpv.i_prim_alert_receiver.state_q ==
prim_alert_rxtx_async_fpv.i_prim_alert_receiver.Idle)),clk_i, !rst_ni || error_present)
// TODO: add FSM liveness of 3x diff decoder instances
endmodule : prim_alert_rxtx_async_assert_fpv

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vendor/lowrisc_ip/ip/prim/fpv/vip/prim_secded_22_16_assert_fpv.sv vendored Normal file
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@ -0,0 +1,33 @@
// Copyright lowRISC contributors.
// Licensed under the Apache License, Version 2.0, see LICENSE for details.
// SPDX-License-Identifier: Apache-2.0
//
// SECDED FPV assertion file generated by util/design/secded_gen.py
module prim_secded_22_16_assert_fpv (
input clk_i,
input rst_ni,
input [15:0] in,
input [15:0] d_o,
input [5:0] syndrome_o,
input [1:0] err_o,
input [21:0] error_inject_i
);
// Inject a maximum of two errors simultaneously.
`ASSUME_FPV(MaxTwoErrors_M, $countones(error_inject_i) <= 2)
// This bounds the input data state space to make sure the solver converges.
`ASSUME_FPV(DataLimit_M, $onehot0(in) || $onehot0(~in))
// Single bit error detection
`ASSERT(SingleErrorDetect_A, $countones(error_inject_i) == 1 |-> err_o[0])
`ASSERT(SingleErrorDetectReverse_A, err_o[0] |-> $countones(error_inject_i) == 1)
// Double bit error detection
`ASSERT(DoubleErrorDetect_A, $countones(error_inject_i) == 2 |-> err_o[1])
`ASSERT(DoubleErrorDetectReverse_A, err_o[1] |-> $countones(error_inject_i) == 2)
// Single bit error correction (implicitly tests the syndrome output)
`ASSERT(SingleErrorCorrect_A, $countones(error_inject_i) < 2 |-> in == d_o)
// Basic syndrome check
`ASSERT(SyndromeCheck_A, |syndrome_o |-> $countones(error_inject_i) > 0)
`ASSERT(SyndromeCheckReverse_A, $countones(error_inject_i) > 0 |-> |syndrome_o)
endmodule : prim_secded_22_16_assert_fpv

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@ -0,0 +1,33 @@
// Copyright lowRISC contributors.
// Licensed under the Apache License, Version 2.0, see LICENSE for details.
// SPDX-License-Identifier: Apache-2.0
//
// SECDED FPV assertion file generated by util/design/secded_gen.py
module prim_secded_28_22_assert_fpv (
input clk_i,
input rst_ni,
input [21:0] in,
input [21:0] d_o,
input [5:0] syndrome_o,
input [1:0] err_o,
input [27:0] error_inject_i
);
// Inject a maximum of two errors simultaneously.
`ASSUME_FPV(MaxTwoErrors_M, $countones(error_inject_i) <= 2)
// This bounds the input data state space to make sure the solver converges.
`ASSUME_FPV(DataLimit_M, $onehot0(in) || $onehot0(~in))
// Single bit error detection
`ASSERT(SingleErrorDetect_A, $countones(error_inject_i) == 1 |-> err_o[0])
`ASSERT(SingleErrorDetectReverse_A, err_o[0] |-> $countones(error_inject_i) == 1)
// Double bit error detection
`ASSERT(DoubleErrorDetect_A, $countones(error_inject_i) == 2 |-> err_o[1])
`ASSERT(DoubleErrorDetectReverse_A, err_o[1] |-> $countones(error_inject_i) == 2)
// Single bit error correction (implicitly tests the syndrome output)
`ASSERT(SingleErrorCorrect_A, $countones(error_inject_i) < 2 |-> in == d_o)
// Basic syndrome check
`ASSERT(SyndromeCheck_A, |syndrome_o |-> $countones(error_inject_i) > 0)
`ASSERT(SyndromeCheckReverse_A, $countones(error_inject_i) > 0 |-> |syndrome_o)
endmodule : prim_secded_28_22_assert_fpv

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@ -0,0 +1,33 @@
// Copyright lowRISC contributors.
// Licensed under the Apache License, Version 2.0, see LICENSE for details.
// SPDX-License-Identifier: Apache-2.0
//
// SECDED FPV assertion file generated by util/design/secded_gen.py
module prim_secded_39_32_assert_fpv (
input clk_i,
input rst_ni,
input [31:0] in,
input [31:0] d_o,
input [6:0] syndrome_o,
input [1:0] err_o,
input [38:0] error_inject_i
);
// Inject a maximum of two errors simultaneously.
`ASSUME_FPV(MaxTwoErrors_M, $countones(error_inject_i) <= 2)
// This bounds the input data state space to make sure the solver converges.
`ASSUME_FPV(DataLimit_M, $onehot0(in) || $onehot0(~in))
// Single bit error detection
`ASSERT(SingleErrorDetect_A, $countones(error_inject_i) == 1 |-> err_o[0])
`ASSERT(SingleErrorDetectReverse_A, err_o[0] |-> $countones(error_inject_i) == 1)
// Double bit error detection
`ASSERT(DoubleErrorDetect_A, $countones(error_inject_i) == 2 |-> err_o[1])
`ASSERT(DoubleErrorDetectReverse_A, err_o[1] |-> $countones(error_inject_i) == 2)
// Single bit error correction (implicitly tests the syndrome output)
`ASSERT(SingleErrorCorrect_A, $countones(error_inject_i) < 2 |-> in == d_o)
// Basic syndrome check
`ASSERT(SyndromeCheck_A, |syndrome_o |-> $countones(error_inject_i) > 0)
`ASSERT(SyndromeCheckReverse_A, $countones(error_inject_i) > 0 |-> |syndrome_o)
endmodule : prim_secded_39_32_assert_fpv

33
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@ -0,0 +1,33 @@
// Copyright lowRISC contributors.
// Licensed under the Apache License, Version 2.0, see LICENSE for details.
// SPDX-License-Identifier: Apache-2.0
//
// SECDED FPV assertion file generated by util/design/secded_gen.py
module prim_secded_64_57_assert_fpv (
input clk_i,
input rst_ni,
input [56:0] in,
input [56:0] d_o,
input [6:0] syndrome_o,
input [1:0] err_o,
input [63:0] error_inject_i
);
// Inject a maximum of two errors simultaneously.
`ASSUME_FPV(MaxTwoErrors_M, $countones(error_inject_i) <= 2)
// This bounds the input data state space to make sure the solver converges.
`ASSUME_FPV(DataLimit_M, $onehot0(in) || $onehot0(~in))
// Single bit error detection
`ASSERT(SingleErrorDetect_A, $countones(error_inject_i) == 1 |-> err_o[0])
`ASSERT(SingleErrorDetectReverse_A, err_o[0] |-> $countones(error_inject_i) == 1)
// Double bit error detection
`ASSERT(DoubleErrorDetect_A, $countones(error_inject_i) == 2 |-> err_o[1])
`ASSERT(DoubleErrorDetectReverse_A, err_o[1] |-> $countones(error_inject_i) == 2)
// Single bit error correction (implicitly tests the syndrome output)
`ASSERT(SingleErrorCorrect_A, $countones(error_inject_i) < 2 |-> in == d_o)
// Basic syndrome check
`ASSERT(SyndromeCheck_A, |syndrome_o |-> $countones(error_inject_i) > 0)
`ASSERT(SyndromeCheckReverse_A, $countones(error_inject_i) > 0 |-> |syndrome_o)
endmodule : prim_secded_64_57_assert_fpv

33
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@ -0,0 +1,33 @@
// Copyright lowRISC contributors.
// Licensed under the Apache License, Version 2.0, see LICENSE for details.
// SPDX-License-Identifier: Apache-2.0
//
// SECDED FPV assertion file generated by util/design/secded_gen.py
module prim_secded_72_64_assert_fpv (
input clk_i,
input rst_ni,
input [63:0] in,
input [63:0] d_o,
input [7:0] syndrome_o,
input [1:0] err_o,
input [71:0] error_inject_i
);
// Inject a maximum of two errors simultaneously.
`ASSUME_FPV(MaxTwoErrors_M, $countones(error_inject_i) <= 2)
// This bounds the input data state space to make sure the solver converges.
`ASSUME_FPV(DataLimit_M, $onehot0(in) || $onehot0(~in))
// Single bit error detection
`ASSERT(SingleErrorDetect_A, $countones(error_inject_i) == 1 |-> err_o[0])
`ASSERT(SingleErrorDetectReverse_A, err_o[0] |-> $countones(error_inject_i) == 1)
// Double bit error detection
`ASSERT(DoubleErrorDetect_A, $countones(error_inject_i) == 2 |-> err_o[1])
`ASSERT(DoubleErrorDetectReverse_A, err_o[1] |-> $countones(error_inject_i) == 2)
// Single bit error correction (implicitly tests the syndrome output)
`ASSERT(SingleErrorCorrect_A, $countones(error_inject_i) < 2 |-> in == d_o)
// Basic syndrome check
`ASSERT(SyndromeCheck_A, |syndrome_o |-> $countones(error_inject_i) > 0)
`ASSERT(SyndromeCheckReverse_A, $countones(error_inject_i) > 0 |-> |syndrome_o)
endmodule : prim_secded_72_64_assert_fpv

33
vendor/lowrisc_ip/ip/prim/fpv/vip/prim_secded_hamming_22_16_assert_fpv.sv vendored Normal file
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@ -0,0 +1,33 @@
// Copyright lowRISC contributors.
// Licensed under the Apache License, Version 2.0, see LICENSE for details.
// SPDX-License-Identifier: Apache-2.0
//
// SECDED FPV assertion file generated by util/design/secded_gen.py
module prim_secded_hamming_22_16_assert_fpv (
input clk_i,
input rst_ni,
input [15:0] in,
input [15:0] d_o,
input [5:0] syndrome_o,
input [1:0] err_o,
input [21:0] error_inject_i
);
// Inject a maximum of two errors simultaneously.
`ASSUME_FPV(MaxTwoErrors_M, $countones(error_inject_i) <= 2)
// This bounds the input data state space to make sure the solver converges.
`ASSUME_FPV(DataLimit_M, $onehot0(in) || $onehot0(~in))
// Single bit error detection
`ASSERT(SingleErrorDetect_A, $countones(error_inject_i) == 1 |-> err_o[0])
`ASSERT(SingleErrorDetectReverse_A, err_o[0] |-> $countones(error_inject_i) == 1)
// Double bit error detection
`ASSERT(DoubleErrorDetect_A, $countones(error_inject_i) == 2 |-> err_o[1])
`ASSERT(DoubleErrorDetectReverse_A, err_o[1] |-> $countones(error_inject_i) == 2)
// Single bit error correction (implicitly tests the syndrome output)
`ASSERT(SingleErrorCorrect_A, $countones(error_inject_i) < 2 |-> in == d_o)
// Basic syndrome check
`ASSERT(SyndromeCheck_A, |syndrome_o |-> $countones(error_inject_i) > 0)
`ASSERT(SyndromeCheckReverse_A, $countones(error_inject_i) > 0 |-> |syndrome_o)
endmodule : prim_secded_hamming_22_16_assert_fpv

33
vendor/lowrisc_ip/ip/prim/fpv/vip/prim_secded_hamming_39_32_assert_fpv.sv vendored Normal file
View file

@ -0,0 +1,33 @@
// Copyright lowRISC contributors.
// Licensed under the Apache License, Version 2.0, see LICENSE for details.
// SPDX-License-Identifier: Apache-2.0
//
// SECDED FPV assertion file generated by util/design/secded_gen.py
module prim_secded_hamming_39_32_assert_fpv (
input clk_i,
input rst_ni,
input [31:0] in,
input [31:0] d_o,
input [6:0] syndrome_o,
input [1:0] err_o,
input [38:0] error_inject_i
);
// Inject a maximum of two errors simultaneously.
`ASSUME_FPV(MaxTwoErrors_M, $countones(error_inject_i) <= 2)
// This bounds the input data state space to make sure the solver converges.
`ASSUME_FPV(DataLimit_M, $onehot0(in) || $onehot0(~in))
// Single bit error detection
`ASSERT(SingleErrorDetect_A, $countones(error_inject_i) == 1 |-> err_o[0])
`ASSERT(SingleErrorDetectReverse_A, err_o[0] |-> $countones(error_inject_i) == 1)
// Double bit error detection
`ASSERT(DoubleErrorDetect_A, $countones(error_inject_i) == 2 |-> err_o[1])
`ASSERT(DoubleErrorDetectReverse_A, err_o[1] |-> $countones(error_inject_i) == 2)
// Single bit error correction (implicitly tests the syndrome output)
`ASSERT(SingleErrorCorrect_A, $countones(error_inject_i) < 2 |-> in == d_o)
// Basic syndrome check
`ASSERT(SyndromeCheck_A, |syndrome_o |-> $countones(error_inject_i) > 0)
`ASSERT(SyndromeCheckReverse_A, $countones(error_inject_i) > 0 |-> |syndrome_o)
endmodule : prim_secded_hamming_39_32_assert_fpv

33
vendor/lowrisc_ip/ip/prim/fpv/vip/prim_secded_hamming_72_64_assert_fpv.sv vendored Normal file
View file

@ -0,0 +1,33 @@
// Copyright lowRISC contributors.
// Licensed under the Apache License, Version 2.0, see LICENSE for details.
// SPDX-License-Identifier: Apache-2.0
//
// SECDED FPV assertion file generated by util/design/secded_gen.py
module prim_secded_hamming_72_64_assert_fpv (
input clk_i,
input rst_ni,
input [63:0] in,
input [63:0] d_o,
input [7:0] syndrome_o,
input [1:0] err_o,
input [71:0] error_inject_i
);
// Inject a maximum of two errors simultaneously.
`ASSUME_FPV(MaxTwoErrors_M, $countones(error_inject_i) <= 2)
// This bounds the input data state space to make sure the solver converges.
`ASSUME_FPV(DataLimit_M, $onehot0(in) || $onehot0(~in))
// Single bit error detection
`ASSERT(SingleErrorDetect_A, $countones(error_inject_i) == 1 |-> err_o[0])
`ASSERT(SingleErrorDetectReverse_A, err_o[0] |-> $countones(error_inject_i) == 1)
// Double bit error detection
`ASSERT(DoubleErrorDetect_A, $countones(error_inject_i) == 2 |-> err_o[1])
`ASSERT(DoubleErrorDetectReverse_A, err_o[1] |-> $countones(error_inject_i) == 2)
// Single bit error correction (implicitly tests the syndrome output)
`ASSERT(SingleErrorCorrect_A, $countones(error_inject_i) < 2 |-> in == d_o)
// Basic syndrome check
`ASSERT(SyndromeCheck_A, |syndrome_o |-> $countones(error_inject_i) > 0)
`ASSERT(SyndromeCheckReverse_A, $countones(error_inject_i) > 0 |-> |syndrome_o)
endmodule : prim_secded_hamming_72_64_assert_fpv

4
vendor/lowrisc_ip/ip/prim/lint/prim.vlt vendored
View file

@ -12,3 +12,7 @@ lint_off -rule UNUSED -file "*/rtl/prim_subreg.sv" -match "Signal is not used: '
// In passthrough mode, clk and reset are not read form within this module
lint_off -rule UNUSED -file "*/rtl/prim_fifo_sync.sv" -match "*clk_i*"
lint_off -rule UNUSED -file "*/rtl/prim_fifo_sync.sv" -match "*rst_ni*"
// prim_lfsr
// lfsr_perm_test is just used for an SVA
lint_off -rule UNUSED -file "*/rtl/prim_lfsr.sv" -match "*lfsr_perm_test*"

3
vendor/lowrisc_ip/ip/prim/lint/prim_clock_div.waiver vendored
View file

@ -6,3 +6,6 @@
waive -rules DUAL_EDGE_CLOCK -location {prim_clock_div.sv} -regexp {.*} \
-comment "The clock switch signal is synchronized on negative edge to ensure it is away from any transition"
waive -rules CLOCK_MUX -location {prim_clock_div.sv} -regexp {.*reaches a multiplexer here, used as a clock.*} \
-comment "A mux is used during scan bypass, and for switching between div by 2 and div by 1 clocks"

2
vendor/lowrisc_ip/ip/prim/prim.core vendored
View file

@ -35,6 +35,7 @@ filesets:
- rtl/prim_slicer.sv
- rtl/prim_sync_reqack.sv
- rtl/prim_sync_reqack_data.sv
- rtl/prim_sync_slow_fast.sv
- rtl/prim_keccak.sv
- rtl/prim_packer.sv
- rtl/prim_packer_fifo.sv
@ -73,7 +74,6 @@ filesets:
depend:
# common waivers
- lowrisc:lint:common
- lowrisc:lint:comportable
targets:
default:

1
vendor/lowrisc_ip/ip/prim/prim_buf.core vendored
View file

@ -31,7 +31,6 @@ filesets:
depend:
# common waivers
- lowrisc:lint:common
- lowrisc:lint:comportable
generate:
impl:

1
vendor/lowrisc_ip/ip/prim/prim_clock_buf.core vendored
View file

@ -31,7 +31,6 @@ filesets:
depend:
# common waivers
- lowrisc:lint:common
- lowrisc:lint:comportable
generate:
impl:

1
vendor/lowrisc_ip/ip/prim/prim_clock_gating.core vendored
View file

@ -31,7 +31,6 @@ filesets:
depend:
# common waivers
- lowrisc:lint:common
- lowrisc:lint:comportable
generate:
impl:

1
vendor/lowrisc_ip/ip/prim/prim_clock_inv.core vendored
View file

@ -31,7 +31,6 @@ filesets:
depend:
# common waivers
- lowrisc:lint:common
- lowrisc:lint:comportable
generate:
impl:

1
vendor/lowrisc_ip/ip/prim/prim_clock_mux2.core vendored
View file

@ -31,7 +31,6 @@ filesets:
depend:
# common waivers
- lowrisc:lint:common
- lowrisc:lint:comportable
generate:
impl:

1
vendor/lowrisc_ip/ip/prim/prim_dom_and_2share.core vendored
View file

@ -33,7 +33,6 @@ filesets:
depend:
# common waivers
- lowrisc:lint:common
- lowrisc:lint:comportable
targets:

3
vendor/lowrisc_ip/ip/prim/prim_flash.core vendored
View file

@ -13,6 +13,8 @@ filesets:
# TODO olofk/fusesoc#404: The below dependency is already added to prim_generic_flash.core.
# However, the generator for the prim:ram1p does not kick in, causing compile errors.
- lowrisc:prim:ram_1p
- lowrisc:prim:clock_inv
- lowrisc:prim:clock_gating
files_verilator_waiver:
@ -34,7 +36,6 @@ filesets:
depend:
# common waivers
- lowrisc:lint:common
- lowrisc:lint:comportable
generate:
impl:

1
vendor/lowrisc_ip/ip/prim/prim_flop.core vendored
View file

@ -30,7 +30,6 @@ filesets:
depend:
# common waivers
- lowrisc:lint:common
- lowrisc:lint:comportable
generate:
impl:

1
vendor/lowrisc_ip/ip/prim/prim_flop_2sync.core vendored
View file

@ -30,7 +30,6 @@ filesets:
depend:
# common waivers
- lowrisc:lint:common
- lowrisc:lint:comportable
generate:

54
vendor/lowrisc_ip/ip/prim/prim_lc_dec.core vendored Normal file
View file

@ -0,0 +1,54 @@
CAPI=2:
# Copyright lowRISC contributors.
# Licensed under the Apache License, Version 2.0, see LICENSE for details.
# SPDX-License-Identifier: Apache-2.0
name: "lowrisc:prim:lc_dec:0.1"
description: "Decoder for life cycle control signals."
filesets:
files_rtl:
depend:
- lowrisc:prim:buf
- lowrisc:ip:lc_ctrl_pkg
files:
- rtl/prim_lc_dec.sv
file_type: systemVerilogSource
files_verilator_waiver:
depend:
# common waivers
- lowrisc:lint:common
files:
file_type: vlt
files_ascentlint_waiver:
depend:
# common waivers
- lowrisc:lint:common
files:
# - lint/prim_lc_sync.waiver
file_type: waiver
files_veriblelint_waiver:
depend:
# common waivers
- lowrisc:lint:common
targets:
default: &default_target
filesets:
- tool_verilator ? (files_verilator_waiver)
- tool_ascentlint ? (files_ascentlint_waiver)
- tool_veriblelint ? (files_veriblelint_waiver)
- files_rtl
lint:
<<: *default_target
default_tool: verilator
parameters:
- SYNTHESIS=true
tools:
verilator:
mode: lint-only
verilator_options:
- "-Wall"

1
vendor/lowrisc_ip/ip/prim/prim_lc_sender.core vendored
View file

@ -34,7 +34,6 @@ filesets:
depend:
# common waivers
- lowrisc:lint:common
- lowrisc:lint:comportable
targets:
default: &default_target

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