Fix some typos

alu.sv

@@ -198,7 +198,7 @@ module riscv_alu
   logic [31:0] shift_right_result;
   logic [31:0] shift_left_result;
 
-  // shifter is also used for preparing operand for divison
+  // shifter is also used for preparing operand for division
   assign shift_amt = div_valid ? div_shift : operand_b_i;
 
   // by reversing the bits of the input, we also have to reverse the order of shift amounts

docs/datasheet/preamble/preamble.tex

@@ -71,7 +71,7 @@
 % Create an inline command for shell commands.
 \newcommand{\shell}[1]{\texttt{#1}}
 
-% Create an enviroment for a shell commands.
+% Create an environment for a shell commands.
 \newenvironment{shellenv}%
 {\VerbatimEnvironment%
  \begin{Sbox}\begin{minipage}{0.97\textwidth}\begin{Verbatim}%

ex_stage.sv

@@ -16,7 +16,7 @@
 //                 Sven Stucki - svstucki@student.ethz.ch                     //
 //                 Andreas Traber - atraber@iis.ee.ethz.ch                    //
 //                                                                            //
-// Design Name:    Excecute stage                                             //
+// Design Name:    Execute stage                                             //
 // Project Name:   RI5CY                                                      //
 // Language:       SystemVerilog                                              //
 //                                                                            //

id_stage.sv

@@ -409,7 +409,7 @@ module riscv_id_stage
   //---------------------------------------------------------------------------
   assign regfile_waddr_id = instr[`REG_D];
 
-  // Second Register Write Adress Selection
+  // Second Register Write Address Selection
   // Used for prepost load/store and multiplier
   assign regfile_alu_waddr_id = regfile_alu_waddr_mux_sel ?
                                 regfile_waddr_id : regfile_addr_ra_id;

tb/serDiv/tb.sv

@@ -28,7 +28,7 @@ module tb;
   time C_CLK_HI               = 5ns;     // set clock high time
   time C_CLK_LO               = 5ns;     // set clock low time
   time C_APPL_DEL             = 2ns;     // set stimuli application delay
-  time C_ACQ_DEL              = 8ns;     // set response aquisition delay
+  time C_ACQ_DEL              = 8ns;     // set response acquisition delay
 
   parameter C_WIDTH           = 32;
   parameter C_LOG_WIDTH       = 6;