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[dv] Fix typos

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Elliot Baptist 2025-06-26 11:56:11 +01:00 • committed by Elliot Baptist
parent 41c2fd8d90
commit 6b88138a90
30 changed files with 52 additions and 52 deletions
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12
dv/cosim/spike_cosim.cc
View file

@ -166,7 +166,7 @@ bool SpikeCosim::backdoor_read_mem(uint32_t addr, size_t len,
// The state.last_inst_pc also remains with the sentinel value PC_INVALID.
// - If we catch a trap_t&, then the take_trap() fn updates the state of the
// processor, and when we call step() again we start executing in the new
// context of the trap (trap andler, new MSTATUS, debug rom, etc. etc.)
// context of the trap (trap handler, new MSTATUS, debug rom, etc. etc.)
bool SpikeCosim::step(uint32_t write_reg, uint32_t write_reg_data, uint32_t pc,
bool sync_trap, bool suppress_reg_write) {
assert(write_reg < 32);
@ -196,7 +196,7 @@ bool SpikeCosim::step(uint32_t write_reg, uint32_t write_reg_data, uint32_t pc,
// we do the stop, so we can restore it after the step (as spike won't
// suppressed the register write).
//
// First check retired instruciton to ensure load suppression is correct
// First check retired instruction to ensure load suppression is correct
if (!check_suppress_reg_write(write_reg, pc, suppressed_write_reg)) {
return false;
}
@ -228,7 +228,7 @@ bool SpikeCosim::step(uint32_t write_reg, uint32_t write_reg_data, uint32_t pc,
// - PC_INVALID == true
// - current state is that of the trapping instruction
// DUT
// - If the dut encounters an async trap (which can be thought of as occuring
// - If the dut encounters an async trap (which can be thought of as occurring
// between instructions), an rvfi_item will be generated for the the first
// retired instruction of the trap handler.
// - If the dut encounters a sync trap, an rvfi_item will be generated for the
@ -626,7 +626,7 @@ void SpikeCosim::early_interrupt_handle() {
// Ibex splits misaligned accesses into two separate requests. They
// independently undergo PMP access checks. It is possible for one to fail (so
// no request produced for that half of the access) whilst the other successed
// no request produced for that half of the access) whilst the other succeeds
// (producing a request for that half of the access).
//
// Spike splits misaligned accesses up into bytes and will apply PMP access
@ -1022,7 +1022,7 @@ SpikeCosim::check_mem_result_e SpikeCosim::check_mem_access(
}
// For any misaligned access that sees an error immediately indicate to
// spike the error has occured, so ensure the top pending access gets
// spike the error has occurred, so ensure the top pending access gets
// removed.
pending_access_done = true;
}
@ -1048,7 +1048,7 @@ bool SpikeCosim::pc_is_debug_ebreak(uint32_t pc) {
uint32_t dcsr = processor->get_csr(CSR_DCSR);
// ebreak debug entry is controlled by the ebreakm (bit 15) and ebreaku (bit
// 12) fields of DCSR. If the appropriate bit of the current privlege level
// 12) fields of DCSR. If the appropriate bit of the current privilege level
// isn't set ebreak won't enter debug so return false.
if ((processor->get_state()->prv == PRV_M) && ((dcsr & 0x1000) == 0) ||
(processor->get_state()->prv == PRV_U) && ((dcsr & 0x8000) == 0)) {

2
dv/cosim/spike_cosim.h
View file

@ -62,7 +62,7 @@ class SpikeCosim : public simif_t, public Cosim {
uint32_t pending_iside_err_addr;
typedef enum {
kCheckMemOk, // Checks passed and access succeded in RTL
kCheckMemOk, // Checks passed and access succeeded in RTL
kCheckMemCheckFailed, // Checks failed
kCheckMemBusError // Checks passed, but access generated bus error in RTL
} check_mem_result_e;

2
dv/cs_registers/model/base_register.cc
View file

@ -65,7 +65,7 @@ bool BaseRegister::ProcessTransaction(bool *match, RegisterTransaction *trans) {
// else if (read_val != trans->csr_rdata) {
// std::cout << "MCycle(H) incrementing as expected" << std::endl;
//}
// Don't panic about MCycle(H) incremeting, this is expected behavior as
// Don't panic about MCycle(H) incrementing, this is expected behavior as
// the clock is always running. Silently ignore mismatches for MCycle(H).
} else if (read_val != trans->csr_rdata) {
std::cout << "Error, transaction:" << std::endl;

4
dv/formal/check/top.sv
View file

@ -80,7 +80,7 @@ module top import ibex_pkg::*; #(
input logic irq_timer_i,
input logic irq_external_i,
input logic [14:0] irq_fast_i,
input logic irq_nm_i, // non-maskeable interrupt
input logic irq_nm_i, // non-maskable interrupt
// Scrambling Interface
input logic scramble_key_valid_i,
@ -435,7 +435,7 @@ assign ex_is_checkable_csr = ~(
`undef INSTR
`define INSTR wbexc_decompressed_instr
// Illegal instructions arent checkable unless the relevant specifications are present.
// Illegal instructions aren't checkable unless the relevant specifications are present.
logic can_check_illegal;
assign can_check_illegal = `SPEC_ILLEGAL & `SPEC_CSR & `SPEC_MRET & `SPEC_WFI;

4
dv/formal/spec/main.sail
View file

@ -13,7 +13,7 @@ main is equivalent to the Sail step function, it has some differences however:
1. It's difficult to compare IRQ handling, since ibex takes them later than the Sail would. This is OK since it's not really
fair to enforce that IRQs are handled between any two specific instructions, so long as it is eventually.
2. The three modes are a useful case analysis we can make. This means that to prove correctness of an I-Type instruction, for example, we
can more easily seperate out the check for instruction fetch correctness, which makes things faster and avoids repeated work.
can more easily separate out the check for instruction fetch correctness, which makes things faster and avoids repeated work.
*/
union FetchResult = {
@ -48,7 +48,7 @@ function main(insn_bits, mode) : (bits(32), MainMode) -> MainResult = {
let irq = dispatchInterrupt(cur_privilege);
let f : FetchResult = altFetch(insn_bits[15..0], insn_bits[31..16]);
let res : MainResult = match mode {
MAIN_IDEX => {
match decompress(insn) {

2
dv/formal/spec/spec_api.sv
View file

@ -5,7 +5,7 @@
// SPDX-License-Identifier: Apache-2.0
/*
This module contains the actual instance of the specification. It's quite ugly. Mostly it's just forwaring things to
This module contains the actual instance of the specification. It's quite ugly. Mostly it's just forwarding things to
different names and ignoring registers we don't care about.
*/

2
dv/uvm/core_ibex/common/ibex_cosim_agent/ibex_cosim_scoreboard.sv
View file

@ -347,7 +347,7 @@ class ibex_cosim_scoreboard extends uvm_scoreboard;
endfunction : final_phase
// If the UVM_EXIT action is triggered (such as by reaching max_quit_count), this callback is run.
// This ensures proper cleanup, such as commiting the logfile to disk.
// This ensures proper cleanup, such as committing the logfile to disk.
function void pre_abort();
cleanup_cosim();
endfunction

2
dv/uvm/core_ibex/common/ibex_mem_intf_agent/ibex_mem_intf_response_seq_lib.sv
View file

@ -178,7 +178,7 @@ class ibex_mem_intf_response_seq extends uvm_sequence #(ibex_mem_intf_seq_item);
endfunction
// Read a word of DATA_WIDTH bits from addr.
// Handle reads fromm uninit memory as follows:
// Handle reads from uninit memory as follows:
// - DMEM : return a random value
// - IMEM : return {2{C.unimp}}
protected function logic [DATA_WIDTH-1:0] read(bit [ADDR_WIDTH-1:0] addr,

2
dv/uvm/core_ibex/common/irq_agent/irq_if.sv
View file

@ -8,7 +8,7 @@ interface irq_if(input clk);
logic irq_timer;
logic irq_external;
logic [14:0] irq_fast;
logic irq_nm; // non-maskeable interrupt
logic irq_nm; // non-maskable interrupt
clocking driver_cb @(posedge clk);
default output negedge;

2
dv/uvm/core_ibex/directed_tests/README.md
View file

@ -5,7 +5,7 @@ This directory contains the custom directed tests as well as scripts and headers
Currently following open source test suites are vendored:
- [riscv-tests](https://github.com/riscv-software-src/riscv-tests)
- [riscv-arch-tests](https://github.com/riscv-non-isa/riscv-arch-test)
- epmp-tests ([fork](https://github.com/lowRISC/riscv-isa-sim/tree/mseccfg_tests) from an opensource [repo](https://github.com/joxie/riscv-isa-sim))
- epmp-tests ([fork](https://github.com/lowRISC/riscv-isa-sim/tree/mseccfg_tests) from an open-source [repo](https://github.com/joxie/riscv-isa-sim))
## Generating test list

2
dv/uvm/core_ibex/directed_tests/gen_testlist.py
View file

@ -1,6 +1,6 @@
#!/usr/bin/env python3
"""
Generating testlists for following opensource test suites
Generating testlists for following open-source test suites
- riscv-tests
- riscv-arch-tests
- ePMP directed tests

2
dv/uvm/core_ibex/env/core_ibex_scoreboard.sv vendored
View file

@ -71,7 +71,7 @@ class core_ibex_scoreboard extends uvm_scoreboard;
end
end
// Latch the 'double_fault_seen_o' signal to catch the fault.
// The single pulse may be receieved sometime before the rvfi_seq_item
// The single pulse may be received sometime before the rvfi_seq_item
// corresponding to the faulting instruction is generated. Hence we
// latch that pulse when it is seen, and then reset above when the
// seq_item arrives.

2
dv/uvm/core_ibex/fcov/core_ibex_fcov_if.sv
View file

@ -310,7 +310,7 @@ interface core_ibex_fcov_if import ibex_pkg::*; (
assign instr_id_matches_trigger_d = id_stage_i.controller_i.trigger_match_i &&
id_stage_i.controller_i.fcov_debug_entry_if;
// Delay instruction matching trigger point since it is catched in IF stage.
// Delay instruction matching trigger point since it is cached in IF stage.
// We would want to cross it with decoded instruction categories and it does not matter
// when exactly we are hitting the condition.
always @(posedge clk_i or negedge rst_ni) begin

14
dv/uvm/core_ibex/fcov/core_ibex_pmp_fcov_if.sv
View file

@ -255,7 +255,7 @@ interface core_ibex_pmp_fcov_if import ibex_pkg::*; #(
csr_pmp_cfg[i_region].mode != PMP_MODE_OFF &&
!(fcov_access_attempted_into_dm[PMP_I])) {
// Will never see a succesful exec access when execute is disallowed
// Will never see a successful exec access when execute is disallowed
illegal_bins illegal_allow_exec =
// Ensuring MML is low and we are not in a X allowed configuration
(binsof(cp_region_priv_bits) intersect {NONE, R, W, WR, L, LR, LW, LWR} &&
@ -313,7 +313,7 @@ interface core_ibex_pmp_fcov_if import ibex_pkg::*; #(
csr_pmp_cfg[i_region].mode != PMP_MODE_OFF &&
!(fcov_access_attempted_into_dm[PMP_I2])) {
// Will never see a succesful exec access when execute is disallowed
// Will never see a successful exec access when execute is disallowed
illegal_bins illegal_allow_exec =
// Ensuring MML is low and we are not in a X allowed configuration
(binsof(cp_region_priv_bits) intersect {NONE, R, W, WR, L, LR, LW, LWR} &&
@ -371,7 +371,7 @@ interface core_ibex_pmp_fcov_if import ibex_pkg::*; #(
csr_pmp_cfg[i_region].mode != PMP_MODE_OFF &&
!(fcov_access_attempted_into_dm[PMP_D])) {
// Will never see a succesful read access when read is disallowed
// Will never see a successful read access when read is disallowed
illegal_bins illegal_allow_read =
// Ensuring MML is low and we are not in a R allowed configuration
(binsof(cp_region_priv_bits) intersect {NONE, W, X, XW, L, LW, LX, LXW} &&
@ -415,7 +415,7 @@ interface core_ibex_pmp_fcov_if import ibex_pkg::*; #(
binsof(cp_req_type_dside) intersect {PMP_ACC_READ} &&
binsof(pmp_dside_req_err) intersect {1});
// Will never see a succesful write access when write is disallowed
// Will never see a successful write access when write is disallowed
illegal_bins illegal_allow_write =
// Ensuring MML is low and we are not in a W allowed configuration
(binsof(cp_region_priv_bits) intersect {NONE, R, X, XR, L, LR, LX, LXR} &&
@ -613,7 +613,7 @@ interface core_ibex_pmp_fcov_if import ibex_pkg::*; #(
pmp_iside_nomatch_cross :
cross cp_req_type_iside, cp_priv_lvl_iside, pmp_iside_req_err, cp_mmwp, cp_mml
iff (pmp_iside_nomatch) {
// Will never see a succesful exec access when execute is disallowed
// Will never see a successful exec access when execute is disallowed
illegal_bins illegal_user_allow_exec =
// In User mode - no match case, we should always deny
(binsof(cp_priv_lvl_iside) intersect {PRIV_LVL_U} &&
@ -639,7 +639,7 @@ interface core_ibex_pmp_fcov_if import ibex_pkg::*; #(
pmp_iside2_nomatch_cross :
cross cp_req_type_iside2, cp_priv_lvl_iside2, pmp_iside2_req_err, cp_mmwp, cp_mml
iff (pmp_iside2_nomatch) {
// Will never see a succesful exec access when execute is disallowed
// Will never see a successful exec access when execute is disallowed
illegal_bins illegal_user_allow_exec =
// In User mode - no match case, we should always deny
(binsof(cp_priv_lvl_iside2) intersect {PRIV_LVL_U} &&
@ -666,7 +666,7 @@ interface core_ibex_pmp_fcov_if import ibex_pkg::*; #(
cross cp_req_type_dside, cp_priv_lvl_dside, pmp_dside_req_err, cp_mmwp, cp_mml
iff (pmp_dside_nomatch) {
// Will never see a succesful write/read access when it should be denied
// Will never see a successful write/read access when it should be denied
illegal_bins illegal_machine_allow_wr =
// Deny WR when MMWP = 1 in Machine mode
(binsof(cp_priv_lvl_dside) intersect {PRIV_LVL_M} &&

2
dv/uvm/core_ibex/riscv_dv_extension/ibex_asm_program_gen.sv
View file

@ -112,7 +112,7 @@ class ibex_asm_program_gen extends riscv_asm_program_gen;
endfunction
// Re-define gen_test_done() to override the base-class with an empty implementation.
// Then, our own overrided gen_program() can append new test_done code.
// Then, our own overriding gen_program() can append new test_done code.
virtual function void gen_test_done();
// empty
endfunction

2
dv/uvm/core_ibex/riscv_dv_extension/ibex_directed_instr_lib.sv
View file

@ -51,7 +51,7 @@ class ibex_breakpoint_stream extends riscv_directed_instr_stream;
la_instr.rd = cfg.gpr[1];
// Create the ebreak insn which will cause us to enter debug mode, and run the
// special code in the debugrom.
// special code in the debug ROM.
ebreak_insn = riscv_instr::get_instr(EBREAK);
// Add the instructions into the stream.

2
dv/uvm/core_ibex/riscv_dv_extension/ibex_log_to_trace_csv.py
View file

@ -206,7 +206,7 @@ def check_ibex_uvm_log(uvm_log):
# the test result so ignore any lines after the test result is seen for
# 'UVM_ERROR' checking. If the loop terminated immediately when a test
# result was seen it would miss issues where the test result is
# (erronously) repeated multiple times with different results.
# (erroneously) repeated multiple times with different results.
test_result_seen = False
for linenum, line in enumerate(log, 1):

4
dv/uvm/core_ibex/riscv_dv_extension/riscv_core_setting.tpl.sv
View file

@ -107,10 +107,10 @@ int kernel_stack_len = 5000;
int kernel_program_instr_cnt = 400;
// ----------------------------------------------------------------------------
// Previleged CSR implementation
// Privileged CSR implementation
// ----------------------------------------------------------------------------
// Implemented previlieged CSR list
// Implemented privileged CSR list
// TODO: Bring back commented out CSRs, these are currently removed as they can
// cause co-sim mismatches. These must be investigated and fixed
const privileged_reg_t implemented_csr[] = {

2
dv/uvm/core_ibex/scripts/compile_tb.py
View file

@ -24,7 +24,7 @@ logger = logging.getLogger(__name__)
def _get_iss_pkgconfig_flags(specifiers: List[str], iss_pc: List[str], simulator: str) -> str:
all_tokens = []
# Seperate pkg-config calls for each specifier as combining them has been
# Separate pkg-config calls for each specifier as combining them has been
# observed misbehaving on CentOS 7
# Generate a list of tokens for each call, and append it to the all_tokens variable
for s in specifiers:

2
dv/uvm/core_ibex/scripts/merge_cov.py
View file

@ -66,7 +66,7 @@ def merge_cov_xlm(md: RegressionMetadata, cov_dbs: Set[pathlib.Path]) -> int:
imc_cmd = ["imc", "-64bit", "-licqueue"]
# Update the metdadata file with the commands we're about to run
# Update the metadata file with the commands we're about to run
with LockedMetadata(md.dir_metadata, __file__) as md:
md.cov_merge_db_list = md.dir_cov / 'cov_db_runfile'

2
dv/uvm/core_ibex/scripts/report_lib/util.py
View file

@ -77,7 +77,7 @@ def parse_xcelium_cov_report(cov_report: str) -> Dict[str, Dict[str, Dict[str, i
}
The top-level dictionary gives per-module info. For each module coverage is
seperated into a number of metrics. Each metric can be one of two types:
separated into a number of metrics. Each metric can be one of two types:
1. covered - Two integers, 'total' giving total number of things to cover
and 'covered' giving the number that are covered.
2. average - Single integer, 'average' giving the average coverage

4
dv/uvm/core_ibex/scripts/scripts_lib.py
View file

@ -263,14 +263,14 @@ class testdata_cls():
"""Baseclass for testdata to hold common methods....
Objects inheriting from this can easily import/export
themselves to files, allowing data to gain continuinty between
themselves to files, allowing data to gain continuity between
different phases of the regression and testing process
"""
@classmethod
@typechecked
def construct_from_pickle(cls, metadata_pickle: pathlib.Path):
"""Allow easy contruction of the data-structure from a file."""
"""Allow easy construction of the data-structure from a file."""
trr = cls()
logger.debug(f"Constructing object from data in {metadata_pickle}")
with metadata_pickle.open('rb') as handle:

6
dv/uvm/core_ibex/tb/core_ibex_tb_top.sv
View file

@ -191,7 +191,7 @@ module core_ibex_tb_top;
// Data load/store vif connection
assign data_mem_vif.reset = ~rst_n;
// Instruction fetch vif connnection
// Instruction fetch vif connection
assign instr_mem_vif.reset = ~rst_n;
assign instr_mem_vif.we = 0;
assign instr_mem_vif.be = 0;
@ -368,13 +368,13 @@ module core_ibex_tb_top;
unused_assert_connected = 1;
end
// Disable the assertion for onhot check in case WrenCheck (set by SecureIbex) is enabled.
// Disable the assertion for onehot check in case WrenCheck (set by SecureIbex) is enabled.
if (SecureIbex) begin : gen_disable_onehot_check
assign dut.u_ibex_top.gen_regfile_ff.register_file_i.gen_wren_check.u_prim_onehot_check.
unused_assert_connected = 1;
end
// Disable the assertion for onhot check in case RdataMuxCheck (set by SecureIbex) is enabled.
// Disable the assertion for onehot check in case RdataMuxCheck (set by SecureIbex) is enabled.
if (SecureIbex) begin : gen_disable_rdata_mux_check
assign dut.u_ibex_top.gen_regfile_ff.register_file_i.gen_rdata_mux_check.
u_prim_onehot_check_raddr_a.unused_assert_connected = 1;

6
dv/uvm/core_ibex/tests/core_ibex_base_test.sv
View file

@ -23,7 +23,7 @@ class core_ibex_base_test extends uvm_test;
int unsigned timeout_in_cycles = 100000000;
int unsigned max_quit_count = 1;
// If no signature_addr handshake functionality is desired between the testbench and the generated
// code, the test will wait for the specifield number of cycles before starting stimulus
// code, the test will wait for the specified number of cycles before starting stimulus
// sequences (irq and debug)
int unsigned stimulus_delay = 800;
bit[ibex_mem_intf_agent_pkg::DATA_WIDTH-1:0] signature_data_q[$];
@ -171,7 +171,7 @@ class core_ibex_base_test extends uvm_test;
void'($value$plusargs("disable_spurious_dside_responses=%0d",
disable_spurious_dside_responses));
// Disable spurious reponses for non secure configs or when disabled through plusarg
// Disable spurious responses for non secure configs or when disabled through plusarg
if ((secure_ibex == 0) || disable_spurious_dside_responses) begin
cfg.enable_spurious_dside_responses = 0;
end
@ -277,7 +277,7 @@ class core_ibex_base_test extends uvm_test;
end
endtask : handle_reset
// Watch for all of the different critera for test pass/failure here
// Watch for all of the different criteria for test pass/failure here
virtual task wait_for_test_done();
longint timeout_timestamp, ts;
bit result;

4
dv/uvm/core_ibex/tests/core_ibex_new_seq_lib.sv
View file

@ -52,7 +52,7 @@ class core_base_new_seq #(type REQ = uvm_sequence_item) extends uvm_sequence #(R
endfunction
virtual task pre_body();
// Randomize once before starting to ensure all unininitialized rand variables have a valid starting value
// Randomize once before starting to ensure all uninitialized rand variables have a valid starting value
this.randomize();
endtask: pre_body
@ -204,7 +204,7 @@ endclass
class memory_error_seq extends core_base_new_seq#(ibex_mem_intf_seq_item);
core_ibex_vseq vseq;
rand bit choose_side;
// When set skip error injection if Ibex is currently handling an exception (incluing IRQs)
// When set skip error injection if Ibex is currently handling an exception (including IRQs)
bit skip_on_exc = 1'b0;
error_type_e err_type = PickErr;

2
dv/uvm/core_ibex/tests/core_ibex_test_lib.sv
View file

@ -1860,7 +1860,7 @@ class core_ibex_mem_error_test extends core_ibex_directed_test;
//
// We don't terminate immediately as sometimes the test hits an illegal instruction exception
// but finds its way back to generated code and terminates as usual. Sometimes it doesn't. The
// treshold allows for normal test termination in cases where that's possible.
// threshold allows for normal test termination in cases where that's possible.
if (!cfg.enable_mem_intg_err) begin
return;
end

2
dv/uvm/icache/dv/env/ibex_icache_env_cov.sv vendored
View file

@ -3,7 +3,7 @@
// SPDX-License-Identifier: Apache-2.0
/**
* Covergoups that are dependent on run-time parameters that may be available
* Covergroups that are dependent on run-time parameters that may be available
* only in build_phase can be defined here
* Covergroups may also be wrapped inside helper classes if needed.
*/

2
dv/uvm/icache/dv/ibex_icache_core_agent/ibex_icache_core_monitor.sv
View file

@ -34,7 +34,7 @@ class ibex_icache_core_monitor extends dv_base_monitor #(
disable fork;
endtask
// collect transactions forever - already forked in dv_base_moditor::run_phase
// collect transactions forever - already forked in dv_base_monitor::run_phase
virtual protected task collect_trans();
ibex_icache_core_bus_item trans;
logic last_inval = 0;

2
dv/uvm/icache/dv/prim_badbit/README.md
View file

@ -1,7 +1,7 @@
Badbit RAM
==========
This is an SRAM wrapper that allows a testbench to force bit errors onthe read interface.
This is an SRAM wrapper that allows a testbench to force bit errors on the read interface.
This works as a dummy technology library.
Instantiate it by adding setting `PRIM_DEFAULT_IMPL` to prim_pkg::ImplBadbit (see the README.md in the prim directory for details).

6
dv/verilator/simple_system_cosim/README.md
View file

@ -3,7 +3,7 @@
This augments the Ibex Simple System (`examples/simple_system`) to include the
co-simulation system to check Ibex's execution. This runs Spike in lockstep with
Ibex and checks each instruction Ibex retires matches what Spike has executed.
In addition all data memory accesses are checked against memory acceses Spike
In addition all data memory accesses are checked against memory accesses Spike
has performed. More details on how the co-simulation works and how to build and
run simple system with it included can be in found in the Ibex documentation
under 'Co-simulation System' in the 'Ibex Reference Guide' section.
@ -20,7 +20,7 @@ mkdir build
cd build
# Configure and build spike
../configure --enable-commitlog --enable-misaligned --prefix=/opt/spike-cosim
../configure --enable-commitlog --enable-misaligned --prefix=/opt/spike-cosim
# Installs in /opt/spike-cosim
sudo make -j8 install
@ -33,7 +33,7 @@ cd <ibex_repo>
# Build simulator
fusesoc --cores-root=. run --target=sim --setup --build lowrisc:ibex:ibex_simple_system_cosim --RV32E=0 --RV32M=ibex_pkg::RV32MFast
# Build coremark test binary, with performance counter dump disabled. The
# Build coremark test binary, with performance counter dump disabled. The
# co-simulator system doesn't produce matching performance counters in spike so
# any read of those CSRs results in a mismatch and a failure.
make -C ./examples/sw/benchmarks/coremark SUPPRESS_PCOUNT_DUMP=1