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Delay simulator finish

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The tracer needs time to log the final instruction.
Introduce a counter to delay calling the simulation finish.

Fixes lowrisc/ibex#468
This commit is contained in:
Tobias Wölfel 2019-11-13 15:56:09 +01:00 • committed by Philipp Wagner
parent 9738b6c703
commit 6be1e8aff3
1 changed files with 12 additions and 2 deletions
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14
shared/rtl/sim/simulator_ctrl.sv
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@ -36,6 +36,7 @@ module simulator_ctrl #(
localparam SIM_CTRL_ADDR = 1; localparam SIM_CTRL_ADDR = 1;
logic [7:0] ctrl_addr; logic [7:0] ctrl_addr;
logic [2:0] sim_finish;
integer log_fd; integer log_fd;
@ -52,6 +53,7 @@ module simulator_ctrl #(
always_ff @(posedge clk_i or negedge rst_ni) begin always_ff @(posedge clk_i or negedge rst_ni) begin
if (~rst_ni) begin if (~rst_ni) begin
rvalid_o <= 0; rvalid_o <= 0;
sim_finish <= 'b0;
end else begin end else begin
// Immeditely respond to any request // Immeditely respond to any request
rvalid_o <= req_i; rvalid_o <= req_i;
@ -68,9 +70,9 @@ module simulator_ctrl #(
end end
end end
SIM_CTRL_ADDR: begin SIM_CTRL_ADDR: begin
if (be_i[0] & wdata_i[0]) begin if ((be_i[0] & wdata_i[0]) && (sim_finish == 'b0)) begin
$display("Terminating simulation by software request."); $display("Terminating simulation by software request.");
$finish; sim_finish <= 3'b001;
end end
end end
endcase endcase
@ -78,6 +80,14 @@ module simulator_ctrl #(
end end
end end
always_ff @(posedge clk_i or negedge rst_ni) begin
if (sim_finish != 'b0) begin
sim_finish <= sim_finish + 1;
end
if (sim_finish >= 3'b010) begin
$finish;
end
end
assign rdata_o = '0; assign rdata_o = '0;
endmodule endmodule