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Fix ack handling in IF
This commit is contained in:
Sven Stucki
parent
67425b0f19
commit
6f5367478f
2 changed files with 99 additions and 28 deletions
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@ -1219,7 +1219,7 @@ module controller
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// we unstall the if_stage if the debug unit wants to set a new
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// pc, so that the new value gets written into current_pc_if and is
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// used by the instr_core_interface
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stall_if_o = instr_ack_stall | load_stall | jr_stall | lsu_stall | misalign_stall | dbg_halt | dbg_stall_i | (~pc_valid_i);
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stall_if_o = /*instr_ack_stall |*/ load_stall | jr_stall | lsu_stall | misalign_stall | dbg_halt | dbg_stall_i | (~pc_valid_i);
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stall_id_o = instr_ack_stall | load_stall | jr_stall | lsu_stall | misalign_stall | dbg_halt | dbg_stall_i;
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stall_ex_o = instr_ack_stall | lsu_stall | dbg_stall_i;
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stall_wb_o = lsu_stall | dbg_stall_i;
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125
if_stage.sv
125
if_stage.sv
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@ -91,7 +91,6 @@ module if_stage
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logic sample_addr;
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logic [1:0] is_compressed;
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logic [31:0] fetch_addr, fetch_addr_n;
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logic [31:0] last_fetch_addr;
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@ -103,9 +102,13 @@ module if_stage
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// instr_core_interface
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logic req_int;
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logic ack_int;
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logic [31:0] rdata_int;
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logic fetch_ack;
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logic [31:0] fetch_addr, fetch_addr_n;
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// stall ack logic
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logic ack_stalled, ack_stalled_n;
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logic ack_int;
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// local cache
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logic [31:0] data_tag;
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@ -146,7 +149,7 @@ module if_stage
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data_tag <= '0;
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data_arr <= 32'h0003;
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end else begin
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if (ack_int) begin
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if (fetch_ack) begin
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data_tag <= last_fetch_addr;
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data_arr[1] <= data_arr[0];
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data_arr[0] <= rdata_int;
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@ -189,15 +192,42 @@ module if_stage
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assign current_pc_if_o = last_fetch_addr + (pc_if_offset? 32'd2 : 32'd0);
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always_ff @(posedge clk, negedge rst_n)
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begin
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if (rst_n == 1'b0)
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ack_stalled <= 1'b0;
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else
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ack_stalled <= ack_stalled_n;
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end
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// handshake to stall logic: keep ack asserted as long as ID is stalled
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// (do not accept new requests while IF/ID stalled)
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always_comb
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begin
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ack_stalled_n = ack_stalled;
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ack_o = ack_int;
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bypass_data_reg = 1'b1;
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if (ack_stalled) begin
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ack_o = 1'b1;
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bypass_data_reg = 1'b0;
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if (stall_id_i == 1'b0)
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ack_stalled_n = 1'b0;
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end else begin
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if (ack_int && stall_id_i)
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ack_stalled_n = 1'b1;
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end
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end
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always_comb
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begin
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fetch_fsm_ns = fetch_fsm_cs;
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pc_if_offset_n = pc_if_offset;
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force_nop_int = 1'b0;
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bypass_data_reg = 1'b1;
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sample_addr = 1'b0;
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ack_o = 1'b0;
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ack_int = 1'b0;
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req_int = 1'b0;
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fetch_addr_n = {next_pc[31:2], 2'b0};
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@ -206,25 +236,72 @@ module if_stage
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begin
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sample_addr = 1'b0;
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if (req_i)
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fetch_fsm_ns = WAIT_REQ;
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fetch_fsm_ns = START_REQ;
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end
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WAIT_REQ,
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// fetch word at fetch addr and start serving requests
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START_REQ: begin
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req_int = 1'b1;
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sample_addr = 1'b1;
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fetch_fsm_ns = WAIT_ACK;
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end
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// WAIT_REQ:
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// - fetch_addr contains current IF PC
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// - last_fetch_addr: current IF PC (i.e. data valid)
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WAIT_REQ:
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begin
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if (stall_if_i == 1'b0 && req_i) begin
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if (pc_if_offset) begin
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if (is_compressed[1]) begin
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// serve second part of fetched instruction and request next
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sample_addr = 1'b1;
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req_int = 1'b1;
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ack_int = 1'b1;
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pc_if_offset_n = 1'b0;
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fetch_fsm_ns = WAIT_ACK;
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end else begin
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// cross line access
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// .. need to fetch next word here and delay everything till then
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sample_addr = 1'b1;
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req_int = 1'b1;
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ack_int = 1'b0;
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fetch_fsm_ns = FETCH_NEXT;
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end
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end else begin
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if (is_compressed[0]) begin
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// compressed instruction, only increase PC by two bytes
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sample_addr = 1'b0;
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req_int = 1'b0;
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ack_int = 1'b1;
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pc_if_offset_n = 1'b1;
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fetch_fsm_ns = WAIT_REQ;
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end else begin
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// aligned 32 bit instruction
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sample_addr = 1'b1;
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req_int = 1'b1;
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ack_int = 1'b1;
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fetch_fsm_ns = WAIT_ACK;
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end
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end
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end
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end
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//WAIT_REQ,
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WAIT_ACK:
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begin
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if (fetch_fsm_cs == WAIT_ACK) begin
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fetch_fsm_ns = WAIT_ACK;
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sample_addr = 1'b0;
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//req_int = 1'b1; // keep req_int asserted or start request (for branches) TODO: remove
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if (ack_int) begin
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if (fetch_ack) begin
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req_int = 1'b0;
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ack_o = 1'b1;
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ack_int = 1'b1;
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fetch_fsm_ns = WAIT_REQ;
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end
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end
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// handle requests
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if (fetch_fsm_cs == WAIT_REQ || ack_int) begin
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if (stall_if_i == 1'b0 && (fetch_fsm_cs == WAIT_REQ || fetch_ack)) begin
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if (req_i) begin
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fetch_fsm_ns = WAIT_ACK;
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req_int = 1'b1;
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@ -233,7 +310,7 @@ module if_stage
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if (is_compressed[1]) begin
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// serve second part of fetched instruction and request next
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pc_if_offset_n = 1'b0;
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ack_o = 1'b1;
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ack_int = 1'b1;
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sample_addr = 1'b1;
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fetch_fsm_ns = WAIT_ACK;
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end else begin
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@ -247,7 +324,7 @@ module if_stage
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// compressed instruction, only increase PC by two bytes
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sample_addr = 1'b0;
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req_int = 1'b0;
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ack_o = 1'b1;
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ack_int = 1'b1;
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pc_if_offset_n = 1'b1;
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fetch_fsm_ns = WAIT_REQ;
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end else begin
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@ -268,7 +345,7 @@ module if_stage
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req_int = 1'b0;
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// insert NOPs and wait for valid target
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force_nop_int = 1'b1;
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ack_o = 1'b1;
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ack_int = 1'b1;
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fetch_fsm_ns = HANDLE_BRANCH;
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end
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end
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@ -279,7 +356,7 @@ module if_stage
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// insert NOPs until branch arrives in EX
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// TODO: probably not needed
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force_nop_int = 1'b1;
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ack_o = req_i;
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ack_int = req_i;
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end else begin
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if (jump_in_ex_i == `BRANCH_COND && branch_decision_i == 1'b0) begin
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// branch not taken, continue as before
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@ -301,12 +378,6 @@ module if_stage
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end
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end
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START_REQ: begin
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req_int = 1'b1;
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sample_addr = 1'b1;
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fetch_fsm_ns = WAIT_ACK;
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end
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//START_REQ, FETCH:
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FETCH:
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begin
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@ -316,7 +387,7 @@ module if_stage
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fetch_fsm_ns = FETCH;
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end
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if (ack_int) begin
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if (fetch_ack) begin
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req_int = 1'b0;
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fetch_fsm_ns = WAIT_REQ;
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@ -328,7 +399,7 @@ module if_stage
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if (is_compressed[1]) begin
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// serve second part of fetched instruction and request next
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pc_if_offset_n = 1'b0;
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ack_o = 1'b1;
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ack_int = 1'b1;
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sample_addr = 1'b1;
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fetch_fsm_ns = WAIT_ACK;
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end else begin
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@ -342,7 +413,7 @@ module if_stage
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// compressed instruction, only increase PC by two bytes
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sample_addr = 1'b0;
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req_int = 1'b0;
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ack_o = 1'b1;
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ack_int = 1'b1;
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pc_if_offset_n = 1'b1;
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fetch_fsm_ns = WAIT_REQ;
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end else begin
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@ -360,8 +431,8 @@ module if_stage
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FETCH_NEXT:
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begin
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sample_addr = 1'b0;
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if (ack_int) begin
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ack_o = 1'b1;
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if (fetch_ack) begin
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ack_int = 1'b1;
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fetch_fsm_ns = WAIT_REQ;
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end
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end
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@ -426,7 +497,7 @@ module if_stage
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.rst_n ( rst_n ),
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.req_i ( req_int ),
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.ack_o ( ack_int ),
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.ack_o ( fetch_ack ),
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.addr_i ( fetch_addr ),
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.rdata_o ( rdata_int ),
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