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https://github.com/lowRISC/ibex.git
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Rename instr_core_intf to prefetch_buffer, add if_busy signal again
This commit is contained in:
Andreas Traber
parent
84ea2c90ee
commit
6fb05eab34
4 changed files with 44 additions and 61 deletions
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@ -959,7 +959,7 @@ module controller
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// Default values
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instr_req_o = 1'b1;
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pc_mux_sel_o = `PC_INCR;
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pc_mux_sel_o = `PC_BOOT;
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ctrl_fsm_ns = ctrl_fsm_cs;
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31
if_stage.sv
31
if_stage.sv
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@ -96,7 +96,8 @@ module if_stage
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logic unaligned;
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logic unaligned_jump;
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// instr_core_interface
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// prefetch buffer related signals
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logic prefetch_busy;
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logic branch_req, branch_req_Q;
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logic [31:0] fetch_addr_n;
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@ -151,15 +152,13 @@ module if_stage
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`PC_BOOT: fetch_addr_n = {boot_addr_i[31:5], `EXC_OFF_RST};
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`PC_JUMP: fetch_addr_n = {jump_target_id_i[31:2], 2'b0};
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`PC_BRANCH: fetch_addr_n = {jump_target_ex_i[31:2], 2'b0};
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// TODO: remove the next entry
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`PC_INCR: fetch_addr_n = 'X; // no longer needed, remove!
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`PC_EXCEPTION: fetch_addr_n = exc_pc; // set PC to exception handler
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`PC_ERET: fetch_addr_n = exception_pc_reg_i; // PC is restored when returning from IRQ/exception
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`PC_HWLOOP: fetch_addr_n = hwloop_target_i; // PC is taken from hwloop start addr
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`PC_DBG_NPC: fetch_addr_n = dbg_npc_i; // PC is taken from debug unit
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default:
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begin
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fetch_addr_n = {boot_addr_i[31:5], `EXC_OFF_RST};
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fetch_addr_n = 'X;
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// synopsys translate_off
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$display("%t: Illegal pc_mux_sel value (%0d)!", $time, pc_mux_sel_i);
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// synopsys translate_on
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@ -181,14 +180,14 @@ module if_stage
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end
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// cache fetch interface
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instr_core_interface instr_core_if_i
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// prefetch buffer, caches a fixed number of instructions
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prefetch_buffer prefetch_buffer_i
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(
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.clk ( clk ),
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.rst_n ( rst_n ),
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.req_i ( 1'b1 ),
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.clear_i ( branch_req ),
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.req_i ( 1'b1 ), // TODO: FETCH_ENABLE!
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.branch_i ( branch_req ),
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.addr_i ( fetch_addr_n ),
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.ready_i ( fetch_ready ),
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@ -199,11 +198,15 @@ module if_stage
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.unaligned_valid_o ( fetch_unaligned_valid ),
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.unaligned_rdata_o ( fetch_unaligned_rdata ),
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// goes to instruction memory / instruction cache
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.instr_req_o ( instr_req_o ),
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.instr_addr_o ( instr_addr_o ),
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.instr_gnt_i ( instr_gnt_i ),
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.instr_rvalid_i ( instr_rvalid_i ),
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.instr_rdata_i ( instr_rdata_i )
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.instr_rdata_i ( instr_rdata_i ),
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// Prefetch Buffer Status
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.busy_o ( prefetch_busy )
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);
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@ -303,6 +306,7 @@ module if_stage
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// take care of jumps and branches
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// only send one branch request per jump/branch
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if (branch_req_Q == 1'b0) begin
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if (jump_in_ex_i == `BRANCH_COND) begin
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if (branch_decision_i) begin
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@ -331,14 +335,7 @@ module if_stage
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end
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assign if_busy_o = 1'b1; // TODO
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// assign if_busy_o = ~(offset_fsm_cs == IDLE ||
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// offset_fsm_cs == VALID_JUMPED_ALIGNED ||
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// offset_fsm_cs == VALID_JUMPED_UNALIGNED ||
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// offset_fsm_cs == VALID_ALIGNED ||
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// offset_fsm_cs == VALID_UNALIGNED_32 ||
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// offset_fsm_cs == UNALIGNED_16) || instr_req_o;
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assign if_busy_o = prefetch_busy;
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// compressed instruction decoding, or more precisely compressed instruction
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@ -359,7 +359,6 @@ endfunction // prettyPrintInstruction
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// PC mux selector defines
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`define PC_BOOT 3'b000
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`define PC_INCR 3'b001
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`define PC_JUMP 3'b010
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`define PC_BRANCH 3'b011
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`define PC_EXCEPTION 3'b100
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@ -2,19 +2,19 @@
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// Company: IIS @ ETHZ - Federal Institute of Technology //
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// DEI @ UNIBO - University of Bologna //
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// //
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// Engineer: Igor Loi - igor.loi@unibo.it //
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// Engineer: Andreas Traber - atraber@iis.ee.ethz.ch //
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// //
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// Additional contributions by: //
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// //
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// //
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// Create Date: 06/08/2014 //
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// Design Name: RISC-V processor core //
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// Module Name: instr_core_interface.sv //
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// Module Name: prefetch_buffer.sv //
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// Project Name: RI5CY //
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// Language: SystemVerilog //
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// //
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// Description: Instruction Fetch interface used to properly handle //
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// cache stalls //
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// Description: Prefetch Buffer that caches instructions. This cuts overly //
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// long critical paths to the instruction cache //
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// //
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// Revision: //
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// Revision v0.1 - File Created //
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@ -191,15 +191,15 @@ module fetch_fifo
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endmodule
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// clear_i deletes everything up to now, i.e. it assumes that addr_i now has
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// branch_i deletes everything up to now, i.e. it assumes that addr_i now has
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// the correct state and uses the current cycle's addr_i to fetch new data
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module instr_core_interface
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module prefetch_buffer
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(
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input logic clk,
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input logic rst_n,
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input logic req_i,
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input logic clear_i,
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input logic branch_i,
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input logic ready_i,
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input logic [31:0] addr_i,
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@ -215,12 +215,11 @@ module instr_core_interface
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output logic [31:0] instr_addr_o,
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input logic instr_gnt_i,
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input logic instr_rvalid_i,
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input logic [31:0] instr_rdata_i
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);
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input logic [31:0] instr_rdata_i,
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// TODO: THERE IS A PROBLEM WIHT REQ_I AND CLEAR_I
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// i.e. what happens if req_i is low and clear_i is high? the core will miss
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// the updated address....
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// Prefetch Buffer Status
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output logic busy_o
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);
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enum logic [1:0] {IDLE, WAIT_GNT, WAIT_RVALID, WAIT_ABORTED } CS, NS;
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@ -233,12 +232,17 @@ module instr_core_interface
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logic fifo_rdata_valid;
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logic fifo_rdata_ready;
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//////////////////////////////////////////////////////////////////////////////
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// prefetch buffer status
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//////////////////////////////////////////////////////////////////////////////
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assign busy_o = (CS != IDLE) || instr_req_o;
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//////////////////////////////////////////////////////////////////////////////
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// address selection and increase
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//////////////////////////////////////////////////////////////////////////////
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assign addr_next = (clear_i) ? addr_i : (fifo_last_addr + 32'd4);
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assign addr_next = (branch_i) ? addr_i : (fifo_last_addr + 32'd4);
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//////////////////////////////////////////////////////////////////////////////
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@ -251,7 +255,7 @@ module instr_core_interface
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.clk ( clk ),
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.rst_n ( rst_n ),
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.clear_i ( clear_i ),
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.clear_i ( branch_i ),
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.in_addr_valid_i ( fifo_addr_valid ),
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.in_addr_ready_o ( fifo_addr_ready ),
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@ -291,7 +295,7 @@ module instr_core_interface
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begin
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instr_req_o = 1'b0;
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if (req_i && fifo_addr_ready) begin
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if ((req_i && fifo_addr_ready) || branch_i) begin
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instr_req_o = 1'b1;
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fifo_addr_valid = 1'b1;
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@ -307,43 +311,26 @@ module instr_core_interface
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// we sent a request but did not yet get a grant
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WAIT_GNT:
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begin
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instr_req_o = 1'b1;
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if (clear_i) begin
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if (branch_i) begin
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instr_addr_o = addr_next;
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if (req_i && fifo_addr_ready) begin
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instr_req_o = 1'b1;
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fifo_addr_valid = 1'b1;
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if(instr_gnt_i) //~> granted request
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NS = WAIT_ABORTED;
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else begin //~> got a request but no grant
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NS = WAIT_GNT;
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end
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end else begin
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if(instr_gnt_i) //~> granted request
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NS = WAIT_ABORTED;
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else begin //~> got a request but no grant
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NS = IDLE;
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end
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end
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fifo_addr_valid = 1'b1;
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end else begin
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instr_req_o = 1'b1;
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instr_addr_o = fifo_last_addr;
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if(instr_gnt_i)
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NS = WAIT_RVALID;
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else
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NS = WAIT_GNT;
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end
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if(instr_gnt_i)
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NS = WAIT_RVALID;
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else
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NS = WAIT_GNT;
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end // case: WAIT_GNT
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// we wait for rvalid, after that we are ready to serve a new request
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WAIT_RVALID: begin
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if ((req_i && fifo_addr_ready) || clear_i) begin
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if ((req_i && fifo_addr_ready) || branch_i) begin
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// prepare for next request
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instr_req_o = 1'b1;
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@ -359,7 +346,7 @@ module instr_core_interface
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end else begin
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// we are requested to abort our current request
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// we didn't get an rvalid yet, so wait for it
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if (clear_i) begin
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if (branch_i) begin
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fifo_addr_valid = 1'b1;
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NS = WAIT_ABORTED;
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end
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